From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Thu, 25 Apr 2013 13:33:35 +0000 (+0200)
Subject: Fixed some undefined references in CTS docu
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2df9059f3e1c1aa81e53e94d35627ad17718347a;p=daqdocu.git

Fixed some undefined references in CTS docu
---

diff --git a/.gitignore b/.gitignore
index 5a5e359..b8749d0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,4 @@
 *.bbl
 *.blg
 *.prv_auto
+*.fdb_latexmk
diff --git a/trb3/CtsBuildingBlocks.tex b/trb3/CtsBuildingBlocks.tex
index d3207da..739d15b 100644
--- a/trb3/CtsBuildingBlocks.tex
+++ b/trb3/CtsBuildingBlocks.tex
@@ -10,7 +10,8 @@
 
    In order to increase the hardware independence of the design, the CTS consists of two major
    building blocks: The \emph{Network Logic} handles the network interfaces (which are not part of the CTS design itself)
-   and propagates event information gathered by the \emph{Trigger Logic} (see figure~\ref{fig:cts_structural_overview}).
+   and propagates event information gathered by the \emph{Trigger
+     Logic} (see figure~\ref{fig:cts_structural_overview}).
    
 \subsection{CTS Network Logic}
    The CTS uses two dedicated network endpoints for communications: The \emph{CTS Endpoint} is obviously needed due to
@@ -104,7 +105,8 @@
          0x2a & \texttt{0x35c3e3e1} & Timestamp \\\hline
             \multicolumn{3}{c}{End of CTS Data. Remaining words are from External Trigger Logic}\\\hline
          
-         0x2b & \texttt{0x10000000} & CBM-MBS word (see table \ref{tab:cts_cbm_data_word}) \\\hline
+         0x2b & \texttt{0x10000000} & External trigger module word %(see table \ref{tab:cts_cbm_data_word}) 
+         \\\hline
       \end{tabular}
       
       \caption{Example of CTS Package.  The data in the subsubevent appears in the same order as the
@@ -211,11 +213,11 @@
    generate pseudo random numbers (PRN). If multiple instance of the pulser are synthesised with different constants. As
    simulations suggest, the values generated are nearly uniform deviates.
    Furthermore, the distance between two successive numbers is also distributed almost uniformly and
-   seems to be uncorrelated to their magnitude (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}).
+   seems to be uncorrelated to their magnitude. % (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}).
 
    In each clock cycle a random number is compared with a configurable threshold. If it is smaller, an event
    is produced. Since the numbers are uniform deviates, the average duty cycle of the pulser is given
-   by the threshold divided by the maximum value possible (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}a).
+   by the threshold divided by the maximum value possible. % (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}a).
    In addition, the uniformly distributed distances prevent the clustering of events that can be observed with
    other pseudorandom number generators, such as linear feedback shift registers.
 
diff --git a/trb3/CtsGettingStarted.tex b/trb3/CtsGettingStarted.tex
index 0210e65..0674c0e 100644
--- a/trb3/CtsGettingStarted.tex
+++ b/trb3/CtsGettingStarted.tex
@@ -1,3 +1,4 @@
+
 \subsubsection{Building the design}
    no content yet
    
diff --git a/trb3/CtsSlowControl.tex b/trb3/CtsSlowControl.tex
index 5249f75..5c0ee35 100644
--- a/trb3/CtsSlowControl.tex
+++ b/trb3/CtsSlowControl.tex
@@ -176,7 +176,7 @@
       dependency between the average trigger rate $F$ and the threshold $T$ given by
       $F(T) = \frac{ 100\text{~MHz} } {2^{32} - 1} \cdot T$.
 
-      \item \textbf{\addr{0x60} External logic- CBM/MBS}. This module indicates the presence of the CBM adapter
+      \item \textbf{\addr{0x60} External logic - CBM/MBS}. This module indicates the presence of the CBM adapter
       module. If set, the lowest bit of the control registers prevents the module from sending data to the
       event builder. The lower 24~bit of the status register contains the timestamp of the last event seen. The
       MSB holds the error flag.
diff --git a/trb3/biblio.bib b/trb3/biblio.bib
index 5188bb3..89dd600 100644
--- a/trb3/biblio.bib
+++ b/trb3/biblio.bib
@@ -48,3 +48,13 @@
   year		= "2009",
   url		= "http://www.latticesemi.com/documents/HB1003.pdf"
 }
+
+@Misc{penschuck12,
+  author =       {Penschuck, Manuel},
+  title =        {Development and Implementation of
+a Central Trigger System for TrbNet-based systems},
+  howpublished =       {Bachelor Thesis, Uni Frankfurt},
+  year =         2012,
+}
+
+
diff --git a/trb3/main.pdf b/trb3/main.pdf
index 86d3f36..8c75710 100644
Binary files a/trb3/main.pdf and b/trb3/main.pdf differ
diff --git a/trb3/main.tex b/trb3/main.tex
index 8225363..7df4996 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -193,10 +193,10 @@
   \section[CTS]{CTS\footnote{If not explicitly stated otherwise, in this chapter, CTS refers to the trigger system embeddable into the central
    FPGA of a TRB3.}}
     \subsection{Features}
-      \input{CtsFeatures}
-    %\subsection{Software}
-    %  \input{CtsGettingStarted}
-    %\subsection{Building Blocks}
+    \input{CtsFeatures}
+    \subsection{Getting Started}
+    \input{CtsGettingStarted}
+    \subsection{Building Blocks}
       \input{CtsBuildingBlocks}
     \subsection{Slow Control Registers}
       \input{CtsSlowControl}