From: Andreas Neiser Date: Fri, 6 Feb 2015 17:43:32 +0000 (+0100) Subject: Little improvements for simulation X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2e2ac91a5a96a597683b37d66ee3803f0bebc513;p=trb3.git Little improvements for simulation --- diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd index b50e4f6..43a3567 100644 --- a/ADC/source/adc_processor.vhd +++ b/ADC/source/adc_processor.vhd @@ -114,7 +114,7 @@ architecture adc_processor_arch of adc_processor is signal channelselect, last_channelselect, channelselect_valid : integer range 0 to 3 := 0; signal prepare_header, last_prepare_header, prepare_header_valid : std_logic := '0'; signal blockcurrent, last_blockcurrent : integer range 0 to 3 := 0; - signal myavg : unsigned(7 downto 0); + signal myavg : unsigned(7 downto 0) := (others => '0'); signal ram_read_rdo : std_logic_vector(CHANNELS - 1 downto 0) := (others => '0'); signal psa_data_i : std_logic_vector(8 downto 0); @@ -914,6 +914,7 @@ begin cfd_state <= CFD_WRITE_READCOUNT; when CFD_WRITE_READCOUNT => + report "CFD ch=" & integer'image(ch) & ": zero=" & integer'image(readcount_zerox) severity note; RDO_write_cfd <= '1'; RDO_data_cfd <= std_logic_vector(to_unsigned(readcount_zerox, RDO_data_cfd'length)); cfd_state <= CFD_WRITE_ZEROX1;