From: Peter Lemmens Date: Thu, 8 Jan 2015 14:58:59 +0000 (+0100) Subject: Collaboration commit. Project soda_hub.ldf is now compiling again. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2e948d583e5dbfb269714e3da677ea0c370b7c81;p=soda.git Collaboration commit. Project soda_hub.ldf is now compiling again. --- diff --git a/SODA_addressmap b/SODA_addressmap new file mode 100644 index 0000000..673248b --- /dev/null +++ b/SODA_addressmap @@ -0,0 +1,61 @@ +SODA_SOURCE (0xF355) +++++++++++++++++++++ +WRITE_REG: + +BE00 soda_cmd_word_S +BE01 LEDregister_i + +READ_REG: + +BE00 soda_cmd_word_S +BE01 super_burst_nr_S +BE02 calib_register_S +BE03 CTRL_STATUS_register_i + +control(read & write): +CTRL_STATUS_register_i[3..0] : LEDs +CTRL_STATUS_register_i[8] : dead_channel +CTRL_STATUS_register_i[15] : reset errors +status(read-only): +CTRL_STATUS_register_i[17] : timeout-error +CTRL_STATUS_register_i[18] : downstream-error +CTRL_STATUS_register_i[31] : report error + + +SODA_CLIENT (0xF356) +++++++++++++++++++++ +WRITE_REG: + +BE00 LEDregister_i + +READ_REG: + +BE00 soda_cmd_word_S +BE01 super_burst_nr_S +BE02 LEDregister_i +BE03 Debug_status +BE04 Debug_RX_count +BE05 Debug_TX_count +BE06 Debug_SOS_count +BE07 Debug_CMD_count + + + + +DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK); +DEBUG_STATUS(30) <= '0'; +DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK); +DEBUG_STATUS(28) <= '0'; +DEBUG_STATUS(27) <= '0'; +DEBUG_STATUS(26) <= rx_allow; +DEBUG_STATUS(25) <= tx_allow; +DEBUG_STATUS(24:20) <= (others => '0'); +DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; +DEBUG_STATUS(15:3) <= (others => '0'); +DEBUG_STATUS(2) <= CLK_EN; +DEBUG_STATUS(1) <= CLEAR; +DEBUG_STATUS(0) <= RESET; + + + + diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index 8fa4235..c13f970 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -65,8 +65,8 @@ entity med_ecp3_sfp_4_sync_down is SCI_ACK : out std_logic := '0'; SCI_NACK : out std_logic := '0'; -- Status and control port --- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); --- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); + STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); + CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ); diff --git a/ctsc.ldf b/ctsc.ldf index 84844b3..1b768a3 100644 --- a/ctsc.ldf +++ b/ctsc.ldf @@ -2,7 +2,7 @@ - + diff --git a/soda_client.ldf b/soda_client.ldf index eac63f0..554b219 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -320,9 +320,6 @@ - - - diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl index 2caca96..678f7a0 100644 --- a/soda_client_probe.rvl +++ b/soda_client_probe.rvl @@ -1,7 +1,7 @@ - + - + @@ -87,16 +87,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/soda_hub.ldf b/soda_hub.ldf index d18c856..cf522c4 100644 --- a/soda_hub.ldf +++ b/soda_hub.ldf @@ -1,5 +1,5 @@ - + diff --git a/soda_hub.lpf b/soda_hub.lpf index 5f8e0a5..81e3704 100644 --- a/soda_hub.lpf +++ b/soda_hub.lpf @@ -1,45 +1,46 @@ -rvl_alias "rxup_full_clk" "the_hub_sync_uplink/rx_full_clk_out"; -RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk"; -RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk"; -RVL_ALIAS "reveal_ist_577" "the_hub_sync_downlink/the_serdes/rx_full_clk_ch0"; +rvl_alias "rxup_full_clk" "rxup_full_clk"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; ################################################################# # Basic Settings ################################################################# -SYSCONFIG MCCLK_FREQ=20 ; +# SYSCONFIG MCCLK_FREQ = 2.5; # FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; # FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O ################################################################# -#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; -#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; #LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ; -#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; -DEFINE PORT GROUP "CLK_group" "CLK*" ; +#LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; +#LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; +#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! +DEFINE PORT GROUP "CLK_group" "*CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; ################################################################# # To central FPGA ################################################################# -#LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; -#LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; -#LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; -#LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; -#LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; -#LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; -#LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; -#LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; -#LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; -#LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; -#LOCATE COMP "FPGA5_COMM_10" SITE "V10"; -#LOCATE COMP "FPGA5_COMM_11" SITE "W10"; -#DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; +LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; +LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; +LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; +LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; +LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; +LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; +LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; +LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; +LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; +LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; +LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; LOCATE COMP "TEST_LINE[0]" SITE "A5" ; LOCATE COMP "TEST_LINE[1]" SITE "A6" ; LOCATE COMP "TEST_LINE[2]" SITE "G8" ; @@ -158,7 +159,7 @@ IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; #terminated differential pair to pads LOCATE COMP "SUPPL" SITE "C14" ; -#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; ################################################################# # LED ################################################################# @@ -178,13 +179,7 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; -#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber ! -#REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE; -#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE; -#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ; -#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ; -#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; No longer present in copper -#LOCATE UGROUP "THE_SYNC_LINK/media_uplink_group" REGION "UPLINK_REGION" ; + MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; @@ -195,13 +190,13 @@ MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; #MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only #MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -BLOCK JTAGPATHS ; -## IOBUF ALLPORTS ; -#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ; -#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ; -#USE PRIMARY NET "THE_HUB_SYNC_DOWNLINK/soda_rxdn_clock_full[1]" ; -USE PRIMARY NET "clk_raw_internal_c" ; -USE PRIMARY NET "clk_soda_i" ; -USE PRIMARY NET "clk_sys_internal_c" ; MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; + +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +USE PRIMARY NET "rxup_full_clk" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; +FREQUENCY NET "rxup_full_clk" 100.000000 MHz ; diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 44250d1..53e1c16 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,10 +1,10 @@ - + - + - + @@ -19,6 +19,18 @@ + + + + + + + + + + + + @@ -234,6 +246,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/trb3_soda_hub.xcf b/trb3_soda_hub.xcf index 9d2e09f..03f5f60 100644 --- a/trb3_soda_hub.xcf +++ b/trb3_soda_hub.xcf @@ -1,6 +1,6 @@ - + JTAG @@ -45,9 +45,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodahub_20140827.bit - 08/27/14 15:46:45 - N/A + /local/lemmens/lattice/soda/trb3_periph_sodahub_20150107.bit + 01/07/15 13:15:28 Fast Program