From: Jan Michel Date: Thu, 22 Jan 2015 15:08:31 +0000 (+0100) Subject: fixing conflicts X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2efe15d96cf7535df403f0d66700e6773feeced6;p=soda.git fixing conflicts --- 2efe15d96cf7535df403f0d66700e6773feeced6 diff --cc .gitattribute index 0000000,0000000..2125666 new file mode 100644 --- /dev/null +++ b/.gitattribute @@@ -1,0 -1,0 +1,1 @@@ ++* text=auto diff --cc code/med_ecp3_sfp_4_sync_down.vhd index 74ae017,e72c1b5..49471b3 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@@ -1,661 -1,678 +1,658 @@@ ----4 channel Media interface for Lattice ECP3 using PCS at 2GHz -- --LIBRARY IEEE; --use IEEE.std_logic_1164.ALL; --use IEEE.numeric_std.all; --use IEEE.std_logic_unsigned.ALL; -- --library work; --use work.trb_net_std.all; --use work.trb_net_components.all; --use work.med_sync_define.all; --use work.soda_components.all; -- --entity med_ecp3_sfp_4_sync_down is -- generic( SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave -- port( -- OSC_CLK : in std_logic; -- 200 MHz reference clock -- TX_DATACLK : in std_logic; -- 200 MHz data clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- --Internal Connection TX -- MED_DATA_IN : in t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0); -- MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(4*c_NUM_WIDTH-1 downto 0); -- MED_DATAREADY_IN : in std_logic_vector(3 downto 0); -- MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); -- --Internal Connection RX -- MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); -- MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); -- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); -- MED_READ_IN : in std_logic_vector(3 downto 0); -- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- -- --Sync operation -- RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used -- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used -- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port - STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); - CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); --- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); --- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); - STAT_OP : out std_logic_vector (63 downto 0); - CTRL_OP : in std_logic_vector (63 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); --end entity; -- -- --architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is -- -- -- Placer Directives -- attribute HGROUP : string; -- -- for whole architecture -- attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group"; -- attribute syn_sharing : string; -- attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off"; - attribute syn_hier : string; - attribute syn_hier of med_ecp3_sfp_4_sync_down_arch : architecture is "hard"; - - -- --signal clk_200_osc : std_logic; --signal clk_200_txdata : std_logic; --signal clk_200_rxdn : std_logic_vector(3 downto 0); --signal clk_200_i : std_logic_vector(3 downto 0); --signal rx_full_clk : std_logic_vector(3 downto 0); --signal rx_half_clk : std_logic_vector(3 downto 0); --signal tx_full_clk : std_logic_vector(3 downto 0); --signal tx_half_clk : std_logic_vector(3 downto 0); -- --signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); --signal tx_k : std_logic_vector(3 downto 0); --signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); --signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); -- --signal rst_n : t_HUB_BIT; --signal rst : t_HUB_BIT; -- PL! --signal rx_serdes_rst : t_HUB_BIT; --signal tx_serdes_rst : std_logic; --signal tx_pcs_rst : t_HUB_BIT; --signal rx_pcs_rst : t_HUB_BIT; --signal rst_qd : t_HUB_BIT; --signal rst_down_quad : std_logic; --signal serdes_rst_qd : t_HUB_BIT; --signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad --signal sd_los_i : t_HUB_BIT; --PL! -- --signal rx_los_low : t_HUB_BIT; --signal lsm_status : t_HUB_BIT; --signal rx_cdr_lol : t_HUB_BIT; --signal tx_pll_lol : t_HUB_BIT; --signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad -- --signal sci_ch_i : std_logic_vector(3 downto 0); --signal sci_qd_i : std_logic; --signal sci_reg_i : std_logic; --signal sci_addr_i : std_logic_vector(8 downto 0); --signal sci_data_in_i : std_logic_vector(7 downto 0); --signal sci_data_out_i : std_logic_vector(7 downto 0); --signal sci_read_i : std_logic; --signal sci_write_i : std_logic; --signal sci_write_shift_i : std_logic_vector(2 downto 0); --signal sci_read_shift_i : std_logic_vector(2 downto 0); -- --signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; --signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; --signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL! --signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); --signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); --signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0); --signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0); -- --signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0'); --signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0'); --signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0'); -- --signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); --signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); -- --signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); --signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); --signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); --signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); --signal debug_reg : std_logic_vector(63 downto 0); -- --type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); --signal sci_state : sci_ctrl; --signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0'); -- --begin -- -- ----SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -- --clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!! --clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! -- -- --gen_clocks : for i in 0 to 3 generate -- -- rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); -- rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); -- -- RX_HALF_CLK_OUT(i) <= rx_half_clk(i); -- RX_FULL_CLK_OUT(i) <= rx_full_clk(i); -- TX_HALF_CLK_OUT(i) <= tx_half_clk(i); -- TX_FULL_CLK_OUT(i) <= tx_full_clk(i); -- ---- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master ---- clk_200_i(i) <= rx_full_clk(i); ---- end generate; -- ---- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate ---- clk_200_i(i) <= clk_200_txdata; ---- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!! ---- end generate; --end generate; -- --------------------------------------------------- ---- Serdes --------------------------------------------------- --THE_SERDES : entity work.serdes_4_sync_downstream -- port map( -- -- CHANNEL0 -- -- hdinp_ch0 => SD_RXD_P_IN(0), -- hdinn_ch0 => SD_RXD_N_IN(0), -- hdoutp_ch0 => SD_TXD_P_OUT(0), -- hdoutn_ch0 => SD_TXD_N_OUT(0), -- rxiclk_ch0 => clk_200_txdata, --clk_200_i(0), -- sci_sel_ch0 => sci_ch_i(0), -- txiclk_ch0 => clk_200_txdata, -- rx_full_clk_ch0 => rx_full_clk(0), -- rx_half_clk_ch0 => rx_half_clk(0), -- tx_full_clk_ch0 => tx_full_clk(0), -- tx_half_clk_ch0 => tx_half_clk(0), -- fpga_rxrefclk_ch0 => clk_200_osc, -- txdata_ch0 => tx_data(0), -- tx_k_ch0 => tx_k(0), -- tx_force_disp_ch0 => '0', -- tx_disp_sel_ch0 => '0', -- rxdata_ch0 => rx_data(0), -- rx_k_ch0 => rx_k(0), -- rx_disp_err_ch0 => open, -- rx_cv_err_ch0 => rx_error(0), -- rx_serdes_rst_ch0_c => rx_serdes_rst(0), -- sb_felb_ch0_c => '0', -- sb_felb_rst_ch0_c => '0', -- tx_pcs_rst_ch0_c => tx_pcs_rst(0), -- tx_pwrup_ch0_c => '1', -- rx_pcs_rst_ch0_c => rx_pcs_rst(0), -- rx_pwrup_ch0_c => '1', -- rx_los_low_ch0_s => rx_los_low(0), -- lsm_status_ch0_s => lsm_status(0), -- rx_cdr_lol_ch0_s => rx_cdr_lol(0), -- tx_div2_mode_ch0_c => '0', -- rx_div2_mode_ch0_c => '0', -- -- CHANNEL1 -- -- hdinp_ch1 => SD_RXD_P_IN(1), -- hdinn_ch1 => SD_RXD_N_IN(1), -- hdoutp_ch1 => SD_TXD_P_OUT(1), -- hdoutn_ch1 => SD_TXD_N_OUT(1), -- rxiclk_ch1 => clk_200_txdata, --clk_200_i(1), -- sci_sel_ch1 => sci_ch_i(1), -- txiclk_ch1 => clk_200_txdata, -- rx_full_clk_ch1 => rx_full_clk(1), -- rx_half_clk_ch1 => rx_half_clk(1), -- tx_full_clk_ch1 => tx_full_clk(1), -- tx_half_clk_ch1 => tx_half_clk(1), -- fpga_rxrefclk_ch1 => clk_200_osc, -- txdata_ch1 => tx_data(1), -- tx_k_ch1 => tx_k(1), -- tx_force_disp_ch1 => '0', -- tx_disp_sel_ch1 => '0', -- rxdata_ch1 => rx_data(1), -- rx_k_ch1 => rx_k(1), -- rx_disp_err_ch1 => open, -- rx_cv_err_ch1 => rx_error(1), -- rx_serdes_rst_ch1_c => rx_serdes_rst(1), -- sb_felb_ch1_c => '0', -- sb_felb_rst_ch1_c => '0', -- tx_pcs_rst_ch1_c => tx_pcs_rst(1), -- tx_pwrup_ch1_c => '1', -- rx_pcs_rst_ch1_c => rx_pcs_rst(1), -- rx_pwrup_ch1_c => '1', -- rx_los_low_ch1_s => rx_los_low(1), -- lsm_status_ch1_s => lsm_status(1), -- rx_cdr_lol_ch1_s => rx_cdr_lol(1), -- tx_div2_mode_ch1_c => '0', -- rx_div2_mode_ch1_c => '0', -- -- CHANNEL2 -- -- hdinp_ch2 => SD_RXD_P_IN(2), -- hdinn_ch2 => SD_RXD_N_IN(2), -- hdoutp_ch2 => SD_TXD_P_OUT(2), -- hdoutn_ch2 => SD_TXD_N_OUT(2), -- rxiclk_ch2 => clk_200_txdata, --clk_200_i(2), -- sci_sel_ch2 => sci_ch_i(2), -- txiclk_ch2 => clk_200_txdata, -- rx_full_clk_ch2 => rx_full_clk(2), -- rx_half_clk_ch2 => rx_half_clk(2), -- tx_full_clk_ch2 => tx_full_clk(2), -- tx_half_clk_ch2 => tx_half_clk(2), -- fpga_rxrefclk_ch2 => clk_200_osc, -- txdata_ch2 => tx_data(2), -- tx_k_ch2 => tx_k(2), -- tx_force_disp_ch2 => '0', -- tx_disp_sel_ch2 => '0', -- rxdata_ch2 => rx_data(2), -- rx_k_ch2 => rx_k(2), -- rx_disp_err_ch2 => open, -- rx_cv_err_ch2 => rx_error(2), -- rx_serdes_rst_ch2_c => rx_serdes_rst(2), -- sb_felb_ch2_c => '0', -- sb_felb_rst_ch2_c => '0', -- tx_pcs_rst_ch2_c => tx_pcs_rst(2), -- tx_pwrup_ch2_c => '1', -- rx_pcs_rst_ch2_c => rx_pcs_rst(2), -- rx_pwrup_ch2_c => '1', -- rx_los_low_ch2_s => rx_los_low(2), -- lsm_status_ch2_s => lsm_status(2), -- rx_cdr_lol_ch2_s => rx_cdr_lol(2), -- tx_div2_mode_ch2_c => '0', -- rx_div2_mode_ch2_c => '0', -- -- CHANNEL3 -- -- hdinp_ch3 => SD_RXD_P_IN(3), -- hdinn_ch3 => SD_RXD_N_IN(3), -- hdoutp_ch3 => SD_TXD_P_OUT(3), -- hdoutn_ch3 => SD_TXD_N_OUT(3), -- rxiclk_ch3 => clk_200_txdata, --clk_200_i(3), -- sci_sel_ch3 => sci_ch_i(3), -- txiclk_ch3 => clk_200_txdata, -- rx_full_clk_ch3 => rx_full_clk(3), -- rx_half_clk_ch3 => rx_half_clk(3), -- tx_full_clk_ch3 => tx_full_clk(3), -- tx_half_clk_ch3 => tx_half_clk(3), -- fpga_rxrefclk_ch3 => clk_200_osc, -- txdata_ch3 => tx_data(3), -- tx_k_ch3 => tx_k(3), -- tx_force_disp_ch3 => '0', -- tx_disp_sel_ch3 => '0', -- rxdata_ch3 => rx_data(3), -- rx_k_ch3 => rx_k(3), -- rx_disp_err_ch3 => open, -- rx_cv_err_ch3 => rx_error(3), -- rx_serdes_rst_ch3_c => rx_serdes_rst(3), -- sb_felb_ch3_c => '0', -- sb_felb_rst_ch3_c => '0', -- tx_pcs_rst_ch3_c => tx_pcs_rst(3), -- tx_pwrup_ch3_c => '1', -- rx_pcs_rst_ch3_c => rx_pcs_rst(3), -- rx_pwrup_ch3_c => '1', -- rx_los_low_ch3_s => rx_los_low(3), -- lsm_status_ch3_s => lsm_status(3), -- rx_cdr_lol_ch3_s => rx_cdr_lol(3), -- tx_div2_mode_ch3_c => '0', -- rx_div2_mode_ch3_c => '0', -- -- COMMON -- -- sci_wrdata => sci_data_in_i, -- sci_rddata => sci_data_out_i, -- sci_addr => sci_addr_i(5 downto 0), -- sci_sel_quad => sci_qd_i, -- sci_rd => sci_read_i, -- sci_wrn => sci_write_i, -- - fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0), - fpga_txrefclk => clk_200_txdata, -- tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 -- tx_pll_lol_qd_s => tx_pll_lol_quad, -- tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols - rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk - rst_qd_c => rst_down_quad, -- serdes_rst_qd_c => serdes_rst_down_quad -- ); -- --------------------------- ---- combined quad reset -- --------------------------- ----rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; --rst_down_quad <= RESET; -- PL: 18/06/14 ----serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0'; --serdes_rst_down_quad <= '0'; -- PL: 23/06/14 -- --generated_logic : for i in 0 to 3 generate -- -- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready -- -- tx_pll_lol(i) <= tx_pll_lol_quad; -- -- ------------------------------------------------- -- -- Reset FSM & Link states -- ------------------------------------------------- -- THE_RX_FSM : rx_reset_fsm -- port map( -- RST_N => rst_n(i), - RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn - RX_REFCLK => rx_full_clk(i), -- TX_PLL_LOL_QD_S => tx_pll_lol(i), -- RX_SERDES_RST_CH_C => rx_serdes_rst(i), -- RX_CDR_LOL_CH_S => rx_cdr_lol(i), -- RX_LOS_LOW_CH_S => rx_los_low(i), -- RX_PCS_RST_CH_C => rx_pcs_rst(i), -- WA_POSITION => wa_position_rx(i), -- STATE_OUT => rx_fsm_state(i) -- ); -- -- THE_TX_FSM : tx_reset_fsm -- port map( -- RST_N => rst_n(i), - TX_REFCLK => clk_200_txdata, --clk_200_osc, - TX_REFCLK => clk_200_txdata, -- TX_PLL_LOL_QD_S => tx_pll_lol(i), -- RST_QD_C => rst_qd(i), -- TX_PCS_RST_CH_C => tx_pcs_rst(i), -- STATE_OUT => tx_fsm_state(i) -- ); -- -- -- -- Master does not do bit-locking -- wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0"; -- -- -- PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i)) -- begin -- if rising_edge(clk_200_txdata) then -- clk_200_txdata ?? -- if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then -- rx_allow(i) <= '1'; -- tx_allow(i) <= '1'; -- else -- rx_allow(i) <= '0'; -- tx_allow(i) <= '1'; -- end if; -- end if; -- end process; -- -- rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK); -- tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); -- -- -- PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i)) -- begin -- if rising_edge(clk_200_txdata) then -- if got_link_ready_i(i) = '1' then -- watchdog_timer(i) <= (others => '0'); -- if start_timer(i)(start_timer'left) = '0' then -- start_timer(i) <= start_timer(i) + 1; ---- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1; -- end if; -- else -- start_timer(i) <= (others => '0'); -- if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then -- watchdog_trigger(i) <= '1'; -- else -- watchdog_trigger(i) <= '0'; -- end if; -- if watchdog_trigger(i) = '0' then -- watchdog_timer(i) <= watchdog_timer(i) + 1; -- else -- watchdog_timer(i) <= (others => '0'); -- end if; -- end if; -- end if; -- end process; -- ------------------------------------------------- -- -- TX Data -- ------------------------------------------------- -- THE_TX : soda_tx_control -- port map( -- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), -- CLK_100 => SYSCLK, -- RESET_IN => rst(i), --CLEAR, PL! -- -- TX_DATA_IN => MED_DATA_IN(i), -- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN(i), -- TX_WRITE_IN => MED_DATAREADY_IN(i), -- TX_READ_OUT => MED_READ_OUT(i), -- -- TX_DATA_OUT => tx_data(i), -- TX_K_OUT => tx_k(i), -- -- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO -- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO -- -- START_RETRANSMIT_IN => start_retr_i(i), --TODO -- START_POSITION_IN => request_retr_position_i(i), --TODO -- -- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), -- SEND_DLM => TX_DLM(i), -- SEND_DLM_WORD => TX_DLM_WORD(i), -- - SEND_LINK_RESET_IN => CTRL_OP(i)(15), - SEND_LINK_RESET_IN => CTRL_OP(i*16 + 15), --CTRL_OP(i)(15), -- TX_ALLOW_IN => tx_allow(i), -- RX_ALLOW_IN => rx_allow(i), -- LINK_PHASE_OUT => link_phase_S(i), --PL! -- -- DEBUG_OUT => debug_tx_control_i(i), -- STAT_REG_OUT => stat_tx_control_i(i) -- ); -- -- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! -- ------------------------------------------------- -- -- RX Data -- ------------------------------------------------- -- THE_RX_CONTROL : rx_control -- port map( -- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! -- CLK_100 => SYSCLK, -- RESET_IN => rst(i), --CLEAR, PL! -- -- RX_DATA_OUT => MED_DATA_OUT(i), -- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT(i), -- RX_WRITE_OUT => MED_DATAREADY_OUT(i), -- RX_READ_IN => MED_READ_IN(i), -- -- RX_DATA_IN => rx_data(i), -- RX_K_IN => rx_k(i), -- -- REQUEST_RETRANSMIT_OUT => request_retr_i(i), -- REQUEST_POSITION_OUT => request_retr_position_i(i), -- -- START_RETRANSMIT_OUT => start_retr_i(i), -- START_POSITION_OUT => start_retr_position_i(i), -- -- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM -- RX_DLM => RX_DLM(i), -- RX_DLM_WORD => RX_DLM_WORD(i), -- -- SEND_LINK_RESET_OUT => send_link_reset_i(i), -- MAKE_RESET_OUT => make_link_reset_i(i), -- RX_ALLOW_IN => rx_allow(i), -- GOT_LINK_READY => got_link_ready_i(i), -- -- DEBUG_OUT => debug_rx_control_i(i), -- STAT_REG_OUT => stat_rx_control_i(i) -- ); -- -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! --- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115 - sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(clk_200_txdata); -- --end generate; -- --------------------------------------------------- ---- SCI --------------------------------------------------- ----gives access to serdes config port from slow control and reads word alignment every ~ 40 us --PROC_SCI_CTRL: process --variable cnt : integer range 0 to 4 := 0; --begin - wait until rising_edge(SYSCLK); - SCI_ACK <= '0'; - case sci_state is - when IDLE => - sci_ch_i <= x"0"; - sci_qd_i <= '0'; - sci_reg_i <= '0'; - sci_read_i <= '0'; - sci_write_i <= '0'; - sci_timer(0) <= sci_timer(0) + 1; - sci_timer(1) <= sci_timer(1) + 1; - sci_timer(2) <= sci_timer(2) + 1; - sci_timer(3) <= sci_timer(3) + 1; - if SCI_READ = '1' or SCI_WRITE = '1' then - sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_addr_i <= SCI_ADDR; - sci_data_in_i <= SCI_DATA_IN; - sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_state <= SCTRL; - else - if sci_timer(0)(sci_timer'left) = '1' then - sci_timer(0) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(1)(sci_timer'left) = '1' then - sci_timer(1) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(2)(sci_timer'left) = '1' then - sci_timer(2) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(3)(sci_timer'left) = '1' then - sci_timer(3) <= (others => '0'); - sci_state <= GET_WA; - end if; - end if; - when SCTRL => - if sci_reg_i = '1' then - SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - else - sci_state <= SCTRL_WAIT; - end if; - when SCTRL_WAIT => - sci_state <= SCTRL_WAIT2; - when SCTRL_WAIT2 => - sci_state <= SCTRL_FINISH; - when SCTRL_FINISH => - SCI_DATA_OUT <= sci_data_out_i; - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - - when GET_WA => - if cnt = 4 then - cnt := 0; - sci_state <= IDLE; - else - sci_state <= GET_WA_WAIT; - sci_addr_i <= '0' & x"22"; - sci_ch_i <= x"0"; - sci_ch_i(cnt) <= '1'; - sci_read_i <= '1'; - end if; - when GET_WA_WAIT => - sci_state <= GET_WA_WAIT2; - when GET_WA_WAIT2 => - sci_state <= GET_WA_FINISH; - when GET_WA_FINISH => - -- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); - wa_position(cnt) <= sci_data_out_i(3 downto 0); - sci_state <= GET_WA; - cnt := cnt + 1; - end case; - - if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then - SCI_NACK <= '1'; - else - SCI_NACK <= '0'; - end if; - - end process; - - - -- ------------------------------------------------- - -- -- Debug Registers - -- ------------------------------------------------- - -- debug_reg(3 downto 0) <= rx_fsm_state; - -- debug_reg(4) <= rx_k; - -- debug_reg(5) <= rx_error; - -- debug_reg(6) <= rx_los_low; - -- debug_reg(7) <= rx_cdr_lol; - -- - -- debug_reg(8) <= tx_k; - -- debug_reg(9) <= tx_pll_lol; - -- debug_reg(10) <= lsm_status; - -- debug_reg(11) <= make_link_reset_i; - -- debug_reg(15 downto 12) <= tx_fsm_state; - -- -- debug_reg(31 downto 24) <= tx_data; - -- - -- debug_reg(16) <= '0'; - -- debug_reg(17) <= tx_allow; - -- debug_reg(18) <= RESET; - -- debug_reg(19) <= CLEAR; - -- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); - -- - -- debug_reg(35 downto 32) <= wa_position(3 downto 0); - -- debug_reg(36) <= debug_tx_control_i(6); - -- debug_reg(39 downto 37) <= "000"; - -- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); - - - STAT_DEBUG <= (others => '0'); --debug_reg; - - generated_status : for i in 0 to 3 generate - -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! - - STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); - STAT_OP(i)(14) <= '0'; - STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset - STAT_OP(i)(12) <= '0'; - STAT_OP(i)(11) <= '0'; - STAT_OP(i)(10) <= rx_allow(i); - STAT_OP(i)(9) <= tx_allow(i); - STAT_OP(i)(8) <= got_link_ready_i(i) when rising_edge(rx_half_clk(i)); - STAT_OP(i)(7) <= send_link_reset_i(i); - STAT_OP(i)(6) <= make_link_reset_i(i); - STAT_OP(i)(5) <= request_retr_i(i); - STAT_OP(i)(4) <= start_retr_i(i); - STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; - end generate; - - end med_ecp3_sfp_4_sync_down_arch; ++--4 channel Media interface for Lattice ECP3 using PCS at 2GHz ++ ++LIBRARY IEEE; ++use IEEE.std_logic_1164.ALL; ++use IEEE.numeric_std.all; ++use IEEE.std_logic_unsigned.ALL; ++ ++library work; ++use work.trb_net_std.all; ++use work.trb_net_components.all; ++use work.med_sync_define.all; ++use work.soda_components.all; ++ ++entity med_ecp3_sfp_4_sync_down is ++ generic( SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave ++ port( ++ OSC_CLK : in std_logic; -- 200 MHz reference clock ++ TX_DATACLK : in std_logic; -- 200 MHz data clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ --Internal Connection TX ++ MED_DATA_IN : in t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0); ++ MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(4*c_NUM_WIDTH-1 downto 0); ++ MED_DATAREADY_IN : in std_logic_vector(3 downto 0); ++ MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); ++ --Internal Connection RX ++ MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); ++ MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); ++ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); ++ MED_READ_IN : in std_logic_vector(3 downto 0); ++ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ ++ --Sync operation ++ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++ STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); ++ CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++end entity; ++ ++ ++architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is ++ ++ -- Placer Directives ++ attribute HGROUP : string; ++ -- for whole architecture ++ attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group"; ++ attribute syn_sharing : string; ++ attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off"; ++ attribute syn_hier : string; ++ attribute syn_hier of med_ecp3_sfp_4_sync_down_arch : architecture is "hard"; ++ ++signal clk_200_osc : std_logic; ++signal clk_200_txdata : std_logic; ++signal clk_200_rxdn : std_logic_vector(3 downto 0); ++signal clk_200_i : std_logic_vector(3 downto 0); ++signal rx_full_clk : std_logic_vector(3 downto 0); ++signal rx_half_clk : std_logic_vector(3 downto 0); ++signal tx_full_clk : std_logic_vector(3 downto 0); ++signal tx_half_clk : std_logic_vector(3 downto 0); ++ ++signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); ++signal tx_k : std_logic_vector(3 downto 0); ++signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); ++signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); ++ ++signal rst_n : t_HUB_BIT; ++signal rst : t_HUB_BIT; -- PL! ++signal rx_serdes_rst : t_HUB_BIT; ++signal tx_serdes_rst : std_logic; ++signal tx_pcs_rst : t_HUB_BIT; ++signal rx_pcs_rst : t_HUB_BIT; ++signal rst_qd : t_HUB_BIT; ++signal rst_down_quad : std_logic; ++signal serdes_rst_qd : t_HUB_BIT; ++signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad ++signal sd_los_i : t_HUB_BIT; --PL! ++ ++signal rx_los_low : t_HUB_BIT; ++signal lsm_status : t_HUB_BIT; ++signal rx_cdr_lol : t_HUB_BIT; ++signal tx_pll_lol : t_HUB_BIT; ++signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad ++ ++signal sci_ch_i : std_logic_vector(3 downto 0); ++signal sci_qd_i : std_logic; ++signal sci_reg_i : std_logic; ++signal sci_addr_i : std_logic_vector(8 downto 0); ++signal sci_data_in_i : std_logic_vector(7 downto 0); ++signal sci_data_out_i : std_logic_vector(7 downto 0); ++signal sci_read_i : std_logic; ++signal sci_write_i : std_logic; ++signal sci_write_shift_i : std_logic_vector(2 downto 0); ++signal sci_read_shift_i : std_logic_vector(2 downto 0); ++ ++signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; ++signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; ++signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL! ++signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); ++signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); ++signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0); ++signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0); ++ ++signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0'); ++signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0'); ++signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0'); ++ ++signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); ++signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); ++ ++signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); ++signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); ++signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); ++signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); ++signal debug_reg : std_logic_vector(63 downto 0); ++ ++type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); ++signal sci_state : sci_ctrl; ++signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0'); ++ ++begin ++ ++ ++--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready ++ ++clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!! ++clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! ++ ++ ++gen_clocks : for i in 0 to 3 generate ++ ++ rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); ++ rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); ++ ++ RX_HALF_CLK_OUT(i) <= rx_half_clk(i); ++ RX_FULL_CLK_OUT(i) <= rx_full_clk(i); ++ TX_HALF_CLK_OUT(i) <= tx_half_clk(i); ++ TX_FULL_CLK_OUT(i) <= tx_full_clk(i); ++ ++-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master ++-- clk_200_i(i) <= rx_full_clk(i); ++-- end generate; ++ ++-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate ++-- clk_200_i(i) <= clk_200_txdata; ++-- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!! ++-- end generate; ++end generate; ++ ++------------------------------------------------- ++-- Serdes ++------------------------------------------------- ++THE_SERDES : entity work.serdes_4_sync_downstream ++ port map( ++ -- CHANNEL0 -- ++ hdinp_ch0 => SD_RXD_P_IN(0), ++ hdinn_ch0 => SD_RXD_N_IN(0), ++ hdoutp_ch0 => SD_TXD_P_OUT(0), ++ hdoutn_ch0 => SD_TXD_N_OUT(0), ++ rxiclk_ch0 => clk_200_txdata, --clk_200_i(0), ++ sci_sel_ch0 => sci_ch_i(0), ++ txiclk_ch0 => clk_200_txdata, ++ rx_full_clk_ch0 => rx_full_clk(0), ++ rx_half_clk_ch0 => rx_half_clk(0), ++ tx_full_clk_ch0 => tx_full_clk(0), ++ tx_half_clk_ch0 => tx_half_clk(0), ++ fpga_rxrefclk_ch0 => clk_200_osc, ++ txdata_ch0 => tx_data(0), ++ tx_k_ch0 => tx_k(0), ++ tx_force_disp_ch0 => '0', ++ tx_disp_sel_ch0 => '0', ++ rxdata_ch0 => rx_data(0), ++ rx_k_ch0 => rx_k(0), ++ rx_disp_err_ch0 => open, ++ rx_cv_err_ch0 => rx_error(0), ++ rx_serdes_rst_ch0_c => rx_serdes_rst(0), ++ sb_felb_ch0_c => '0', ++ sb_felb_rst_ch0_c => '0', ++ tx_pcs_rst_ch0_c => tx_pcs_rst(0), ++ tx_pwrup_ch0_c => '1', ++ rx_pcs_rst_ch0_c => rx_pcs_rst(0), ++ rx_pwrup_ch0_c => '1', ++ rx_los_low_ch0_s => rx_los_low(0), ++ lsm_status_ch0_s => lsm_status(0), ++ rx_cdr_lol_ch0_s => rx_cdr_lol(0), ++ tx_div2_mode_ch0_c => '0', ++ rx_div2_mode_ch0_c => '0', ++ -- CHANNEL1 -- ++ hdinp_ch1 => SD_RXD_P_IN(1), ++ hdinn_ch1 => SD_RXD_N_IN(1), ++ hdoutp_ch1 => SD_TXD_P_OUT(1), ++ hdoutn_ch1 => SD_TXD_N_OUT(1), ++ rxiclk_ch1 => clk_200_txdata, --clk_200_i(1), ++ sci_sel_ch1 => sci_ch_i(1), ++ txiclk_ch1 => clk_200_txdata, ++ rx_full_clk_ch1 => rx_full_clk(1), ++ rx_half_clk_ch1 => rx_half_clk(1), ++ tx_full_clk_ch1 => tx_full_clk(1), ++ tx_half_clk_ch1 => tx_half_clk(1), ++ fpga_rxrefclk_ch1 => clk_200_osc, ++ txdata_ch1 => tx_data(1), ++ tx_k_ch1 => tx_k(1), ++ tx_force_disp_ch1 => '0', ++ tx_disp_sel_ch1 => '0', ++ rxdata_ch1 => rx_data(1), ++ rx_k_ch1 => rx_k(1), ++ rx_disp_err_ch1 => open, ++ rx_cv_err_ch1 => rx_error(1), ++ rx_serdes_rst_ch1_c => rx_serdes_rst(1), ++ sb_felb_ch1_c => '0', ++ sb_felb_rst_ch1_c => '0', ++ tx_pcs_rst_ch1_c => tx_pcs_rst(1), ++ tx_pwrup_ch1_c => '1', ++ rx_pcs_rst_ch1_c => rx_pcs_rst(1), ++ rx_pwrup_ch1_c => '1', ++ rx_los_low_ch1_s => rx_los_low(1), ++ lsm_status_ch1_s => lsm_status(1), ++ rx_cdr_lol_ch1_s => rx_cdr_lol(1), ++ tx_div2_mode_ch1_c => '0', ++ rx_div2_mode_ch1_c => '0', ++ -- CHANNEL2 -- ++ hdinp_ch2 => SD_RXD_P_IN(2), ++ hdinn_ch2 => SD_RXD_N_IN(2), ++ hdoutp_ch2 => SD_TXD_P_OUT(2), ++ hdoutn_ch2 => SD_TXD_N_OUT(2), ++ rxiclk_ch2 => clk_200_txdata, --clk_200_i(2), ++ sci_sel_ch2 => sci_ch_i(2), ++ txiclk_ch2 => clk_200_txdata, ++ rx_full_clk_ch2 => rx_full_clk(2), ++ rx_half_clk_ch2 => rx_half_clk(2), ++ tx_full_clk_ch2 => tx_full_clk(2), ++ tx_half_clk_ch2 => tx_half_clk(2), ++ fpga_rxrefclk_ch2 => clk_200_osc, ++ txdata_ch2 => tx_data(2), ++ tx_k_ch2 => tx_k(2), ++ tx_force_disp_ch2 => '0', ++ tx_disp_sel_ch2 => '0', ++ rxdata_ch2 => rx_data(2), ++ rx_k_ch2 => rx_k(2), ++ rx_disp_err_ch2 => open, ++ rx_cv_err_ch2 => rx_error(2), ++ rx_serdes_rst_ch2_c => rx_serdes_rst(2), ++ sb_felb_ch2_c => '0', ++ sb_felb_rst_ch2_c => '0', ++ tx_pcs_rst_ch2_c => tx_pcs_rst(2), ++ tx_pwrup_ch2_c => '1', ++ rx_pcs_rst_ch2_c => rx_pcs_rst(2), ++ rx_pwrup_ch2_c => '1', ++ rx_los_low_ch2_s => rx_los_low(2), ++ lsm_status_ch2_s => lsm_status(2), ++ rx_cdr_lol_ch2_s => rx_cdr_lol(2), ++ tx_div2_mode_ch2_c => '0', ++ rx_div2_mode_ch2_c => '0', ++ -- CHANNEL3 -- ++ hdinp_ch3 => SD_RXD_P_IN(3), ++ hdinn_ch3 => SD_RXD_N_IN(3), ++ hdoutp_ch3 => SD_TXD_P_OUT(3), ++ hdoutn_ch3 => SD_TXD_N_OUT(3), ++ rxiclk_ch3 => clk_200_txdata, --clk_200_i(3), ++ sci_sel_ch3 => sci_ch_i(3), ++ txiclk_ch3 => clk_200_txdata, ++ rx_full_clk_ch3 => rx_full_clk(3), ++ rx_half_clk_ch3 => rx_half_clk(3), ++ tx_full_clk_ch3 => tx_full_clk(3), ++ tx_half_clk_ch3 => tx_half_clk(3), ++ fpga_rxrefclk_ch3 => clk_200_osc, ++ txdata_ch3 => tx_data(3), ++ tx_k_ch3 => tx_k(3), ++ tx_force_disp_ch3 => '0', ++ tx_disp_sel_ch3 => '0', ++ rxdata_ch3 => rx_data(3), ++ rx_k_ch3 => rx_k(3), ++ rx_disp_err_ch3 => open, ++ rx_cv_err_ch3 => rx_error(3), ++ rx_serdes_rst_ch3_c => rx_serdes_rst(3), ++ sb_felb_ch3_c => '0', ++ sb_felb_rst_ch3_c => '0', ++ tx_pcs_rst_ch3_c => tx_pcs_rst(3), ++ tx_pwrup_ch3_c => '1', ++ rx_pcs_rst_ch3_c => rx_pcs_rst(3), ++ rx_pwrup_ch3_c => '1', ++ rx_los_low_ch3_s => rx_los_low(3), ++ lsm_status_ch3_s => lsm_status(3), ++ rx_cdr_lol_ch3_s => rx_cdr_lol(3), ++ tx_div2_mode_ch3_c => '0', ++ rx_div2_mode_ch3_c => '0', ++ -- COMMON -- ++ sci_wrdata => sci_data_in_i, ++ sci_rddata => sci_data_out_i, ++ sci_addr => sci_addr_i(5 downto 0), ++ sci_sel_quad => sci_qd_i, ++ sci_rd => sci_read_i, ++ sci_wrn => sci_write_i, ++ ++ fpga_txrefclk => clk_200_txdata, ++ tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 ++ tx_pll_lol_qd_s => tx_pll_lol_quad, ++ tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols ++ rst_qd_c => rst_down_quad, ++ serdes_rst_qd_c => serdes_rst_down_quad ++ ); ++ ++------------------------- ++-- combined quad reset -- ++------------------------- ++--rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; ++rst_down_quad <= RESET; -- PL: 18/06/14 ++--serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0'; ++serdes_rst_down_quad <= '0'; -- PL: 23/06/14 ++ ++generated_logic : for i in 0 to 3 generate ++ ++ SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready ++ ++ tx_pll_lol(i) <= tx_pll_lol_quad; ++ ++ ------------------------------------------------- ++ -- Reset FSM & Link states ++ ------------------------------------------------- ++ THE_RX_FSM : rx_reset_fsm ++ port map( ++ RST_N => rst_n(i), ++ RX_REFCLK => rx_full_clk(i), ++ TX_PLL_LOL_QD_S => tx_pll_lol(i), ++ RX_SERDES_RST_CH_C => rx_serdes_rst(i), ++ RX_CDR_LOL_CH_S => rx_cdr_lol(i), ++ RX_LOS_LOW_CH_S => rx_los_low(i), ++ RX_PCS_RST_CH_C => rx_pcs_rst(i), ++ WA_POSITION => wa_position_rx(i), ++ STATE_OUT => rx_fsm_state(i) ++ ); ++ ++ THE_TX_FSM : tx_reset_fsm ++ port map( ++ RST_N => rst_n(i), ++ TX_REFCLK => clk_200_txdata, ++ TX_PLL_LOL_QD_S => tx_pll_lol(i), ++ RST_QD_C => rst_qd(i), ++ TX_PCS_RST_CH_C => tx_pcs_rst(i), ++ STATE_OUT => tx_fsm_state(i) ++ ); ++ ++ ++ -- Master does not do bit-locking ++ wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0"; ++ ++ ++ PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i)) ++ begin ++ if rising_edge(clk_200_txdata) then -- clk_200_txdata ?? ++ if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then ++ rx_allow(i) <= '1'; ++ tx_allow(i) <= '1'; ++ else ++ rx_allow(i) <= '0'; ++ tx_allow(i) <= '1'; ++ end if; ++ end if; ++ end process; ++ ++ rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK); ++ tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); ++ ++ ++ PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i)) ++ begin ++ if rising_edge(clk_200_txdata) then ++ if got_link_ready_i(i) = '1' then ++ watchdog_timer(i) <= (others => '0'); ++ if start_timer(i)(start_timer'left) = '0' then ++ start_timer(i) <= start_timer(i) + 1; ++-- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1; ++ end if; ++ else ++ start_timer(i) <= (others => '0'); ++ if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then ++ watchdog_trigger(i) <= '1'; ++ else ++ watchdog_trigger(i) <= '0'; ++ end if; ++ if watchdog_trigger(i) = '0' then ++ watchdog_timer(i) <= watchdog_timer(i) + 1; ++ else ++ watchdog_timer(i) <= (others => '0'); ++ end if; ++ end if; ++ end if; ++ end process; ++ ------------------------------------------------- ++ -- TX Data ++ ------------------------------------------------- ++ THE_TX : soda_tx_control ++ port map( ++ CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), ++ CLK_100 => SYSCLK, ++ RESET_IN => rst(i), --CLEAR, PL! ++ ++ TX_DATA_IN => MED_DATA_IN(i), ++ TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN(i), ++ TX_WRITE_IN => MED_DATAREADY_IN(i), ++ TX_READ_OUT => MED_READ_OUT(i), ++ ++ TX_DATA_OUT => tx_data(i), ++ TX_K_OUT => tx_k(i), ++ ++ REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO ++ REQUEST_POSITION_IN => request_retr_position_i(i), --TODO ++ ++ START_RETRANSMIT_IN => start_retr_i(i), --TODO ++ START_POSITION_IN => request_retr_position_i(i), --TODO ++ ++ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), ++ SEND_DLM => TX_DLM(i), ++ SEND_DLM_WORD => TX_DLM_WORD(i), ++ ++ SEND_LINK_RESET_IN => CTRL_OP(i)(15), --CTRL_OP(i)(15), ++ TX_ALLOW_IN => tx_allow(i), ++ RX_ALLOW_IN => rx_allow(i), ++ LINK_PHASE_OUT => link_phase_S(i), --PL! ++ ++ DEBUG_OUT => debug_tx_control_i(i), ++ STAT_REG_OUT => stat_tx_control_i(i) ++ ); ++ ++ LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! ++ ------------------------------------------------- ++ -- RX Data ++ ------------------------------------------------- ++ THE_RX_CONTROL : rx_control ++ port map( ++ CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! ++ CLK_100 => SYSCLK, ++ RESET_IN => rst(i), --CLEAR, PL! ++ ++ RX_DATA_OUT => MED_DATA_OUT(i), ++ RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT(i), ++ RX_WRITE_OUT => MED_DATAREADY_OUT(i), ++ RX_READ_IN => MED_READ_IN(i), ++ ++ RX_DATA_IN => rx_data(i), ++ RX_K_IN => rx_k(i), ++ ++ REQUEST_RETRANSMIT_OUT => request_retr_i(i), ++ REQUEST_POSITION_OUT => request_retr_position_i(i), ++ ++ START_RETRANSMIT_OUT => start_retr_i(i), ++ START_POSITION_OUT => start_retr_position_i(i), ++ ++ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM ++ RX_DLM => RX_DLM(i), ++ RX_DLM_WORD => RX_DLM_WORD(i), ++ ++ SEND_LINK_RESET_OUT => send_link_reset_i(i), ++ MAKE_RESET_OUT => make_link_reset_i(i), ++ RX_ALLOW_IN => rx_allow(i), ++ GOT_LINK_READY => got_link_ready_i(i), ++ ++ DEBUG_OUT => debug_rx_control_i(i), ++ STAT_REG_OUT => stat_rx_control_i(i) ++ ); ++ ++ internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; ++ sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(clk_200_txdata); ++ ++end generate; ++ ++------------------------------------------------- ++-- SCI ++------------------------------------------------- ++--gives access to serdes config port from slow control and reads word alignment every ~ 40 us ++PROC_SCI_CTRL: process ++variable cnt : integer range 0 to 4 := 0; ++begin + wait until rising_edge(SYSCLK); - SCI_ACK <= '0'; - case sci_state is - when IDLE => - sci_ch_i <= x"0"; - sci_qd_i <= '0'; - sci_reg_i <= '0'; - sci_read_i <= '0'; - sci_write_i <= '0'; - sci_timer(0) <= sci_timer(0) + 1; - sci_timer(1) <= sci_timer(1) + 1; - sci_timer(2) <= sci_timer(2) + 1; - sci_timer(3) <= sci_timer(3) + 1; - if SCI_READ = '1' or SCI_WRITE = '1' then - sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_addr_i <= SCI_ADDR; - sci_data_in_i <= SCI_DATA_IN; - sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_state <= SCTRL; - else - if sci_timer(0)(sci_timer'left) = '1' then - sci_timer(0) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(1)(sci_timer'left) = '1' then - sci_timer(1) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(2)(sci_timer'left) = '1' then - sci_timer(2) <= (others => '0'); - sci_state <= GET_WA; - end if; - if sci_timer(3)(sci_timer'left) = '1' then - sci_timer(3) <= (others => '0'); - sci_state <= GET_WA; - end if; - end if; -when SCTRL => - if sci_reg_i = '1' then - SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - else - sci_state <= SCTRL_WAIT; - end if; -when SCTRL_WAIT => - sci_state <= SCTRL_WAIT2; -when SCTRL_WAIT2 => - sci_state <= SCTRL_FINISH; -when SCTRL_FINISH => - SCI_DATA_OUT <= sci_data_out_i; - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - -when GET_WA => - if cnt = 4 then - cnt := 0; - sci_state <= IDLE; - else - sci_state <= GET_WA_WAIT; - sci_addr_i <= '0' & x"22"; - sci_ch_i <= x"0"; - sci_ch_i(cnt) <= '1'; - sci_read_i <= '1'; - end if; -when GET_WA_WAIT => - sci_state <= GET_WA_WAIT2; -when GET_WA_WAIT2 => - sci_state <= GET_WA_FINISH; -when GET_WA_FINISH => --- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); - wa_position(cnt) <= sci_data_out_i(3 downto 0); - sci_state <= GET_WA; - cnt := cnt + 1; -end case; - -if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then - SCI_NACK <= '1'; -else - SCI_NACK <= '0'; -end if; - -end process; - - --- ------------------------------------------------- --- -- Debug Registers --- ------------------------------------------------- --- debug_reg(3 downto 0) <= rx_fsm_state; --- debug_reg(4) <= rx_k; --- debug_reg(5) <= rx_error; --- debug_reg(6) <= rx_los_low; --- debug_reg(7) <= rx_cdr_lol; --- --- debug_reg(8) <= tx_k; --- debug_reg(9) <= tx_pll_lol; --- debug_reg(10) <= lsm_status; --- debug_reg(11) <= make_link_reset_i; --- debug_reg(15 downto 12) <= tx_fsm_state; --- -- debug_reg(31 downto 24) <= tx_data; --- --- debug_reg(16) <= '0'; --- debug_reg(17) <= tx_allow; --- debug_reg(18) <= RESET; --- debug_reg(19) <= CLEAR; --- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); --- --- debug_reg(35 downto 32) <= wa_position(3 downto 0); --- debug_reg(36) <= debug_tx_control_i(6); --- debug_reg(39 downto 37) <= "000"; --- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); - - - STAT_DEBUG <= (others => '0'); --debug_reg; - - generated_status : for i in 0 to 3 generate - -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! - - STAT_OP(i*16 + 15) <= send_link_reset_i(i) when rising_edge(SYSCLK); - STAT_OP(i*16 + 14) <= '0'; - STAT_OP(i*16 + 13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset - STAT_OP(i*16 + 12) <= '0'; - STAT_OP(i*16 + 11) <= '0'; - STAT_OP(i*16 + 10) <= rx_allow(i); - STAT_OP(i*16 + 9) <= tx_allow(i); - STAT_OP(i*16 + 8) <= got_link_ready_i(i); - STAT_OP(i*16 + 7) <= send_link_reset_i(i); - STAT_OP(i*16 + 6) <= make_link_reset_i(i); - STAT_OP(i*16 + 5) <= request_retr_i(i); - STAT_OP(i*16 + 4) <= start_retr_i(i); - STAT_OP(i*16 + 3 downto i*16) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; - -- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); --- STAT_OP(i)(14) <= '0'; --- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset --- STAT_OP(i)(12) <= '0'; --- STAT_OP(i)(11) <= '0'; --- STAT_OP(i)(10) <= rx_allow(i); --- STAT_OP(i)(9) <= tx_allow(i); --- STAT_OP(i)(8) <= got_link_ready_i(i); --- STAT_OP(i)(7) <= send_link_reset_i(i); --- STAT_OP(i)(6) <= make_link_reset_i(i); --- STAT_OP(i)(5) <= request_retr_i(i); --- STAT_OP(i)(4) <= start_retr_i(i); --- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; - - end generate; - -end med_ecp3_sfp_4_sync_down_arch; ++ SCI_ACK <= '0'; ++ case sci_state is ++ when IDLE => ++ sci_ch_i <= x"0"; ++ sci_qd_i <= '0'; ++ sci_reg_i <= '0'; ++ sci_read_i <= '0'; ++ sci_write_i <= '0'; ++ sci_timer(0) <= sci_timer(0) + 1; ++ sci_timer(1) <= sci_timer(1) + 1; ++ sci_timer(2) <= sci_timer(2) + 1; ++ sci_timer(3) <= sci_timer(3) + 1; ++ if SCI_READ = '1' or SCI_WRITE = '1' then ++ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); ++ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); ++ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); ++ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); ++ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); ++ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); ++ sci_addr_i <= SCI_ADDR; ++ sci_data_in_i <= SCI_DATA_IN; ++ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); ++ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); ++ sci_state <= SCTRL; ++ else ++ if sci_timer(0)(sci_timer'left) = '1' then ++ sci_timer(0) <= (others => '0'); ++ sci_state <= GET_WA; ++ end if; ++ if sci_timer(1)(sci_timer'left) = '1' then ++ sci_timer(1) <= (others => '0'); ++ sci_state <= GET_WA; ++ end if; ++ if sci_timer(2)(sci_timer'left) = '1' then ++ sci_timer(2) <= (others => '0'); ++ sci_state <= GET_WA; ++ end if; ++ if sci_timer(3)(sci_timer'left) = '1' then ++ sci_timer(3) <= (others => '0'); ++ sci_state <= GET_WA; ++ end if; ++ end if; ++when SCTRL => ++ if sci_reg_i = '1' then ++ SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); ++ SCI_ACK <= '1'; ++ sci_write_i <= '0'; ++ sci_read_i <= '0'; ++ sci_state <= IDLE; ++ else ++ sci_state <= SCTRL_WAIT; ++ end if; ++when SCTRL_WAIT => ++ sci_state <= SCTRL_WAIT2; ++when SCTRL_WAIT2 => ++ sci_state <= SCTRL_FINISH; ++when SCTRL_FINISH => ++ SCI_DATA_OUT <= sci_data_out_i; ++ SCI_ACK <= '1'; ++ sci_write_i <= '0'; ++ sci_read_i <= '0'; ++ sci_state <= IDLE; ++ ++when GET_WA => ++ if cnt = 4 then ++ cnt := 0; ++ sci_state <= IDLE; ++ else ++ sci_state <= GET_WA_WAIT; ++ sci_addr_i <= '0' & x"22"; ++ sci_ch_i <= x"0"; ++ sci_ch_i(cnt) <= '1'; ++ sci_read_i <= '1'; ++ end if; ++when GET_WA_WAIT => ++ sci_state <= GET_WA_WAIT2; ++when GET_WA_WAIT2 => ++ sci_state <= GET_WA_FINISH; ++when GET_WA_FINISH => ++-- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); ++ wa_position(cnt) <= sci_data_out_i(3 downto 0); ++ sci_state <= GET_WA; ++ cnt := cnt + 1; ++end case; ++ ++if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then ++ SCI_NACK <= '1'; ++else ++ SCI_NACK <= '0'; ++end if; ++ ++end process; ++ ++ ++-- ------------------------------------------------- ++-- -- Debug Registers ++-- ------------------------------------------------- ++-- debug_reg(3 downto 0) <= rx_fsm_state; ++-- debug_reg(4) <= rx_k; ++-- debug_reg(5) <= rx_error; ++-- debug_reg(6) <= rx_los_low; ++-- debug_reg(7) <= rx_cdr_lol; ++-- ++-- debug_reg(8) <= tx_k; ++-- debug_reg(9) <= tx_pll_lol; ++-- debug_reg(10) <= lsm_status; ++-- debug_reg(11) <= make_link_reset_i; ++-- debug_reg(15 downto 12) <= tx_fsm_state; ++-- -- debug_reg(31 downto 24) <= tx_data; ++-- ++-- debug_reg(16) <= '0'; ++-- debug_reg(17) <= tx_allow; ++-- debug_reg(18) <= RESET; ++-- debug_reg(19) <= CLEAR; ++-- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); ++-- ++-- debug_reg(35 downto 32) <= wa_position(3 downto 0); ++-- debug_reg(36) <= debug_tx_control_i(6); ++-- debug_reg(39 downto 37) <= "000"; ++-- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); ++ ++ ++ STAT_DEBUG <= (others => '0'); --debug_reg; ++ ++ generated_status : for i in 0 to 3 generate ++ STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); ++ STAT_OP(i)(14) <= '0'; ++ STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset ++ STAT_OP(i)(12) <= '0'; ++ STAT_OP(i)(11) <= '0'; ++ STAT_OP(i)(10) <= rx_allow(i); ++ STAT_OP(i)(9) <= tx_allow(i); ++ STAT_OP(i)(8) <= got_link_ready_i(i) when rising_edge(rx_half_clk(i)); ++ STAT_OP(i)(7) <= send_link_reset_i(i); ++ STAT_OP(i)(6) <= make_link_reset_i(i); ++ STAT_OP(i)(5) <= request_retr_i(i); ++ STAT_OP(i)(4) <= start_retr_i(i); ++ STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; ++ end generate; ++ ++end med_ecp3_sfp_4_sync_down_arch; diff --cc code/soda_components.vhd index 4ce848f,a926589..a8daee8 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@@ -1,818 -1,818 +1,818 @@@ --library ieee; --use ieee.std_logic_1164.all; --use ieee.numeric_std.all; --use IEEE.STD_LOGIC_ARITH.ALL; -- --library work; --use work.trb_net_std.all; --use work.trb_net_components.all; --use work.trb_net16_hub_func.all; -- -- --package soda_components is -- -- attribute syn_useioff : boolean; -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- -- constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda -- constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda -- constant c_HUB_CHILDREN : natural range 1 to 4 := 4; -- number of children per soda-hub -- constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns -- constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns -- constant cSODA_CYCLE_PERIOD : natural range 1 to 50 := 25; -- cycle-period at which soda transmits, in ns -- constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns -- constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns -- constant cSODA_CALIBRATION_TIMEOUT : natural range 100 to 5000 := 250; -- soda clock-period in ns -- -- constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles -- constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles -- -- constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH; -- constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH; -- constant c_QUAD_MUX_WIDTH : integer := 3; --!!! -- -- subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0); -- type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0); -- type t_HUB_NIBL is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(3 downto 0); -- type t_HUB_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); -- type t_HUB_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); -- type t_HUB_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); -- -- type t_HUB_TIMER13 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(12 downto 0); -- type t_HUB_TIMER19 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(18 downto 0); -- type t_HUB_TIMER21 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(20 downto 0); -- -- type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET); -- type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT; -- -- subtype t_HUB_BIT_ARRAY is std_logic_vector(c_HUB_CHILDREN-1 downto 0); -- type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); -- type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); -- type t_HUB_LWORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); -- -- subtype t_QUAD_BIT is std_logic_vector(3 downto 0); -- type t_QUAD_NIBL is array(3 downto 0) of std_logic_vector(3 downto 0); -- type t_QUAD_BYTE is array(3 downto 0) of std_logic_vector(7 downto 0); -- type t_QUAD_9WORD is array(3 downto 0) of std_logic_vector(8 downto 0); -- type t_QUAD_WORD is array(3 downto 0) of std_logic_vector(15 downto 0); -- type t_QUAD_LWORD is array(3 downto 0) of std_logic_vector(31 downto 0); -- -- component soda_superburst_generator -- generic( -- BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts -- ); -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- --Internal Connection -- SODA_BURST_PULSE_IN : in std_logic := '0'; -- -- START_OF_SUPERBURST_OUT : out std_logic := '0'; -- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); -- SODA_CMD_WINDOW_OUT : out std_logic := '0' -- ); -- end component; -- -- component soda_packet_builder -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- --Internal Connection -- LINK_PHASE_IN : in std_logic := '0'; -- SODA_CYCLE_IN : in std_logic := '0'; -- SODA_CMD_STROBE_IN : in std_logic := '0'; -- -- START_OF_SUPERBURST : in std_logic := '0'; -- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); -- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit -- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- TIME_CAL_OUT : out std_logic := '0'; -- -- TX_DLM_PREVIEW_OUT : out std_logic := '0'; -- -- TX_DLM_OUT : out std_logic := '0'; -- -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_packet_handler -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- --Internal Connection -- START_OF_SUPERBURST_OUT : out std_logic := '0'; -- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); -- START_OF_CALIBRATION_OUT : out std_logic := '0'; -- SODA_CMD_VALID_OUT : out std_logic := '0'; -- SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); -- RX_DLM_IN : in std_logic; -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_d8crc8 -- crc-calculator/checker -- port( -- CLOCK : in std_logic; -- RESET : in std_logic; -- SOC_IN : in std_logic; -- DATA_IN : in std_logic_vector(7 downto 0); -- DATA_VALID_IN : in std_logic; -- EOC_IN : in std_logic; -- CRC_OUT : out std_logic_vector(7 downto 0); -- CRC_VALID_OUT : out std_logic -- ); -- end component; -- -- component soda_source -- box containing soda_source components -- port( -- SYSCLK : in std_logic; -- fabric clock -- SODACLK : in std_logic; -- clock for data to serdes -- RESET : in std_logic; -- synchronous reset -- --Internal Connection -- SODA_BURST_PULSE_IN : in std_logic := '0'; -- -- -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- RX_DLM_IN : in std_logic; -- TX_DLM_OUT : out std_logic; -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! -- LINK_PHASE_IN : in std_logic := '0'; --PL! -- -- -- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); -- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); -- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- SODA_READ_IN : in std_logic := '0'; -- SODA_WRITE_IN : in std_logic := '0'; -- SODA_ACK_OUT : out std_logic := '0'; -- LEDS_OUT : out std_logic_vector(3 downto 0) -- ); -- end component; -- -- component soda_4source is -- port( -- SYSCLK : in std_logic; -- fabric clock -- SODACLK : in std_logic; -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- -- SODA_BURST_PULSE_IN : in std_logic := '0'; -- SODA_CYCLE_IN : in std_logic := '0'; -- -- MULTIPLE DUPLEX DOWN-LINKS -- RX_DLM_IN : in t_HUB_BIT; -- RX_DLM_WORD_IN : in t_HUB_BYTE; -- TX_DLM_OUT : out t_HUB_BIT; -- TX_DLM_WORD_OUT : out t_HUB_BYTE; -- TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! -- LINK_PHASE_IN : in t_HUB_BIT; --PL! -- -- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); -- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); -- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- SODA_READ_IN : in std_logic := '0'; -- SODA_WRITE_IN : in std_logic := '0'; -- SODA_ACK_OUT : out std_logic := '0'; -- LEDS_OUT : out std_logic_vector(3 downto 0); -- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_hub -- port( -- SYSCLK : in std_logic; -- fabric clock -- SODACLK : in std_logic; -- recovered clock ---- SODA_OUT_CLK : in t_HUB_BIT; -- transmit clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- -- -- SINGLE DUBPLEX UP-LINK TO THE TOP -- RXUP_DLM_IN : in std_logic; -- RXUP_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- TXUP_DLM_OUT : out std_logic; -- TXUP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- TXUP_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! -- UPLINK_PHASE_IN : in std_logic := '0'; --PL! -- -- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM -- RXDN_DLM_IN : in t_HUB_BIT; -- RXDN_DLM_WORD_IN : in t_HUB_BYTE; -- TXDN_DLM_OUT : out t_HUB_BIT; -- TXDN_DLM_WORD_OUT : out t_HUB_BYTE; -- TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! -- DNLINK_PHASE_IN : in t_HUB_BIT; --PL! -- -- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); -- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); -- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- SODA_READ_IN : in std_logic := '0'; -- SODA_WRITE_IN : in std_logic := '0'; -- SODA_ACK_OUT : out std_logic := '0'; -- LEDS_OUT : out std_logic_vector(3 downto 0); -- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_client -- box containing soda_source components -- port( -- SYSCLK : in std_logic; -- fabric clock -- SODACLK : in std_logic; -- recovered clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- --Internal Connection -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- RX_DLM_IN : in std_logic; -- TX_DLM_OUT : out std_logic; -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! -- LINK_PHASE_IN : in std_logic := '0'; --PL! -- -- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); -- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); -- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- SODA_READ_IN : in std_logic := '0'; -- SODA_WRITE_IN : in std_logic := '0'; -- SODA_ACK_OUT : out std_logic := '0'; -- LEDS_OUT : out std_logic_vector(3 downto 0); -- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_reply_pkt_builder -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- --Internal Connection -- LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0'); -- START_OF_SUPERBURST : in std_logic := '0'; -- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); -- SODA_CMD_STROBE_IN : in std_logic := '0'; -- -- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit -- TX_DLM_PREVIEW_OUT : out std_logic := '0'; -- TX_DLM_OUT : out std_logic := '0'; -- -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_reply_handler -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- --Internal Connection -- -- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; -- EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- RX_DLM_IN : in std_logic := '0'; -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- REPLY_VALID_OUT : out std_logic := '0'; -- REPLY_OK_OUT : out std_logic := '0' -- ); -- end component; -- -- component soda_calibration_timer -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- CLK_EN : in std_logic; -- --Internal Connection -- START_CALIBRATION : in std_logic := '0'; -- END_CALIBRATION : in std_logic := '0'; -- VALID_OUT : out std_logic := '0'; -- -- CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); -- TIMEOUT_ERROR : out std_logic := '0' -- ); -- end component; -- -- component spi_flash_and_fpga_reload -- port( -- CLK_IN : in std_logic; -- RESET_IN : in std_logic; -- -- BUS_ADDR_IN : in std_logic_vector(8 downto 0); -- BUS_READ_IN : in std_logic; -- BUS_WRITE_IN : in std_logic; -- BUS_DATAREADY_OUT : out std_logic; -- BUS_WRITE_ACK_OUT : out std_logic; -- BUS_UNKNOWN_ADDR_OUT : out std_logic; -- BUS_NO_MORE_DATA_OUT : out std_logic; -- BUS_DATA_IN : in std_logic_vector(31 downto 0); -- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- -- DO_REBOOT_IN : in std_logic; -- PROGRAMN : out std_logic; -- -- SPI_CS_OUT : out std_logic; -- SPI_SCK_OUT : out std_logic; -- SPI_SDO_OUT : out std_logic; -- SPI_SDI_IN : in std_logic -- ); -- end component; -- -- component soda_start_of_burst_faker -- generic( -- CLOCK_PERIOD : natural range 1 to 20 := 5; -- clock-period in ns -- BURST_PERIOD : natural range 1 to 2400 := 2400 -- burst-period in ns -- ); -- port( -- SYSCLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- SODA_BURST_PULSE_OUT : out std_logic := '0' -- ); -- end component; -- -- component soda_start_of_burst_control is -- generic( -- CLOCK_PERIOD : natural range 1 to 25 := cSODA_CLOCK_PERIOD; -- clock-period in ns -- CYCLE_PERIOD : natural range 5 to 50 := cSODA_CYCLE_PERIOD; -- cycle-period in ns -- BURST_PERIOD : natural := cBURST_PERIOD -- burst-period in ns -- ); -- port( -- SODA_CLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- SODA_BURST_PULSE_OUT : out std_logic := '0'; -- SODA_40MHZ_CYCLE_OUT : out std_logic := '0' -- ); -- end component; -- -- component posedge_to_pulse -- port ( -- IN_CLK : in std_logic; -- OUT_CLK : in std_logic; -- CLK_EN : in std_logic; -- SIGNAL_IN : in std_logic; -- PULSE_OUT : out std_logic -- ); -- end component; -- -- component med_ecp3_sfp_sync_down is -- generic( -- SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_NO); --select slave mode -- port( -- OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- -- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes -- -- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes -- --Internal Connection TX -- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); -- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); -- MED_DATAREADY_IN : in std_logic; -- MED_READ_OUT : out std_logic := '0'; -- --Internal Connection RX -- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); -- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); -- MED_DATAREADY_OUT : out std_logic := '0'; -- MED_READ_IN : in std_logic; -- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- -- --Sync operation -- RX_DLM : out std_logic := '0'; -- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; -- TX_DLM : in std_logic := '0'; -- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; -- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! -- LINK_PHASE_OUT : out std_logic := '0'; --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in std_logic; -- SD_RXD_N_IN : in std_logic; -- SD_TXD_P_OUT : out std_logic; -- SD_TXD_N_OUT : out std_logic; -- SD_REFCLK_P_IN : in std_logic; --not used -- SD_REFCLK_N_IN : in std_logic; --not used -- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port -- STAT_OP : out std_logic_vector (15 downto 0); -- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); -- end component; -- -- component med_ecp3_sfp_4_sync_down is -- generic( SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_NO); --select slave mode -- port( -- OSC_CLK : in std_logic; -- 200 MHz reference clock -- TX_DATACLK : in std_logic; -- 200 MHz data clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- --Internal Connection TX -- MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0); -- MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(c_QUAD_NUM_WIDTH-1 downto 0); -- MED_DATAREADY_IN : in std_logic_vector(3 downto 0); -- MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); -- --Internal Connection RX -- MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); -- MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); -- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); -- MED_READ_IN : in std_logic_vector(3 downto 0); -- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- -- --Sync operation -- RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in t_HUB_BIT; --std_logic; -- SD_RXD_N_IN : in t_HUB_BIT; --std_logic; -- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; -- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; -- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used -- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used -- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port - STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); - CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); - STAT_OP : out std_logic_vector (63 downto 0); - CTRL_OP : in std_logic_vector (63 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); -- end component; -- -- component med_ecp3_sfp_4_sync_down_EP is -- generic( SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_NO); --select slave mode -- port( -- OSC_CLK : in std_logic; -- 200 MHz reference clock -- TX_DATACLK : in std_logic; -- 200 MHz data clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- -- --Sync operation -- RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in t_HUB_BIT; --std_logic; -- SD_RXD_N_IN : in t_HUB_BIT; --std_logic; -- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; -- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; -- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used -- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used -- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port ---- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); ---- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); -- end component; -- -- component med_ecp3_sfp_sync_up is -- generic( -- SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_YES --select slave mode -- ); -- port( -- OSCCLK : in std_logic; -- 200 MHz reference clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --Internal Connection TX -- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); -- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); -- MED_DATAREADY_IN : in std_logic; -- MED_READ_OUT : out std_logic := '0'; -- --Internal Connection RX -- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); -- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); -- MED_DATAREADY_OUT : out std_logic := '0'; -- MED_READ_IN : in std_logic; -- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz -- TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz -- RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 -- --Sync operation -- RX_DLM : out std_logic := '0'; -- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; -- TX_DLM : in std_logic := '0'; -- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; -- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! -- LINK_PHASE_OUT : out std_logic := '0'; --PL! -- LINK_READY_OUT : out std_logic := '0'; --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in std_logic; -- SD_RXD_N_IN : in std_logic; -- SD_TXD_P_OUT : out std_logic; -- SD_TXD_N_OUT : out std_logic; -- SD_REFCLK_P_IN : in std_logic; --not used -- SD_REFCLK_N_IN : in std_logic; --not used -- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port -- STAT_OP : out std_logic_vector (15 downto 0); -- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); -- end component; -- -- component soda_only_ecp3_sfp_sync_up -- generic( SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_YES); --select slave mode -- port( -- OSCCLK : in std_logic; -- 200 MHz reference clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- -- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 -- -- --Sync operation -- RX_DLM : out std_logic := '0'; -- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; -- TX_DLM : in std_logic := '0'; -- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; -- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! -- LINK_PHASE_OUT : out std_logic := '0'; --PL! -- LINK_READY_OUT : out std_logic := '0'; --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in std_logic; -- SD_RXD_N_IN : in std_logic; -- SD_TXD_P_OUT : out std_logic; -- SD_TXD_N_OUT : out std_logic; -- SD_REFCLK_P_IN : in std_logic; --not used -- SD_REFCLK_N_IN : in std_logic; --not used -- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0' -- ); -- end component; -- -- component med_ecp3_sfp_4_soda is -- generic( SERDES_NUM : integer range 0 to 3 := 0; -- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave -- port( -- OSC_CLK : in std_logic; -- 200 MHz reference clock -- TX_DATACLK : in std_logic; -- 200 MHz data clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --------------------------------------------------------------------------------------------------------------------------------------------------------- ---- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. -- --------------------------------------------------------------------------------------------------------------------------------------------------------- -- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz -- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz -- -- --Sync operation -- RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); -- TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); -- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! -- -- --SFP Connection -- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); -- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used -- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used -- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port ---- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); ---- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); -- end component; -- -- component Cu_trb_net16_soda_sync_ecp3_sfp -- port( -- OSCCLK : in std_logic; -- 200 MHz reference clock -- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock -- RESET : in std_logic; -- synchronous reset -- CLEAR : in std_logic; -- asynchronous reset -- --Internal Connection TX -- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); -- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); -- MED_DATAREADY_IN : in std_logic; -- MED_READ_OUT : out std_logic := '0'; -- --Internal Connection RX -- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); -- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); -- MED_DATAREADY_OUT : out std_logic := '0'; -- MED_READ_IN : in std_logic; -- -- --Copper SFP Connection -- CU_RXD_P_IN : in std_logic; -- CU_RXD_N_IN : in std_logic; -- CU_TXD_P_OUT : out std_logic; -- CU_TXD_N_OUT : out std_logic; -- CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable -- --Fiber/sync SFP Connection -- SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz -- SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz -- SYNC_DLM_IN : in std_logic; -- SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0); -- SYNC_DLM_OUT : out std_logic; ++library ieee; ++use ieee.std_logic_1164.all; ++use ieee.numeric_std.all; ++use IEEE.STD_LOGIC_ARITH.ALL; ++ ++library work; ++use work.trb_net_std.all; ++use work.trb_net_components.all; ++use work.trb_net16_hub_func.all; ++ ++ ++package soda_components is ++ ++ attribute syn_useioff : boolean; ++ attribute syn_keep : boolean; ++ attribute syn_preserve : boolean; ++ ++ constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda ++ constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda ++ constant c_HUB_CHILDREN : natural range 1 to 4 := 4; -- number of children per soda-hub ++ constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns ++ constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns ++ constant cSODA_CYCLE_PERIOD : natural range 1 to 50 := 25; -- cycle-period at which soda transmits, in ns ++ constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns ++ constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns ++ constant cSODA_CALIBRATION_TIMEOUT : natural range 100 to 5000 := 250; -- soda clock-period in ns ++ ++ constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles ++ constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles ++ ++ constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH; ++ constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH; ++ constant c_QUAD_MUX_WIDTH : integer := 3; --!!! ++ ++ subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0); ++ type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0); ++ type t_HUB_NIBL is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(3 downto 0); ++ type t_HUB_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); ++ type t_HUB_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); ++ type t_HUB_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); ++ ++ type t_HUB_TIMER13 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(12 downto 0); ++ type t_HUB_TIMER19 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(18 downto 0); ++ type t_HUB_TIMER21 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(20 downto 0); ++ ++ type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET); ++ type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT; ++ ++ subtype t_HUB_BIT_ARRAY is std_logic_vector(c_HUB_CHILDREN-1 downto 0); ++ type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); ++ type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); ++ type t_HUB_LWORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); ++ ++ subtype t_QUAD_BIT is std_logic_vector(3 downto 0); ++ type t_QUAD_NIBL is array(3 downto 0) of std_logic_vector(3 downto 0); ++ type t_QUAD_BYTE is array(3 downto 0) of std_logic_vector(7 downto 0); ++ type t_QUAD_9WORD is array(3 downto 0) of std_logic_vector(8 downto 0); ++ type t_QUAD_WORD is array(3 downto 0) of std_logic_vector(15 downto 0); ++ type t_QUAD_LWORD is array(3 downto 0) of std_logic_vector(31 downto 0); ++ ++ component soda_superburst_generator ++ generic( ++ BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts ++ ); ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ --Internal Connection ++ SODA_BURST_PULSE_IN : in std_logic := '0'; -- ++ START_OF_SUPERBURST_OUT : out std_logic := '0'; ++ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); ++ SODA_CMD_WINDOW_OUT : out std_logic := '0' ++ ); ++ end component; ++ ++ component soda_packet_builder ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ --Internal Connection ++ LINK_PHASE_IN : in std_logic := '0'; ++ SODA_CYCLE_IN : in std_logic := '0'; ++ SODA_CMD_STROBE_IN : in std_logic := '0'; -- ++ START_OF_SUPERBURST : in std_logic := '0'; ++ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); ++ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit ++ EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ TIME_CAL_OUT : out std_logic := '0'; -- ++ TX_DLM_PREVIEW_OUT : out std_logic := '0'; -- ++ TX_DLM_OUT : out std_logic := '0'; -- ++ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_packet_handler ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ --Internal Connection ++ START_OF_SUPERBURST_OUT : out std_logic := '0'; ++ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); ++ START_OF_CALIBRATION_OUT : out std_logic := '0'; ++ SODA_CMD_VALID_OUT : out std_logic := '0'; ++ SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); ++ RX_DLM_IN : in std_logic; ++ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_d8crc8 -- crc-calculator/checker ++ port( ++ CLOCK : in std_logic; ++ RESET : in std_logic; ++ SOC_IN : in std_logic; ++ DATA_IN : in std_logic_vector(7 downto 0); ++ DATA_VALID_IN : in std_logic; ++ EOC_IN : in std_logic; ++ CRC_OUT : out std_logic_vector(7 downto 0); ++ CRC_VALID_OUT : out std_logic ++ ); ++ end component; ++ ++ component soda_source -- box containing soda_source components ++ port( ++ SYSCLK : in std_logic; -- fabric clock ++ SODACLK : in std_logic; -- clock for data to serdes ++ RESET : in std_logic; -- synchronous reset ++ --Internal Connection ++ SODA_BURST_PULSE_IN : in std_logic := '0'; -- ++ ++ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ RX_DLM_IN : in std_logic; ++ TX_DLM_OUT : out std_logic; ++ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! ++ LINK_PHASE_IN : in std_logic := '0'; --PL! ++ ++ ++ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); ++ SODA_READ_IN : in std_logic := '0'; ++ SODA_WRITE_IN : in std_logic := '0'; ++ SODA_ACK_OUT : out std_logic := '0'; ++ LEDS_OUT : out std_logic_vector(3 downto 0) ++ ); ++ end component; ++ ++ component soda_4source is ++ port( ++ SYSCLK : in std_logic; -- fabric clock ++ SODACLK : in std_logic; ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ ++ SODA_BURST_PULSE_IN : in std_logic := '0'; ++ SODA_CYCLE_IN : in std_logic := '0'; ++ -- MULTIPLE DUPLEX DOWN-LINKS ++ RX_DLM_IN : in t_HUB_BIT; ++ RX_DLM_WORD_IN : in t_HUB_BYTE; ++ TX_DLM_OUT : out t_HUB_BIT; ++ TX_DLM_WORD_OUT : out t_HUB_BYTE; ++ TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! ++ LINK_PHASE_IN : in t_HUB_BIT; --PL! ++ ++ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); ++ SODA_READ_IN : in std_logic := '0'; ++ SODA_WRITE_IN : in std_logic := '0'; ++ SODA_ACK_OUT : out std_logic := '0'; ++ LEDS_OUT : out std_logic_vector(3 downto 0); ++ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_hub ++ port( ++ SYSCLK : in std_logic; -- fabric clock ++ SODACLK : in std_logic; -- recovered clock ++-- SODA_OUT_CLK : in t_HUB_BIT; -- transmit clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ ++ -- SINGLE DUBPLEX UP-LINK TO THE TOP ++ RXUP_DLM_IN : in std_logic; ++ RXUP_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ TXUP_DLM_OUT : out std_logic; ++ TXUP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ TXUP_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! ++ UPLINK_PHASE_IN : in std_logic := '0'; --PL! ++ ++ -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM ++ RXDN_DLM_IN : in t_HUB_BIT; ++ RXDN_DLM_WORD_IN : in t_HUB_BYTE; ++ TXDN_DLM_OUT : out t_HUB_BIT; ++ TXDN_DLM_WORD_OUT : out t_HUB_BYTE; ++ TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! ++ DNLINK_PHASE_IN : in t_HUB_BIT; --PL! ++ ++ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); ++ SODA_READ_IN : in std_logic := '0'; ++ SODA_WRITE_IN : in std_logic := '0'; ++ SODA_ACK_OUT : out std_logic := '0'; ++ LEDS_OUT : out std_logic_vector(3 downto 0); ++ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_client -- box containing soda_source components ++ port( ++ SYSCLK : in std_logic; -- fabric clock ++ SODACLK : in std_logic; -- recovered clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ --Internal Connection ++ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ RX_DLM_IN : in std_logic; ++ TX_DLM_OUT : out std_logic; ++ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! ++ LINK_PHASE_IN : in std_logic := '0'; --PL! ++ ++ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); ++ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); ++ SODA_READ_IN : in std_logic := '0'; ++ SODA_WRITE_IN : in std_logic := '0'; ++ SODA_ACK_OUT : out std_logic := '0'; ++ LEDS_OUT : out std_logic_vector(3 downto 0); ++ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_reply_pkt_builder ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ --Internal Connection ++ LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0'); ++ START_OF_SUPERBURST : in std_logic := '0'; ++ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); ++ SODA_CMD_STROBE_IN : in std_logic := '0'; -- ++ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit ++ TX_DLM_PREVIEW_OUT : out std_logic := '0'; ++ TX_DLM_OUT : out std_logic := '0'; -- ++ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_reply_handler ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ --Internal Connection ++ -- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; ++ EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ RX_DLM_IN : in std_logic := '0'; ++ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ REPLY_VALID_OUT : out std_logic := '0'; ++ REPLY_OK_OUT : out std_logic := '0' ++ ); ++ end component; ++ ++ component soda_calibration_timer ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ CLK_EN : in std_logic; ++ --Internal Connection ++ START_CALIBRATION : in std_logic := '0'; ++ END_CALIBRATION : in std_logic := '0'; ++ VALID_OUT : out std_logic := '0'; -- ++ CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); ++ TIMEOUT_ERROR : out std_logic := '0' ++ ); ++ end component; ++ ++ component spi_flash_and_fpga_reload ++ port( ++ CLK_IN : in std_logic; ++ RESET_IN : in std_logic; ++ ++ BUS_ADDR_IN : in std_logic_vector(8 downto 0); ++ BUS_READ_IN : in std_logic; ++ BUS_WRITE_IN : in std_logic; ++ BUS_DATAREADY_OUT : out std_logic; ++ BUS_WRITE_ACK_OUT : out std_logic; ++ BUS_UNKNOWN_ADDR_OUT : out std_logic; ++ BUS_NO_MORE_DATA_OUT : out std_logic; ++ BUS_DATA_IN : in std_logic_vector(31 downto 0); ++ BUS_DATA_OUT : out std_logic_vector(31 downto 0); ++ ++ DO_REBOOT_IN : in std_logic; ++ PROGRAMN : out std_logic; ++ ++ SPI_CS_OUT : out std_logic; ++ SPI_SCK_OUT : out std_logic; ++ SPI_SDO_OUT : out std_logic; ++ SPI_SDI_IN : in std_logic ++ ); ++ end component; ++ ++ component soda_start_of_burst_faker ++ generic( ++ CLOCK_PERIOD : natural range 1 to 20 := 5; -- clock-period in ns ++ BURST_PERIOD : natural range 1 to 2400 := 2400 -- burst-period in ns ++ ); ++ port( ++ SYSCLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ SODA_BURST_PULSE_OUT : out std_logic := '0' ++ ); ++ end component; ++ ++ component soda_start_of_burst_control is ++ generic( ++ CLOCK_PERIOD : natural range 1 to 25 := cSODA_CLOCK_PERIOD; -- clock-period in ns ++ CYCLE_PERIOD : natural range 5 to 50 := cSODA_CYCLE_PERIOD; -- cycle-period in ns ++ BURST_PERIOD : natural := cBURST_PERIOD -- burst-period in ns ++ ); ++ port( ++ SODA_CLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ SODA_BURST_PULSE_OUT : out std_logic := '0'; ++ SODA_40MHZ_CYCLE_OUT : out std_logic := '0' ++ ); ++ end component; ++ ++ component posedge_to_pulse ++ port ( ++ IN_CLK : in std_logic; ++ OUT_CLK : in std_logic; ++ CLK_EN : in std_logic; ++ SIGNAL_IN : in std_logic; ++ PULSE_OUT : out std_logic ++ ); ++ end component; ++ ++ component med_ecp3_sfp_sync_down is ++ generic( ++ SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_NO); --select slave mode ++ port( ++ OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ -- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes ++ -- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes ++ --Internal Connection TX ++ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); ++ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); ++ MED_DATAREADY_IN : in std_logic; ++ MED_READ_OUT : out std_logic := '0'; ++ --Internal Connection RX ++ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); ++ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); ++ MED_DATAREADY_OUT : out std_logic := '0'; ++ MED_READ_IN : in std_logic; ++ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ ++ --Sync operation ++ RX_DLM : out std_logic := '0'; ++ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM : in std_logic := '0'; ++ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! ++ LINK_PHASE_OUT : out std_logic := '0'; --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in std_logic; ++ SD_RXD_N_IN : in std_logic; ++ SD_TXD_P_OUT : out std_logic; ++ SD_TXD_N_OUT : out std_logic; ++ SD_REFCLK_P_IN : in std_logic; --not used ++ SD_REFCLK_N_IN : in std_logic; --not used ++ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++ STAT_OP : out std_logic_vector (15 downto 0); ++ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component med_ecp3_sfp_4_sync_down is ++ generic( SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_NO); --select slave mode ++ port( ++ OSC_CLK : in std_logic; -- 200 MHz reference clock ++ TX_DATACLK : in std_logic; -- 200 MHz data clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ --Internal Connection TX ++ MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0); ++ MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(c_QUAD_NUM_WIDTH-1 downto 0); ++ MED_DATAREADY_IN : in std_logic_vector(3 downto 0); ++ MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); ++ --Internal Connection RX ++ MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); ++ MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); ++ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); ++ MED_READ_IN : in std_logic_vector(3 downto 0); ++ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ ++ --Sync operation ++ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in t_HUB_BIT; --std_logic; ++ SD_RXD_N_IN : in t_HUB_BIT; --std_logic; ++ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; ++ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; ++ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++ STAT_OP : out t_HUB_WORD; ++ CTRL_OP : in t_HUB_WORD; ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component med_ecp3_sfp_4_sync_down_EP is ++ generic( SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_NO); --select slave mode ++ port( ++ OSC_CLK : in std_logic; -- 200 MHz reference clock ++ TX_DATACLK : in std_logic; -- 200 MHz data clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ ++ --Sync operation ++ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in t_HUB_BIT; --std_logic; ++ SD_RXD_N_IN : in t_HUB_BIT; --std_logic; ++ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; ++ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; ++ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); ++-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component med_ecp3_sfp_sync_up is ++ generic( ++ SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_YES --select slave mode ++ ); ++ port( ++ OSCCLK : in std_logic; -- 200 MHz reference clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --Internal Connection TX ++ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); ++ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); ++ MED_DATAREADY_IN : in std_logic; ++ MED_READ_OUT : out std_logic := '0'; ++ --Internal Connection RX ++ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); ++ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); ++ MED_DATAREADY_OUT : out std_logic := '0'; ++ MED_READ_IN : in std_logic; ++ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz ++ TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz ++ RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 ++ --Sync operation ++ RX_DLM : out std_logic := '0'; ++ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM : in std_logic := '0'; ++ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! ++ LINK_PHASE_OUT : out std_logic := '0'; --PL! ++ LINK_READY_OUT : out std_logic := '0'; --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in std_logic; ++ SD_RXD_N_IN : in std_logic; ++ SD_TXD_P_OUT : out std_logic; ++ SD_TXD_N_OUT : out std_logic; ++ SD_REFCLK_P_IN : in std_logic; --not used ++ SD_REFCLK_N_IN : in std_logic; --not used ++ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++ STAT_OP : out std_logic_vector (15 downto 0); ++ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_only_ecp3_sfp_sync_up ++ generic( SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_YES); --select slave mode ++ port( ++ OSCCLK : in std_logic; -- 200 MHz reference clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ ++ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 ++ ++ --Sync operation ++ RX_DLM : out std_logic := '0'; ++ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM : in std_logic := '0'; ++ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; ++ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! ++ LINK_PHASE_OUT : out std_logic := '0'; --PL! ++ LINK_READY_OUT : out std_logic := '0'; --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in std_logic; ++ SD_RXD_N_IN : in std_logic; ++ SD_TXD_P_OUT : out std_logic; ++ SD_TXD_N_OUT : out std_logic; ++ SD_REFCLK_P_IN : in std_logic; --not used ++ SD_REFCLK_N_IN : in std_logic; --not used ++ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0' ++ ); ++ end component; ++ ++ component med_ecp3_sfp_4_soda is ++ generic( SERDES_NUM : integer range 0 to 3 := 0; ++ IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave ++ port( ++ OSC_CLK : in std_logic; -- 200 MHz reference clock ++ TX_DATACLK : in std_logic; -- 200 MHz data clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++-- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. ++ --------------------------------------------------------------------------------------------------------------------------------------------------------- ++ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz ++ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz ++ ++ --Sync operation ++ RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); ++ TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); ++ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! ++ ++ --SFP Connection ++ SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); ++ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used ++ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); ++-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component Cu_trb_net16_soda_sync_ecp3_sfp ++ port( ++ OSCCLK : in std_logic; -- 200 MHz reference clock ++ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock ++ RESET : in std_logic; -- synchronous reset ++ CLEAR : in std_logic; -- asynchronous reset ++ --Internal Connection TX ++ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); ++ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); ++ MED_DATAREADY_IN : in std_logic; ++ MED_READ_OUT : out std_logic := '0'; ++ --Internal Connection RX ++ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); ++ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); ++ MED_DATAREADY_OUT : out std_logic := '0'; ++ MED_READ_IN : in std_logic; ++ ++ --Copper SFP Connection ++ CU_RXD_P_IN : in std_logic; ++ CU_RXD_N_IN : in std_logic; ++ CU_TXD_P_OUT : out std_logic; ++ CU_TXD_N_OUT : out std_logic; ++ CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable ++ --Fiber/sync SFP Connection ++ SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz ++ SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz ++ SYNC_DLM_IN : in std_logic; ++ SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0); ++ SYNC_DLM_OUT : out std_logic; SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0); -- SYNC_RXD_P_IN : in std_logic; -- SYNC_RXD_N_IN : in std_logic; -- SYNC_TXD_P_OUT : out std_logic; -- SYNC_TXD_N_OUT : out std_logic; -- SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) -- SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable -- --Control Interface -- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); -- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); -- SCI_READ : in std_logic := '0'; -- SCI_WRITE : in std_logic := '0'; -- SCI_ACK : out std_logic := '0'; -- SCI_NACK : out std_logic := '0'; -- -- Status and control port -- STAT_OP : out std_logic_vector (15 downto 0); -- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); -- STAT_DEBUG : out std_logic_vector (63 downto 0); -- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') -- ); ++ SYNC_RXD_P_IN : in std_logic; ++ SYNC_RXD_N_IN : in std_logic; ++ SYNC_TXD_P_OUT : out std_logic; ++ SYNC_TXD_N_OUT : out std_logic; ++ SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) ++ SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) ++ SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable ++ --Control Interface ++ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); ++ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); ++ SCI_READ : in std_logic := '0'; ++ SCI_WRITE : in std_logic := '0'; ++ SCI_ACK : out std_logic := '0'; ++ SCI_NACK : out std_logic := '0'; ++ -- Status and control port ++ STAT_OP : out std_logic_vector (15 downto 0); ++ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); ++ STAT_DEBUG : out std_logic_vector (63 downto 0); ++ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ++ ); ++ end component; ++ ++ component soda_tx_control ++ port( ++ CLK_200 : in std_logic; ++ CLK_100 : in std_logic; ++ RESET_IN : in std_logic; ++ ++ TX_DATA_IN : in std_logic_vector(15 downto 0); ++ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); ++ TX_WRITE_IN : in std_logic; ++ TX_READ_OUT : out std_logic; ++ ++ TX_DATA_OUT : out std_logic_vector( 7 downto 0); ++ TX_K_OUT : out std_logic; ++ ++ REQUEST_RETRANSMIT_IN : in std_logic := '0'; ++ REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); ++ ++ START_RETRANSMIT_IN : in std_logic := '0'; ++ START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); ++ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM ++ TX_DLM_PREVIEW_IN : in std_logic := '0'; ++ SEND_DLM : in std_logic := '0'; ++ SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); ++ ++ SEND_LINK_RESET_IN : in std_logic := '0'; ++ TX_ALLOW_IN : in std_logic := '0'; ++ RX_ALLOW_IN : in std_logic := '0'; ++ LINK_PHASE_OUT : out std_logic := '0'; ++ ++ DEBUG_OUT : out std_logic_vector(31 downto 0); ++ STAT_REG_OUT : out std_logic_vector(31 downto 0) ++ ); ++ end component; ++ ++ component soda_cmd_window_generator ++ generic( CLOCK_PERIOD : natural range 1 to 20 := cSODA_CLOCK_PERIOD; -- clock-period in ns ++ COMMAND_WINDOS_SIZE : natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE -- command window size in ns ++ ); ++ port( ++ SODACLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset ++ START_OF_SUPERBURST_IN : in std_logic := '0'; -- ++ SODA_CMD_WINDOW_OUT : out std_logic := '0' ++ ); end component; -- -- component soda_tx_control -- port( -- CLK_200 : in std_logic; -- CLK_100 : in std_logic; -- RESET_IN : in std_logic; -- -- TX_DATA_IN : in std_logic_vector(15 downto 0); -- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); -- TX_WRITE_IN : in std_logic; -- TX_READ_OUT : out std_logic; -- -- TX_DATA_OUT : out std_logic_vector( 7 downto 0); -- TX_K_OUT : out std_logic; -- -- REQUEST_RETRANSMIT_IN : in std_logic := '0'; -- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); -- -- START_RETRANSMIT_IN : in std_logic := '0'; -- START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); -- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM -- TX_DLM_PREVIEW_IN : in std_logic := '0'; -- SEND_DLM : in std_logic := '0'; -- SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); -- -- SEND_LINK_RESET_IN : in std_logic := '0'; -- TX_ALLOW_IN : in std_logic := '0'; -- RX_ALLOW_IN : in std_logic := '0'; -- LINK_PHASE_OUT : out std_logic := '0'; -- -- DEBUG_OUT : out std_logic_vector(31 downto 0); -- STAT_REG_OUT : out std_logic_vector(31 downto 0) -- ); -- end component; -- -- component soda_cmd_window_generator -- generic( CLOCK_PERIOD : natural range 1 to 20 := cSODA_CLOCK_PERIOD; -- clock-period in ns -- COMMAND_WINDOS_SIZE : natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE -- command window size in ns -- ); -- port( -- SODACLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset -- START_OF_SUPERBURST_IN : in std_logic := '0'; -- -- SODA_CMD_WINDOW_OUT : out std_logic := '0' -- ); -- end component; -- -- component soda_clockscaler is -- port( -- CLK : in std_logic; -- fabric clock -- RESET : in std_logic; -- synchronous reset ++ ++ component soda_clockscaler is ++ port( ++ CLK : in std_logic; -- fabric clock ++ RESET : in std_logic; -- synchronous reset CLOCK_ENABLE_OUT : out std_logic := '0'; -- CLOCK_OUT : out std_logic -- ); ++ CLOCK_OUT : out std_logic ++ ); end component; -- component DCS -- -- synthesis translate_off -- generic -- ( -- DCSMODE : string :=“POS” -- ); -- -- synthesis translate_on -- port ( -- CLK0 : in std_logic ; -- CLK1 : in std_logic ; -- SEL : in std_logic ; ++ component DCS ++ -- synthesis translate_off ++ generic ++ ( ++ DCSMODE : string :=“POS” ++ ); ++ -- synthesis translate_on ++ port ( ++ CLK0 : in std_logic ; ++ CLK1 : in std_logic ; ++ SEL : in std_logic ; DCSOUT : out std_logic -- ); -- end component; ++ ); ++ end component; -- component dff_re ++ component dff_re Port ( -- rst : in STD_LOGIC; -- clk : in STD_LOGIC; -- enable : in STD_LOGIC; -- d : in STD_LOGIC_VECTOR; -- q : out STD_LOGIC_VECTOR; -- data_valid : out STD_LOGIC -- ); ++ rst : in STD_LOGIC; ++ clk : in STD_LOGIC; ++ enable : in STD_LOGIC; ++ d : in STD_LOGIC_VECTOR; ++ q : out STD_LOGIC_VECTOR; ++ data_valid : out STD_LOGIC ++ ); end component; -- --end package; ++ ++end package;