From: Michael Boehmer Date: Mon, 8 Aug 2022 14:53:00 +0000 (+0200) Subject: bug fixed in inserter, destroyed SOP kommas X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2fea059f0895a404924ebf964bd0ff4dc8d341c3;p=trbnet.git bug fixed in inserter, destroyed SOP kommas --- diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd index 669ac3c..22bd896 100644 --- a/gbe_trb/base/inserter.vhd +++ b/gbe_trb/base/inserter.vhd @@ -18,7 +18,9 @@ entity inserter is TX_CD_OUT : out std_logic; -- DLM stuff DLM_DATA_IN : in std_logic_vector(7 downto 0); - DLM_INJECT_IN : in std_logic + DLM_INJECT_IN : in std_logic; + -- + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity inserter; @@ -50,10 +52,11 @@ architecture inserter_arch of inserter is signal inject_k : std_logic; signal inject_d : std_logic; - - signal phy_cd_q : std_logic; - signal phy_k_q : std_logic; - signal phy_d_q : std_logic_vector(7 downto 0); + + -- 9 = CD, 8 = K, 7..0 = D + signal delay_qqq : std_logic_vector(9 downto 0); + signal delay_qq : std_logic_vector(9 downto 0); + signal delay_q : std_logic_vector(9 downto 0); signal idle_x : std_logic; signal idle_int : std_logic; @@ -64,24 +67,42 @@ architecture inserter_arch of inserter is signal drop_req_x : std_logic; signal ins_cnt : unsigned(2 downto 0); - + begin + DEBUG_OUT(0) <= drop_req_x; + DEBUG_OUT(1) <= idle_int; + DEBUG_OUT(2) <= fifo_wr_x; + DEBUG_OUT(3) <= fifo_rd_x; + DEBUG_OUT(4) <= fifo_empty_x; + DEBUG_OUT(5) <= remove_x; + DEBUG_OUT(6) <= remove_int; + DEBUG_OUT(7) <= inject_k; + DEBUG_OUT(8) <= inject_d; + + DEBUG_OUT(15 downto 9) <= (others => '0'); + -- Syncing and delaying signals for /IT recognition THE_SYNC_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - phy_d_q <= PHY_D_IN; - phy_k_q <= PHY_K_IN; - phy_cd_q <= PHY_CD_IN; + -- third stage + delay_qqq <= delay_qq; + -- second stage + delay_qq <= delay_q; + -- first stage + delay_q(7 downto 0) <= PHY_D_IN; + delay_q(8) <= PHY_K_IN; + delay_q(9) <= PHY_CD_IN; + -- sync idle_int <= idle_x; remove_int <= remove_x; end if; end process THE_SYNC_PROC; - -- we have an /I/ candidate for dropping - idle_x <= '1' when ((phy_d_q = x"bc") and (phy_k_q = '1') and (phy_cd_q = '0') and - (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) + -- we have an /I/ candidate for dropping (in the input and first stage) + idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and + (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) else '0'; -- insert counter @@ -90,9 +111,9 @@ begin if( rising_edge(CLK) ) then if ( RESET = '1' ) then ins_cnt <= (others => '0'); - elsif( (DLM_INJECT_IN = '1') and (remove_x = '0') ) then + elsif( (DLM_INJECT_IN = '1') and (remove_x = '0') ) then -- maybe inject_d ? ins_cnt <= ins_cnt + 1; - elsif( (DLM_INJECT_IN = '0') and (remove_x = '1') ) then + elsif( (DLM_INJECT_IN = '0') and (remove_x = '1') ) then -- maybe inject_d ? ins_cnt <= ins_cnt - 1; end if; end if; @@ -109,19 +130,17 @@ begin -- FIFO THE_FIFO: fifo_inserter port map( - DATA(9) => phy_cd_q, - DATA(8) => phy_k_q, - DATA(7 downto 0) => phy_d_q, - CLOCK => CLK, - WREN => fifo_wr_x, - RDEN => fifo_rd_x, - RESET => RESET, - Q(9) => tx_cd_int, - Q(8) => tx_k_int, - Q(7 downto 0) => tx_d_int, - EMPTY => open, - FULL => open, - ALMOSTEMPTY => fifo_empty_x + DATA => delay_qqq, + CLOCK => CLK, + WREN => fifo_wr_x, + RDEN => fifo_rd_x, + RESET => RESET, + Q(9) => tx_cd_int, + Q(8) => tx_k_int, + Q(7 downto 0) => tx_d_int, + EMPTY => open, + FULL => open, + ALMOSTEMPTY => fifo_empty_x ); -- diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd index e2f272c..dcda515 100644 --- a/gbe_trb/base/remover.vhd +++ b/gbe_trb/base/remover.vhd @@ -1,61 +1,73 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity remover is - port( - CLK : in std_logic; - RESET : in std_logic; - -- SerDes output +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity remover is + port( + CLK : in std_logic; + RESET : in std_logic; + -- SerDes output RX_D_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; + RX_K_IN : in std_logic; -- PHY input - PHY_D_OUT : out std_logic_vector(7 downto 0); + PHY_D_OUT : out std_logic_vector(7 downto 0); PHY_K_OUT : out std_logic; -- DLM stuff DLM_DATA_OUT : out std_logic_vector(7 downto 0); - DLM_FOUND_OUT : out std_logic - ); -end entity remover; - -architecture remover_arch of remover is - --- Components - component fifo_remover - port( - DATA : in std_logic_vector(8 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - WCNT : out std_logic_vector(4 downto 0); - Q : out std_logic_vector(8 downto 0); + DLM_FOUND_OUT : out std_logic; + -- + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity remover; + +architecture remover_arch of remover is + +-- Components + component fifo_remover + port( + DATA : in std_logic_vector(8 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(8 downto 0); + WCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; FULL : out std_logic; ALMOSTFULL : out std_logic - ); - end component fifo_remover; - --- state machine signals - type state_t is (FILL, IDLE, ONE, TWO, THREE); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal dlm_found_x : std_logic; - signal dlm_found : std_logic; + ); + end component fifo_remover; + +-- state machine signals + type state_t is (FILL, IDLE, ONE, TWO, THREE); + signal STATE, NEXT_STATE : state_t; + +-- Signals + signal dlm_found_x : std_logic; + signal dlm_found : std_logic; signal fifo_wr_x : std_logic; signal fifofull : std_logic; - signal phy_k_fifo : std_logic; - signal phy_d_fifo : std_logic_vector(7 downto 0); + signal fifoempty : std_logic; + signal phy_k_fifo : std_logic; + signal phy_d_fifo : std_logic_vector(7 downto 0); signal fifo_rd_x : std_logic; - signal replace_k_x : std_logic; - signal replace_k : std_logic; - signal replace_d_x : std_logic; - signal replace_d : std_logic; + signal replace_k_x : std_logic; + signal replace_k : std_logic; + signal replace_d_x : std_logic; + signal replace_d : std_logic; signal dlm_data_int : std_logic_vector(7 downto 0); - -begin + +begin + + DEBUG_OUT(0) <= dlm_found; + DEBUG_OUT(1) <= fifo_wr_x; + DEBUG_OUT(2) <= replace_k; + DEBUG_OUT(3) <= replace_d; + DEBUG_OUT(4) <= fifofull; + DEBUG_OUT(5) <= fifoempty; + DEBUG_OUT(15 downto 6) <= (others => '0'); -- DLM komma detected in data stream dlm_found_x <= '1' when ((RX_K_IN = '1') and (RX_D_IN = x"dc")) else '0'; @@ -78,23 +90,24 @@ begin DLM_DATA_OUT <= dlm_data_int; -- write signal for FIFO - fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1'; + fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1'; -- FIFO THE_FIFO: fifo_remover - port map( + port map( DATA(8) => RX_K_IN, DATA(7 downto 0) => RX_D_IN, CLOCK => CLK, - WREN => fifo_wr_x, - RDEN => fifo_rd_x, - RESET => RESET, - Q(8) => phy_k_fifo, + WREN => fifo_wr_x, + RDEN => fifo_rd_x, + RESET => RESET, + Q(8) => phy_k_fifo, Q(7 downto 0) => phy_d_fifo, - WCNT => open, + WCNT => open, + EMPTY => fifoempty, FULL => open, - ALMOSTFULL => fifofull - ); + ALMOSTFULL => fifofull + ); -- read signal for FIFO fifo_rd_x <= '0' when (STATE = FILL) or @@ -106,38 +119,38 @@ begin PHY_K_OUT <= '1' when (replace_k = '1') else '0' when (replace_d = '1') else phy_k_fifo; - - -- data to PHY, multiplexed + + -- data to PHY, multiplexed PHY_D_OUT <= x"bc" when (replace_k = '1') else x"50" when (replace_d = '1') else - phy_d_fifo; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK ) - begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then + phy_d_fifo; + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( RESET = '1' ) then STATE <= FILL; replace_k <= '0'; - replace_d <= '0'; - else - STATE <= NEXT_STATE; - replace_k <= replace_k_x; - replace_d <= replace_d_x; - end if; - end if; - end process THE_FSM; - + replace_d <= '0'; + else + STATE <= NEXT_STATE; + replace_k <= replace_k_x; + replace_d <= replace_d_x; + end if; + end if; + end process THE_FSM; + + ----------------------------------------------------------- + -- staemachine: transitions ----------------------------------------------------------- - -- staemachine: transitions - ----------------------------------------------------------- - THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull ) + THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull ) begin replace_k_x <= '0'; replace_d_x <= '0'; - + case STATE is when FILL => if( (RX_K_IN = '1') and (RX_D_IN = x"bc") and (fifofull = '1') ) then @@ -154,12 +167,12 @@ begin end if; when ONE => - if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then + if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then NEXT_STATE <= TWO; - replace_k_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; + replace_k_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; when TWO => NEXT_STATE <= THREE; @@ -168,14 +181,14 @@ begin when THREE => if( fifofull = '0' ) then NEXT_STATE <= TWO; - replace_k_x <= '1'; + replace_k_x <= '1'; else NEXT_STATE <= IDLE; end if; - - when others => - NEXT_STATE <= IDLE; - end case; - end process THE_STATE_TRANSITIONS; - -end architecture; + + when others => + NEXT_STATE <= IDLE; + end case; + end process THE_STATE_TRANSITIONS; + +end architecture; diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd index 6dd9a9d..7643a50 100644 --- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd @@ -265,6 +265,9 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is signal rx_bsm : std_logic_vector(3 downto 0); + signal remover_dbg : std_logic_vector(15 downto 0); + signal inserter_dbg : std_logic_vector(15 downto 0); + -- -- just a check to see if something goes wrong.... -- attribute HGROUP : string; -- attribute HGROUP of gbe_med_fifo_arch : architecture is "media_interface_group"; @@ -511,7 +514,32 @@ begin D_OUT(1) => rx_serdes_rst_q ); +-- -- RX PATH -- -- "Good" debugging pins +-- debug(7 downto 0) <= sd_rx_data_src; +-- debug(15 downto 8) <= sd_rx_data_dst; +-- debug(16) <= sd_rx_kcntl_src(0); +-- debug(17) <= sd_rx_kcntl_dst(0); +-- debug(18) <= sd_rx_disp_error(0); +-- debug(19) <= sd_rx_cv_error(0); +-- -- "Bad" debugging pins +-- debug(20) <= remover_dbg(0); +-- debug(21) <= remover_dbg(1); +-- debug(22) <= remover_dbg(2); +-- debug(23) <= remover_dbg(3); +-- debug(24) <= remover_dbg(4); +-- debug(25) <= remover_dbg(5); +-- debug(26) <= pcs_rx_en; +-- debug(27) <= pcs_rx_er; +-- debug(28) <= mac_rx_wr; +-- debug(29) <= mac_rx_eof; +-- debug(30) <= mac_rx_err; +-- debug(31) <= '0'; +-- debug(32) <= sd_rx_clk; +-- debug(33) <= CLK_125; + + -- TX PATH + -- "Good" debugging pins debug(7 downto 0) <= sd_tx_data_src; debug(15 downto 8) <= sd_tx_data_dst; debug(16) <= sd_tx_kcntl_src(0); @@ -519,16 +547,16 @@ begin debug(18) <= sd_tx_correct_disp_src(0); debug(19) <= sd_tx_correct_disp_dst(0); -- "Bad" debugging pins - debug(20) <= DLM_INJECT_IN; - debug(21) <= '0'; - debug(22) <= '0'; - debug(23) <= '0'; - debug(24) <= '0'; - debug(25) <= '0'; - debug(26) <= '0'; - debug(27) <= '0'; - debug(28) <= '0'; - debug(29) <= '0'; + debug(20) <= inserter_dbg(0); + debug(21) <= inserter_dbg(1); + debug(22) <= inserter_dbg(2); + debug(23) <= inserter_dbg(3); + debug(24) <= inserter_dbg(4); + debug(25) <= inserter_dbg(5); + debug(26) <= inserter_dbg(6); + debug(27) <= inserter_dbg(7); + debug(28) <= inserter_dbg(8); + debug(29) <= pcs_tx_en; debug(30) <= '0'; debug(31) <= '0'; debug(32) <= sd_rx_clk; @@ -551,7 +579,9 @@ begin TX_CD_OUT => sd_tx_correct_disp_dst(0), -- DLM stuff DLM_DATA_IN => DLM_DATA_IN, - DLM_INJECT_IN => DLM_INJECT_IN + DLM_INJECT_IN => DLM_INJECT_IN, + -- + DEBUG_OUT => inserter_dbg ); THE_EVE: entity remover @@ -566,7 +596,9 @@ begin PHY_K_OUT => sd_rx_kcntl_dst(0), -- DLM stuff DLM_DATA_OUT => DLM_DATA_OUT, - DLM_FOUND_OUT => DLM_FOUND_OUT + DLM_FOUND_OUT => DLM_FOUND_OUT, + -- + DEBUG_OUT => remover_dbg ); ------------------------------------------------------------ ------------------------------------------------------------