From: Michael Boehmer Date: Mon, 18 Jul 2022 09:41:33 +0000 (+0200) Subject: cleanups X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=304306c9d09ebd10c30a3894dee8b2a1c9ba98c9;p=trbnet.git cleanups --- diff --git a/gbe_trb/base/gather_ports.vhd b/gbe_trb/base/gather_ports.vhd index 9ee21b7..478cc9d 100644 --- a/gbe_trb/base/gather_ports.vhd +++ b/gbe_trb/base/gather_ports.vhd @@ -13,6 +13,7 @@ entity gather_ports is FRAME_REQ_OUT : out std_logic_vector(15 downto 0); FRAME_ACK_IN : in std_logic_vector(15 downto 0) := (others => '0'); PORT_SELECT_OUT : out std_logic_vector(15 downto 0); + PORT_MUX_OUT : out std_logic_vector(3 downto 0); CYCLE_DONE_OUT : out std_logic; -- DEBUG : out std_logic_vector(15 downto 0) @@ -36,6 +37,9 @@ architecture gather_ports_arch of gather_ports is signal select_ports : std_logic_vector(15 downto 0); signal req_ports : std_logic_vector(15 downto 0); + signal next_mux_x : std_logic_vector(3 downto 0); + signal mux_ports : std_logic_vector(3 downto 0); + begin -- we need to start a gather cycle if any src port has frames available @@ -65,8 +69,10 @@ begin if( rising_edge(CLK) ) then if( RESET = '1' ) then select_ports <= (others => '0'); + mux_ports <= (others => '0'); else select_ports <= next_port_x; + mux_ports <= next_mux_x; end if; end if; end process THE_SELECT_PORT_PROC; @@ -85,38 +91,55 @@ begin begin if ( stored_ports(0) = '1' ) then next_port_x <= x"0001"; + next_mux_x <= x"0"; elsif( stored_ports(1) = '1' ) then next_port_x <= x"0002"; + next_mux_x <= x"1"; elsif( stored_ports(2) = '1' ) then next_port_x <= x"0004"; + next_mux_x <= x"2"; elsif( stored_ports(3) = '1' ) then next_port_x <= x"0008"; + next_mux_x <= x"3"; elsif( stored_ports(4) = '1' ) then next_port_x <= x"0010"; + next_mux_x <= x"4"; elsif( stored_ports(5) = '1' ) then next_port_x <= x"0020"; + next_mux_x <= x"5"; elsif( stored_ports(6) = '1' ) then next_port_x <= x"0040"; + next_mux_x <= x"6"; elsif( stored_ports(7) = '1' ) then next_port_x <= x"0080"; + next_mux_x <= x"7"; elsif( stored_ports(8) = '1' ) then next_port_x <= x"0100"; + next_mux_x <= x"8"; elsif( stored_ports(9) = '1' ) then next_port_x <= x"0200"; + next_mux_x <= x"9"; elsif( stored_ports(10) = '1' ) then next_port_x <= x"0400"; + next_mux_x <= x"a"; elsif( stored_ports(11) = '1' ) then next_port_x <= x"0800"; + next_mux_x <= x"b"; elsif( stored_ports(12) = '1' ) then next_port_x <= x"1000"; + next_mux_x <= x"c"; elsif( stored_ports(13) = '1' ) then next_port_x <= x"2000"; + next_mux_x <= x"d"; elsif( stored_ports(14) = '1' ) then next_port_x <= x"4000"; + next_mux_x <= x"e"; elsif( stored_ports(15) = '1' ) then next_port_x <= x"8000"; + next_mux_x <= x"f"; else next_port_x <= x"0000"; + next_mux_x <= x"0"; end if; end process THE_NEXT_PORT_PROC; diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd index 13375d8..4e74f0a 100644 --- a/gbe_trb/base/gbe_wrapper_fifo.vhd +++ b/gbe_trb/base/gbe_wrapper_fifo.vhd @@ -79,10 +79,10 @@ entity gbe_wrapper_fifo is -- IP configuration BUS_IP_RX : in CTRLBUS_RX; BUS_IP_TX : out CTRLBUS_TX; - -- Registers config + -- Registers config BUS_REG_RX : in CTRLBUS_RX; BUS_REG_TX : out CTRLBUS_TX; - -- Forwarder + -- Forwarder FWD_DST_MAC_IN : in std_logic_vector(47 downto 0) := (others => '0'); FWD_DST_IP_IN : in std_logic_vector(31 downto 0) := (others => '0'); FWD_DST_UDP_IN : in std_logic_vector(15 downto 0) := (others => '0'); @@ -273,17 +273,16 @@ begin MAC_READY_CONF_IN => LINK_ACTIVE_IN, MAC_RECONF_OUT => open, MAC_AN_READY_IN => PCS_AN_READY_IN, ----- - MAC_RX_DATA_IN => MAC_RX_DATA_IN, --FIFO_DATA_IN(7 downto 0), - MAC_RX_WRITE_IN => MAC_RX_WRITE_IN, --rx_fifo_wr, - MAC_RX_EOF_IN => MAC_RX_EOF_IN, --FIFO_DATA_IN(8), - MAC_RX_ERROR_IN => MAC_RX_ERROR_IN, --'0', ----- + -- MAC RX stuff + MAC_RX_DATA_IN => MAC_RX_DATA_IN, + MAC_RX_WRITE_IN => MAC_RX_WRITE_IN, + MAC_RX_EOF_IN => MAC_RX_EOF_IN, + MAC_RX_ERROR_IN => MAC_RX_ERROR_IN, -- FIFO TX stuff FT_TX_DATA_OUT => ft_tx_data, FT_TX_WR_OUT => ft_tx_wr, FT_TX_FIFOFULL_IN => ft_tx_fifofull, ----- + -- CTS_NUMBER_IN => mlt_cts_number, CTS_CODE_IN => mlt_cts_code, CTS_INFORMATION_IN => mlt_cts_information,