From: Jan Michel Date: Mon, 22 Aug 2016 12:06:43 +0000 (+0200) Subject: Add TDC design for logicbox X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=31a0da8fb0f5619c70dfb30e2b8f7ed680d5e0a0;p=logicbox.git Add TDC design for logicbox --- diff --git a/code/ffarray.vhd b/code/ffarray.vhd deleted file mode 100644 index 52bd3ee..0000000 --- a/code/ffarray.vhd +++ /dev/null @@ -1,109 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; - - -entity ffarray is - port( - CLK : in std_logic; - RESET_IN : in std_logic; - SIGNAL_IN : in std_logic; - - DATA_OUT : out std_logic_vector(8 downto 0); - READ_IN : in std_logic := '0'; - EMPTY_OUT : out std_logic := '0' - ); -end entity; - -architecture ffarray_arch of ffarray is - -attribute syn_hier : string; -attribute syn_hier of ffarray_arch : architecture is "hard"; - -signal CLKt : std_logic_vector(3 downto 0); -signal CLKa : std_logic_vector(7 downto 0); - -signal final1, final2 : std_logic_vector(7 downto 0); -signal final_t : std_logic_vector(7 downto 0); -signal final : std_logic_vector(8 downto 0); -type ffarr_t is array(0 to 3) of std_logic_vector(7 downto 0); -signal ffarr : ffarr_t; - -type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0); -signal ram : ram_t; - -signal fifo_write, last : std_logic; - - - attribute syn_preserve : boolean; - attribute syn_keep : boolean; - - attribute syn_preserve of CLKa : signal is true; - attribute syn_keep of CLKa : signal is true; - attribute syn_preserve of CLKt : signal is true; - attribute syn_keep of CLKt : signal is true; - - -begin - -THE_PLL : entity work.pll_4x266 - port map( - CLKI => CLK, - CLKOP => CLKt(0), - CLKOS => CLKt(1), - CLKOS2 => CLKt(2), - CLKOS3 => CLKt(3) - ); - -CLKa(3 downto 0) <= CLKt(3 downto 0); -CLKa(7 downto 4) <= not CLKt(3 downto 0); - -gen_ffarr_first : for i in 0 to 7 generate - ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i)); - ffarr(1)(i) <= ffarr(0)(i) when rising_edge(CLKa((i/4)*4)); - ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0)); -end generate; - -process begin - wait until falling_edge(CLK); - final_t <= ffarr(2); -end process; - - -process begin - wait until rising_edge(CLK); - final1 <= final_t; - final2 <= ffarr(2); - last <= final2(7); - if (final1(7) xor last) = '1' then - fifo_write <= '1'; - final <= final1 & last; - elsif (final2(7) xor final1(7)) = '1' then - fifo_write <= '1'; - final <= final2 & final1(7); - else - fifo_write <= '0'; - end if; -end process; - - -THE_FIFO : entity work.fifo_9x2k_oreg - port map( - Data => final, - WrClock => CLK, - RdClock => CLK, - WrEn => fifo_write, - RdEn => READ_IN, - Reset => RESET_IN, - RPReset => RESET_IN, - Q => DATA_OUT, - Empty => EMPTY_OUT, - Full => open, - AlmostEmpty => open, - AlmostFull => open - ); - -end architecture; \ No newline at end of file diff --git a/code/uart_sctrl.vhd b/code/uart_sctrl.vhd index 9cb8d05..0b1f71b 100644 --- a/code/uart_sctrl.vhd +++ b/code/uart_sctrl.vhd @@ -4,15 +4,17 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.version.all; - -library machxo2; -use machxo2.all; +-- use work.version.all; +-- +-- library machxo2; +-- use machxo2.all; entity uart_sctrl is generic( - CLOCK_SPEED : integer := 33250000 + CLOCK_SPEED : integer := 33250000; + BAUD : integer := 115200 + ); port( CLK : in std_logic; @@ -34,7 +36,7 @@ end entity; architecture uart_sctrl_arch of uart_sctrl is -constant CLK_DIV : integer := CLOCK_SPEED/115200; +constant CLK_DIV : integer := CLOCK_SPEED/BAUD; signal rx_data : std_logic_vector(7 downto 0); signal tx_data : std_logic_vector(7 downto 0); @@ -45,6 +47,7 @@ signal bytecount : integer range 0 to 15; type rx_state_t is (IDLE,START,START2,DO_COMMAND,DO_READ,SEND_BYTE1,SEND_BYTE2,SEND_BYTE3,SEND_TERM,SEND_FINISH); signal state : rx_state_t; signal addr_data : std_logic_vector(39 downto 0); +signal addr_data_tx : std_logic_vector(31 downto 0); signal timer : unsigned(25 downto 0) := (others => '0'); signal timeout : std_logic := '0'; @@ -120,8 +123,6 @@ begin when DO_COMMAND => WRITE_OUT <= cmd_wr; READ_OUT <= cmd_rd; - DATA_OUT <= addr_data(31 downto 0); - ADDR_OUT <= addr_data(39 downto 32); if cmd_rd = '1' then state <= DO_READ; else @@ -131,7 +132,7 @@ begin --Read cycle when DO_READ => if READY_IN = '1' then - addr_data(31 downto 0) <= DATA_IN; + addr_data_tx(31 downto 0) <= DATA_IN; tx_send <= '1'; tx_data <= x"52"; state <= SEND_BYTE1; @@ -139,11 +140,11 @@ begin end if; when SEND_BYTE1 => - tmp := x"0" & unsigned(addr_data(bytecount*4+3 downto bytecount*4)); + tmp := x"0" & unsigned(addr_data_tx(bytecount*4+3 downto bytecount*4)); state <= SEND_BYTE2; when SEND_BYTE2 => - if tmp > x"09" then + if tmp(3 downto 0) > x"9" then tmp := tmp + x"41" - x"0a"; else tmp := tmp + x"30"; @@ -187,8 +188,10 @@ begin end if; end process; - -timeout <= timer(25); +DATA_OUT <= addr_data(31 downto 0); +ADDR_OUT <= addr_data(39 downto 32); + +timeout <= timer(19); diff --git a/cores/pll_4x266.ipx b/cores/pll_4x266.ipx deleted file mode 100644 index 1e203ff..0000000 --- a/cores/pll_4x266.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/cores/pll_4x266.lpc b/cores/pll_4x266.lpc deleted file mode 100644 index 3d397ba..0000000 --- a/cores/pll_4x266.lpc +++ /dev/null @@ -1,87 +0,0 @@ -[Device] -Family=machxo3lf -PartType=LCMXO3LF-2100E -PartName=LCMXO3LF-2100E-5UWG49CTR -SpeedGrade=5 -Package=WLCSP49 -OperatingCondition=COM -Status=S - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PLL -CoreRevision=5.8 -ModuleName=pll_4x266 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/05/2016 -Time=17:14:32 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=None -Order=None -IO=0 -mode=Frequency -CLKI=125 -CLKI_DIV=1 -BW=10.504 -VCO=500.000 -fb_mode=INT_OP -CLKFB_DIV=2 -FRACN_ENABLE=0 -FRACN_DIV=0 -DynamicPhase=STATIC -ClkEnable=0 -Standby=0 -Enable_sel=0 -PLLRst=0 -PLLMRst=0 -ClkOS2Rst=0 -ClkOS3Rst=0 -LockSig=0 -LockStk=0 -WBProt=0 -OPBypass=0 -OPUseDiv=0 -CLKOP_DIV=2 -FREQ_PIN_CLKOP=250 -OP_Tol=1.0 -CLKOP_AFREQ=250.000000 -CLKOP_PHASEADJ=0 -CLKOP_TRIM_POL=Rising -CLKOP_TRIM_DELAY=0 -EnCLKOS=1 -OSBypass=0 -OSUseDiv=0 -CLKOS_DIV=2 -FREQ_PIN_CLKOS=250 -OS_Tol=0.0 -CLKOS_AFREQ=250.000000 -CLKOS_PHASEADJ=45 -CLKOS_TRIM_POL=Rising -CLKOS_TRIM_DELAY=0 -EnCLKOS2=1 -OS2Bypass=0 -OS2UseDiv=0 -CLKOS2_DIV=2 -FREQ_PIN_CLKOS2=250 -OS2_Tol=0.0 -CLKOS2_AFREQ=250.000000 -CLKOS2_PHASEADJ=90 -EnCLKOS3=1 -OS3Bypass=0 -OS3UseDiv=0 -CLKOS3_DIV=2 -FREQ_PIN_CLKOS3=250 -OS3_Tol=0.0 -CLKOS3_AFREQ=250.000000 -CLKOS3_PHASEADJ=135 - -[Command] -cmd_line= -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 diff --git a/cores/pll_4x266.vhd b/cores/pll_4x266.vhd deleted file mode 100644 index 7ff3200..0000000 --- a/cores/pll_4x266.vhd +++ /dev/null @@ -1,170 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 --- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 - --- Tue Apr 5 17:14:32 2016 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library MACHXO3L; -use MACHXO3L.components.all; --- synopsys translate_on - -entity pll_4x266 is - port ( - CLKI: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - CLKOS2: out std_logic; - CLKOS3: out std_logic); -end pll_4x266; - -architecture Structure of pll_4x266 is - - -- internal signal declarations - signal LOCK: std_logic; - signal CLKOS3_t: std_logic; - signal CLKOS2_t: std_logic; - signal CLKOS_t: std_logic; - signal CLKOP_t: std_logic; - signal CLKFB_t: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VLO - port (Z: out std_logic); - end component; - component EHXPLLJ - generic (INTFB_WAKE : in String; DDRST_ENA : in String; - DCRST_ENA : in String; MRST_ENA : in String; - PLLRST_ENA : in String; DPHASE_SOURCE : in String; - STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String; - OUTDIVIDER_MUXC2 : in String; - OUTDIVIDER_MUXB2 : in String; - OUTDIVIDER_MUXA2 : in String; - PREDIVIDER_MUXD1 : in Integer; - PREDIVIDER_MUXC1 : in Integer; - PREDIVIDER_MUXB1 : in Integer; - PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String; - PLL_LOCK_MODE : in Integer; - CLKOS_TRIM_DELAY : in Integer; - CLKOS_TRIM_POL : in String; - CLKOP_TRIM_DELAY : in Integer; - CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer; - FRACN_ENABLE : in String; FEEDBK_PATH : in String; - CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer; - CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer; - CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer; - CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer; - VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String; - VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String; - CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String; - CLKOS_ENABLE : in String; CLKOP_ENABLE : in String; - CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer; - CLKOS_DIV : in Integer; CLKOP_DIV : in Integer; - CLKFB_DIV : in Integer; CLKI_DIV : in Integer); - port (CLKI: in std_logic; CLKFB: in std_logic; - PHASESEL1: in std_logic; PHASESEL0: in std_logic; - PHASEDIR: in std_logic; PHASESTEP: in std_logic; - LOADREG: in std_logic; STDBY: in std_logic; - PLLWAKESYNC: in std_logic; RST: in std_logic; - RESETM: in std_logic; RESETC: in std_logic; - RESETD: in std_logic; ENCLKOP: in std_logic; - ENCLKOS: in std_logic; ENCLKOS2: in std_logic; - ENCLKOS3: in std_logic; PLLCLK: in std_logic; - PLLRST: in std_logic; PLLSTB: in std_logic; - PLLWE: in std_logic; PLLADDR4: in std_logic; - PLLADDR3: in std_logic; PLLADDR2: in std_logic; - PLLADDR1: in std_logic; PLLADDR0: in std_logic; - PLLDATI7: in std_logic; PLLDATI6: in std_logic; - PLLDATI5: in std_logic; PLLDATI4: in std_logic; - PLLDATI3: in std_logic; PLLDATI2: in std_logic; - PLLDATI1: in std_logic; PLLDATI0: in std_logic; - CLKOP: out std_logic; CLKOS: out std_logic; - CLKOS2: out std_logic; CLKOS3: out std_logic; - LOCK: out std_logic; INTLOCK: out std_logic; - REFCLK: out std_logic; CLKINTFB: out std_logic; - DPHSRC: out std_logic; PLLACK: out std_logic; - PLLDATO7: out std_logic; PLLDATO6: out std_logic; - PLLDATO5: out std_logic; PLLDATO4: out std_logic; - PLLDATO3: out std_logic; PLLDATO2: out std_logic; - PLLDATO1: out std_logic; PLLDATO0: out std_logic); - end component; - attribute FREQUENCY_PIN_CLKOS3 : string; - attribute FREQUENCY_PIN_CLKOS2 : string; - attribute FREQUENCY_PIN_CLKOS : string; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute ICP_CURRENT : string; - attribute LPF_RESISTOR : string; - attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "250.000000"; - attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "250.000000"; - attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "250.000000"; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; - attribute ICP_CURRENT of PLLInst_0 : label is "10"; - attribute LPF_RESISTOR of PLLInst_0 : label is "24"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - PLLInst_0: EHXPLLJ - generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED", - MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", - STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", - PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 6, CLKOS3_CPHASE=> 1, - CLKOS2_FPHASE=> 4, CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 2, - CLKOS_CPHASE=> 1, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1, - PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", - CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0, - FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD", - PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED", - OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED", - CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB", - PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED", - OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED", - CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2, CLKOS2_DIV=> 2, - CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1, - FEEDBK_PATH=> "INT_DIVA") - port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, - PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, - PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo, - PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo, - RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo, - ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, - PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo, - PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo, - PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo, - PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo, - PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo, - PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo, - PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo, - PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, - CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK, - INTLOCK=>open, REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open, - PLLACK=>open, PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open, - PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open, - PLLDATO1=>open, PLLDATO0=>open); - - CLKOS3 <= CLKOS3_t; - CLKOS2 <= CLKOS2_t; - CLKOS <= CLKOS_t; - CLKOP <= CLKOP_t; -end Structure; - --- synopsys translate_off -library MACHXO3L; -configuration Structure_CON of pll_4x266 is - for Structure - for all:VLO use entity MACHXO3L.VLO(V); end for; - for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/pinout/tdc.lpf b/pinout/tdc.lpf new file mode 100644 index 0000000..1b09991 --- /dev/null +++ b/pinout/tdc.lpf @@ -0,0 +1,50 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +SYSCONFIG MCCLK_FREQ=133 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE ; +LOCATE COMP "INPUT[6]" SITE "A6" ; +LOCATE COMP "INPUT[7]" SITE "C5" ; +LOCATE COMP "INPUT[4]" SITE "B4" ; +LOCATE COMP "INPUT[5]" SITE "B5" ; +LOCATE COMP "CONTROLI" SITE "B1" ; +LOCATE COMP "CONTROLO" SITE "A1" ; +LOCATE COMP "LED[0]" SITE "A7" ; +LOCATE COMP "LED[1]" SITE "E5" ; +LOCATE COMP "LED[2]" SITE "C1" ; +LOCATE COMP "LED[3]" SITE "B2" ; +LOCATE COMP "INPUT[0]" SITE "F7" ; +LOCATE COMP "INPUT[2]" SITE "G7" ; +LOCATE COMP "INPUT[3]" SITE "F4" ; +LOCATE COMP "INPUT[1]" SITE "F3" ; +LOCATE COMP "RX_OUT" SITE "F1" ; +LOCATE COMP "TX_IN" SITE "C4" ; +LOCATE COMP "CBUS" SITE "C3" ; +LOCATE COMP "CLK" SITE "G4" ; +LOCATE COMP "STATUSO" SITE "G2" ; +LOCATE COMP "STATUSI" SITE "G1" ; +IOBUF PORT "INPUT[0]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[1]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[2]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[3]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[4]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[5]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[6]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "INPUT[7]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF PULLMODE=DOWN ; +IOBUF PORT "CONTROLI" IO_TYPE=LVTTL33 ; +IOBUF PORT "CONTROLO" IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=8 ; +IOBUF PORT "LED[0]" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "LED[1]" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "LED[2]" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "LED[3]" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "RX_OUT" IO_TYPE=LVTTL33 ; +IOBUF PORT "TX_IN" IO_TYPE=LVTTL33 ; +IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ; +IOBUF PORT "CLK" IO_TYPE=LVDS25 ; +IOBUF PORT "STATUSO" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +BANK 0 VCCIO 3.3 V; +BANK 5 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; + + +FREQUENCY PORT CLK 125 MHz; +FREQUENCY NET clk_osc 133 MHz; \ No newline at end of file diff --git a/tdc/compile.pl b/tdc/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/tdc/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/tdc/config_compile_frankfurt.pl b/tdc/config_compile_frankfurt.pl new file mode 100644 index 0000000..e848798 --- /dev/null +++ b/tdc/config_compile_frankfurt.pl @@ -0,0 +1,27 @@ +Familyname => 'MachXO3LF', +Devicename => 'LCMXO3LF-2100E', +Package => 'WLCSP49', +Speedgrade => '5', + +TOPNAME => "tdc", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +# synplify_path => '/d/jspc29/lattice/synplify/L-2016.03/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +make_jed => 1, diff --git a/tdc/par.p2t b/tdc/par.p2t new file mode 100644 index 0000000..9386a1c --- /dev/null +++ b/tdc/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 3 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/tdc/readdata2.pl b/tdc/readdata2.pl new file mode 120000 index 0000000..f2a3bf6 --- /dev/null +++ b/tdc/readdata2.pl @@ -0,0 +1 @@ +../../mdcfee/mboasd8/readdata2.pl \ No newline at end of file diff --git a/tdc/tdc.lpf b/tdc/tdc.lpf new file mode 100644 index 0000000..2068fba --- /dev/null +++ b/tdc/tdc.lpf @@ -0,0 +1,322 @@ +UGROUP "ffarr0groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][7] + ; + +UGROUP "ffarr0groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][7] + ; + +UGROUP "ffarr1groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][7] + ; + +UGROUP "ffarr1groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][7] + ; + +UGROUP "ffarr2groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][7] + ; + +UGROUP "ffarr2groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][7] + ; + +UGROUP "ffarr3groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][7] + ; + +UGROUP "ffarr3groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][7] + ; + +UGROUP "ffarr4groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][7] + ; + +UGROUP "ffarr4groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][7] + ; + +UGROUP "ffarr5groupA" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][7] + ; + +UGROUP "ffarr5groupB" BBOX 1 2 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][7] + ; + +UGROUP "ffarr6groupA" BBOX 1 3 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][7] + ; + +UGROUP "ffarr6groupB" BBOX 1 3 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][7] + ; + +UGROUP "ffarr7groupA" BBOX 1 3 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][7] + ; + +UGROUP "ffarr7groupB" BBOX 1 3 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][0] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][7] + ; + + +REGION "FFARR0A" "R12C3" 1 2 DEVSIZE; +REGION "FFARR0B" "R13C3" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr0groupA" REGION "FFARR0A"; +LOCATE UGROUP "ffarr0groupB" REGION "FFARR0B"; + +REGION "FFARR1A" "R12C13" 1 2 DEVSIZE; +REGION "FFARR1B" "R13C13" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr1groupA" REGION "FFARR1A"; +LOCATE UGROUP "ffarr1groupB" REGION "FFARR1B"; + +REGION "FFARR2A" "R12C5" 1 2 DEVSIZE; +REGION "FFARR2B" "R13C5" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr2groupA" REGION "FFARR2A"; +LOCATE UGROUP "ffarr2groupB" REGION "FFARR2B"; + +REGION "FFARR3A" "R12C11" 1 2 DEVSIZE; +REGION "FFARR3B" "R13C11" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr3groupA" REGION "FFARR3A"; +LOCATE UGROUP "ffarr3groupB" REGION "FFARR3B"; + +REGION "FFARR4A" "R2C18" 1 2 DEVSIZE; +REGION "FFARR4B" "R3C18" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr4groupA" REGION "FFARR4A"; +LOCATE UGROUP "ffarr4groupB" REGION "FFARR4B"; + +REGION "FFARR5A" "R2C20" 1 2 DEVSIZE; +REGION "FFARR5B" "R3C20" 1 2 DEVSIZE; +LOCATE UGROUP "ffarr5groupA" REGION "FFARR5A"; +LOCATE UGROUP "ffarr5groupB" REGION "FFARR5B"; + +REGION "FFARR6A" "R2C12" 1 3 DEVSIZE; +REGION "FFARR6B" "R3C12" 1 3 DEVSIZE; +LOCATE UGROUP "ffarr6groupA" REGION "FFARR6A"; +LOCATE UGROUP "ffarr6groupB" REGION "FFARR6B"; + +REGION "FFARR7A" "R2C15" 1 3 DEVSIZE; +REGION "FFARR7B" "R3C15" 1 3 DEVSIZE; +LOCATE UGROUP "ffarr7groupA" REGION "FFARR7A"; +LOCATE UGROUP "ffarr7groupB" REGION "FFARR7B"; + + +BLOCK PATH FROM CELL "PROC_REGS.input_disable[*]"; + +USE PRIMARY NET "THE_TDC/CLKa*"; +USE PRIMARY NET "THE_TDC_CLKa*"; +USE PRIMARY NET "THE_TDC/CLKa[0]"; +USE PRIMARY NET "THE_TDC/CLKa[1]"; +USE PRIMARY NET "THE_TDC/CLKa[2]"; +USE PRIMARY NET "THE_TDC/CLKa[3]"; +USE PRIMARY NET "THE_TDC_CLKa[0]"; +USE PRIMARY NET "THE_TDC_CLKa[1]"; +USE PRIMARY NET "THE_TDC_CLKa[2]"; +USE PRIMARY NET "THE_TDC_CLKa[3]"; + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tdc/tdc.prj b/tdc/tdc.prj new file mode 100644 index 0000000..b888e74 --- /dev/null +++ b/tdc/tdc.prj @@ -0,0 +1,77 @@ +#project files + +#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.7_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" + +add_file -vhdl -lib work "../../mdcfee/cores/fifo_36x1k.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" +add_file -vhdl -lib work "../../mdcfee/cores/pll_4x266.vhd" +add_file -vhdl -lib work "../../mdcfee/code/ffarray.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../mdcfee/code/uart_sctrl.vhd" +add_file -vhdl -lib work "tdc.vhd" + + + +#implementation: "LogicBox" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par + +#device options +set_option -technology MACHXO3LF +set_option -part LCMXO3LF_2100E +set_option -package UWG49CTR +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "tdc" + +# mapper_options +set_option -frequency 100 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 1000 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 1 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 +set_option -multi_file_compilation_unit 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/tdc.edf" + +#set log file +set_option log_file "workdir/tdc.srf" +impl -active "workdir" diff --git a/tdc/tdc.vhd b/tdc/tdc.vhd new file mode 100644 index 0000000..8d6d022 --- /dev/null +++ b/tdc/tdc.vhd @@ -0,0 +1,292 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- library machxo3lf; +-- use machxo3lf.all; + +library work; +use work.trb_net_std.all; + +entity tdc is + port( + CLK : in std_logic; + + INPUT : in std_logic_vector(7 downto 0); + + LED : inout std_logic_vector(3 downto 0); + RX_OUT : out std_logic; + TX_IN : in std_logic; + CBUS : in std_logic + + ); +end entity; + +architecture arch of tdc is + +-- component OSCH +-- generic (NOM_FREQ: string := "133.00"); +-- port ( +-- STDBY :IN std_logic; +-- OSC :OUT std_logic; +-- SEDSTDBY :OUT std_logic +-- ); +-- end component; + + signal clk_i : std_logic; + + signal uart_rx_data : std_logic_vector(31 downto 0); + signal uart_tx_data : std_logic_vector(31 downto 0); + signal uart_addr : std_logic_vector(7 downto 0); + signal bus_read : std_logic := '0'; + signal bus_write : std_logic := '0'; + signal bus_ready : std_logic; + signal uart_busy : std_logic; + + signal sed_error : std_logic; + signal sed_debug : std_logic_vector(31 downto 0); + signal controlsed_i : std_logic_vector(3 downto 0); + + signal f_read, f_empty : std_logic; + signal last_f_read, last2_f_read : std_logic; + signal f_data : std_logic_vector(31 downto 0); + +-- signal reg : std_logic_vector(31 downto 0); + signal config : std_logic_vector(3 downto 0); + signal config_reg : std_logic_vector(3 downto 0); + + signal input_hold : std_logic_vector(7 downto 0); + signal input_reg_0, input_reg_1, input_reg_2, input_i : std_logic_vector(7 downto 0); + +-- signal edge_rising, edge_falling : std_logic_vector(3 downto 0); +-- signal pulser : std_logic; + signal last_config : std_logic_vector(3 downto 0); + signal led_i : std_logic_vector(3 downto 0); + signal timer_i : unsigned(31 downto 0) := (others => '0'); + signal led_highz : std_logic; + + type led_timer_t is array(0 to 3) of unsigned(7 downto 0); + signal led_timer : led_timer_t; + signal led_state : std_logic_vector(3 downto 0); + signal led_clk_en : std_logic; + + type counter_arr is array(0 to 7) of unsigned(15 downto 0); + signal input_counter : counter_arr; + signal select_i : std_logic_vector(3 downto 0); + signal readcounter : unsigned(15 downto 0); + signal uart_debug : std_logic_vector(15 downto 0); + signal input_disable : std_logic_vector(7 downto 0); + +begin + +clk_i <= CLK; + +timer_i <= timer_i + 1 when rising_edge(clk_i); + +--------------------------------------------------------------------------- +-- UART +--------------------------------------------------------------------------- +THE_UART : entity work.uart_sctrl + generic map( + CLOCK_SPEED => 125000000, + BAUD => 921076 + ) + port map( + CLK => clk_i, + RESET => sed_error, + UART_RX => TX_IN, + UART_TX => RX_OUT, + + DATA_OUT => uart_rx_data, + DATA_IN => uart_tx_data, + ADDR_OUT => uart_addr, + WRITE_OUT => bus_write, + READ_OUT => bus_read, + READY_IN => bus_ready, + BUSY_OUT => uart_busy, + + DEBUG => uart_debug + ); + + +PROC_REGS : process begin + wait until rising_edge(clk_i); + bus_ready <= '0'; + f_read <= '0'; + last2_f_read <= last_f_read; last_f_read <= f_read; +-- pwm_write_i <= '0'; + if bus_read = '1' then + bus_ready <= '1'; + case uart_addr is + when x"00" => uart_tx_data <= x"000000" & config & config_reg; + when x"01" => uart_tx_data <= x"00000" & "00" & CBUS & '0' & input_reg_2; + when x"11" => + uart_tx_data <= x"000000" & input_disable; + when x"d0" => + f_read <= '1'; + bus_ready <= '0'; + when x"ee" => uart_tx_data <= sed_debug; +-- when x"ff" => uart_tx_data(15 downto 0) <= std_logic_vector(readcounter); +-- readcounter <= readcounter + 1; + end case; + if uart_addr(7 downto 4) = x"2" then + uart_tx_data(31 downto 16) <= uart_addr(3 downto 0) & x"000"; + uart_tx_data(15 downto 0) <= std_logic_vector(input_counter(to_integer(unsigned(uart_addr(3 downto 0))))); + end if; + elsif bus_write = '1' then + case uart_addr is + when x"00" => + config_reg <= uart_rx_data(3 downto 0); + when x"11" => + input_disable <= uart_rx_data(7 downto 0); +-- when x"80" => +-- pwm_write_i <= '1'; +-- pwm_data_i <= uart_rx_data(15 downto 0); +-- pwm_addr_i <= uart_rx_data(28 downto 24); +-- when x"90" => +-- temperature_i <= uart_rx_data(11 downto 0); +-- when x"91" => +-- comp_setting <= uart_rx_data(15 downto 0); + when x"ee" => + controlsed_i <= uart_rx_data(3 downto 0); + end case; + end if; + if last2_f_read = '1' then + uart_tx_data <= f_data; + bus_ready <= '1'; + end if; + + if config_reg(0) = '1' then + if f_empty = '0' and uart_busy = '0' and last2_f_read = '0' and last_f_read = '0' and f_read = '0' and bus_ready = '0' then + f_read <= '1'; + end if; + end if; + + +end process; + +--------------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------------- +-- clk_source: OSCH +-- generic map ( NOM_FREQ => "2.08" ) +-- port map ( +-- STDBY => '0', +-- OSC => clk_osc, +-- SEDSTDBY => open +-- ); + + + +--------------------------------------------------------------------------- +-- Input Reg +--------------------------------------------------------------------------- +input_reg_0 <= INPUT when rising_edge(clk_i); --or input_hold +input_reg_1 <= input_reg_0 when rising_edge(clk_i); +input_reg_2 <= input_reg_1 when rising_edge(clk_i); + +input_hold <= INPUT or (input_hold and not input_reg_0); + +input_i <= INPUT and not input_disable; + +--------------------------------------------------------------------------- +-- Input Counter +--------------------------------------------------------------------------- +gen_input_counter : for i in 0 to 7 generate + proc_cnt : process begin + wait until rising_edge(clk_i); + if (input_reg_2(i) = '1') and (input_reg_1(i) = '0') then + input_counter(i) <= input_counter(i) + 1; + end if; + end process; +end generate; + + +--------------------------------------------------------------------------- +-- TDC +--------------------------------------------------------------------------- +THE_TDC : entity work.ffarray + generic map( + CHANNELS => 8 + ) + port map( + CLK => clk_i, + RESET_IN => '0', + SIGNAL_IN(7 downto 0) => input_i(7 downto 0), + DATA_OUT => f_data, + READ_IN => f_read, + EMPTY_OUT => f_empty + ); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + PROC_LED : process begin + wait until rising_edge(clk_i); + if not (config = last_config) and timer_i(27) = '0' then + led_i <= config; + else + led_i <= led_state; + end if; + end process; + + PROC_LED_STATE : process begin + wait until rising_edge(clk_i); + if timer_i(15 downto 0) = 0 then + led_clk_en <= '1'; + else + led_clk_en <= '0'; + end if; + + for i in 0 to 3 loop + if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(7 downto 5) > 0) then + led_state(i) <= not led_state(i); + led_timer(i) <= 0; + elsif led_timer(i)(7) = '1' then + led_state(i) <= input_reg_1(i); + elsif led_clk_en = '1' then + led_timer(i) <= led_timer(i) + 1; + end if; + end loop; + end process; + +--------------------------------------------------------------------------- +-- Read configuration switch +--------------------------------------------------------------------------- +process begin + wait until rising_edge(clk_i); + + + if timer_i(27 downto 10) = 0 then + led_highz <= '1'; + last_config <= config; + if timer_i(9 downto 0) = "11"&x"ff" then + config <= not LED; + end if; + else + led_highz <= '0'; + end if; +end process; + +LED <= led_i when led_highz = '0' else + "ZZZZ"; + + + +-- +-- THE_SED : entity work.sedcheck +-- port map( +-- CLK => clk_i, +-- ERROR_OUT => sed_error, +-- +-- CONTROL_IN => controlsed_i, +-- DEBUG => sed_debug +-- ); + + + +end architecture; + + + \ No newline at end of file