From: Cahit Date: Mon, 1 Dec 2014 14:29:14 +0000 (+0100) Subject: top files and component files for the tdc version 2.0 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=31efd8607954b0c990d8eb2fd11260841e0f334c;p=trb3.git top files and component files for the tdc version 2.0 --- diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd deleted file mode 120000 index 5200d30..0000000 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ /dev/null @@ -1 +0,0 @@ -trb3_periph_32PinAddOn.vhd.1.6.xx \ No newline at end of file diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd new file mode 100644 index 0000000..5373ced --- /dev/null +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -0,0 +1,970 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.tdc_components.all; +use work.config.all; +use work.tdc_version.all; +use work.version.all; + + +entity trb3_periph_32PinAddOn is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Connection to ADA AddOn + SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only + INP : in std_logic_vector(63 downto 0); + --DAC + DAC_IN_SDI : in std_logic; + DAC_OUT_SDO : out std_logic; + DAC_OUT_SCK : out std_logic; + DAC_OUT_CS : out std_logic; + DAC_OUT_CLR : out std_logic; + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of DAC_IN_SDI : signal is true; + attribute syn_useioff of DAC_OUT_SDO : signal is true; + attribute syn_useioff of DAC_OUT_SCK : signal is true; + attribute syn_useioff of DAC_OUT_CS : signal is true; + attribute syn_useioff of DAC_OUT_CLR : signal is true; + + +end entity; + + +architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 0; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spidac_read_en : std_logic; + signal spidac_write_en : std_logic; + signal spidac_data_in : std_logic_vector(31 downto 0); + signal spidac_addr : std_logic_vector(4 downto 0); + signal spidac_data_out : std_logic_vector(31 downto 0); + signal spidac_ack : std_logic; + signal spidac_busy : std_logic; + + signal dac_cs_i : std_logic_vector(3 downto 0); + signal dac_sck_i : std_logic; + signal dac_sdi_i : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal cdb_read_en : std_logic; + signal cdb_write_en : std_logic; + signal cdb_addr : std_logic_vector(6 downto 0); + signal cdb_data_out : std_logic_vector(31 downto 0); + signal cdb_data_ready : std_logic; + signal cdb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal trig_out : std_logic_vector(3 downto 0); + signal trig_din : std_logic_vector(31 downto 0); + signal trig_dout : std_logic_vector(31 downto 0); + signal trig_write : std_logic := '0'; + signal trig_read : std_logic := '0'; + signal trig_ack : std_logic := '0'; + signal trig_nack : std_logic := '0'; + signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal stat_out : std_logic_vector(3 downto 0); + signal stat_din : std_logic_vector(31 downto 0); + signal stat_dout : std_logic_vector(31 downto 0); + signal stat_write : std_logic := '0'; + signal stat_read : std_logic := '0'; + signal stat_ack : std_logic := '0'; + signal stat_nack : std_logic := '0'; + signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal sed_error : std_logic; + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + -- internal oscillator with frequency of 2.5MHz for tdc calibration + OSCInst0 : OSCF + port map ( + OSC => osc_int); + + + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, + REGIO_INIT_ADDRESS => INIT_ADDRESS, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 12, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**12-400, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + timing_trg_received_i <= TRIGGER_LEFT; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 10, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", + 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", 9 => x"c200", --c300 c400 + others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, + 5 => 3, 6 => 6, 7 => 7, 8 => 4, 9 => 7, + others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --Bus Handler (SPI DAC) + BUS_READ_ENABLE_OUT(2) => spidac_read_en, + BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, + BUS_DATAREADY_IN(2) => spidac_ack, + BUS_WRITE_ACK_IN(2) => spidac_ack, + BUS_NO_MORE_DATA_IN(2) => spidac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write, + BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(5) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(5) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(6) => trig_read, + BUS_WRITE_ENABLE_OUT(6) => trig_write, + BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din, + BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout, + BUS_DATAREADY_IN(6) => trig_ack, + BUS_WRITE_ACK_IN(6) => trig_ack, + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => trig_nack, + --Input statistics + BUS_READ_ENABLE_OUT(7) => stat_read, + BUS_WRITE_ENABLE_OUT(7) => stat_write, + BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din, + BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout, + BUS_DATAREADY_IN(7) => stat_ack, + BUS_WRITE_ACK_IN(7) => stat_ack, + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => stat_nack, + --SEU Detection + BUS_READ_ENABLE_OUT(8) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(8) => bussed_rx.write, + BUS_DATA_OUT(8*32+31 downto 8*32) => bussed_rx.data, + BUS_ADDR_OUT(8*16+15 downto 8*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(8) => bussed_rx.timeout, + BUS_DATA_IN(8*32+31 downto 8*32) => bussed_tx.data, + BUS_DATAREADY_IN(8) => bussed_tx.ack, + BUS_WRITE_ACK_IN(8) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(8) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(8) => bussed_tx.unknown, + --Channel Debug Registers + BUS_READ_ENABLE_OUT(9) => cdb_read_en, + BUS_WRITE_ENABLE_OUT(9) => cdb_write_en, + BUS_DATA_OUT(9*32+31 downto 9*32) => open, + BUS_ADDR_OUT(9*16+6 downto 9*16) => cdb_addr, + BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => cdb_data_out, + BUS_DATAREADY_IN(9) => cdb_data_ready, + BUS_WRITE_ACK_IN(9) => '0', + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => cdb_invalid, + + ----Encoder Start Registers + --BUS_READ_ENABLE_OUT(5) => esb_read_en, + --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + --BUS_DATA_OUT(5*32+31 downto 5*32) => open, + --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + --BUS_TIMEOUT_OUT(5) => open, + --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + --BUS_DATAREADY_IN(5) => esb_data_ready, + --BUS_WRITE_ACK_IN(5) => '0', + --BUS_NO_MORE_DATA_IN(5) => '0', + --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + ----Fifo Write Registers + --BUS_READ_ENABLE_OUT(6) => efb_read_en, + --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + --BUS_DATA_OUT(6*32+31 downto 6*32) => open, + --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + --BUS_TIMEOUT_OUT(6) => open, + --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + --BUS_DATAREADY_IN(6) => efb_data_ready, + --BUS_WRITE_ACK_IN(6) => '0', + --BUS_NO_MORE_DATA_IN(6) => '0', + --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + ----Lost Hit Registers + --BUS_READ_ENABLE_OUT(7) => lhb_read_en, + --BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + --BUS_DATA_OUT(7*32+31 downto 7*32) => open, + --BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + --BUS_TIMEOUT_OUT(7) => open, + --BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + --BUS_DATAREADY_IN(7) => lhb_data_ready, + --BUS_WRITE_ACK_IN(7) => '0', + --BUS_NO_MORE_DATA_IN(7) => '0', + --BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------- +-- SPI +------------------------------------------------------------------------------- + gen_SPI : if INCLUDE_SPI = 1 generate + DAC_SPI : spi_ltc2600 + generic map ( + BITS => 14, + WAITCYCLES => 100) + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_BUSY_OUT => spidac_busy, + BUS_ACK_OUT => spidac_ack, + BUS_ADDR_IN => spidac_addr, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(0) => DAC_OUT_CS, + SPI_SDI_IN => DAC_IN_SDI, + SPI_SDO_OUT => DAC_OUT_SDO, + SPI_SCK_OUT => DAC_OUT_SCK, + SPI_CLR_OUT(0) => DAC_OUT_CLR + ); + end generate; + + + gen_NO_SPI : if INCLUDE_SPI = 0 generate + DAC_OUT_SDO <= trig_out(0); + DAC_OUT_SCK <= trig_out(1); + DAC_OUT_CS <= trig_out(2); + DAC_OUT_CLR <= trig_out(3); + end generate; + + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- + gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => PHYSICAL_INPUTS, + OUTPUTS => 4 + ) + port map( + CLK => clk_100_i, + + INPUT => INP(PHYSICAL_INPUTS-1 downto 0), + OUTPUT => trig_out, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); + FPGA5_COMM(10 downto 7) <= trig_out; + end generate; + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- + gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => PHYSICAL_INPUTS, + SINGLE_FIFO_ONLY => USE_SINGLE_FIFO + ) + port map( + CLK => clk_100_i, + + INPUT => INP(PHYSICAL_INPUTS-1 downto 0), + + DATA_IN => stat_din, + DATA_OUT => stat_dout, + WRITE_IN => stat_write, + READ_IN => stat_read, + ACK_OUT => stat_ack, + NACK_OUT => stat_nack, + ADDR_IN => stat_addr + ); + end generate; + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= '1'; + LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= logic_analyser_i; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels + STATUS_REG_NR => 21, -- Number of status regs + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => TDC_VERSION, -- TDC version number + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Channel Debug Bus + CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe + CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe + CDB_ADDR_IN => cdb_addr, -- bus address + CDB_DATA_OUT => cdb_data_out, -- bus data + CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe + CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => lhb_addr, -- bus address + LHB_DATA_OUT => lhb_data_out, -- bus data + LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INP; + end generate; + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; + end generate; + + +end architecture; diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.6.xx b/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.6.xx deleted file mode 100644 index f2e1491..0000000 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.6.xx +++ /dev/null @@ -1,988 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.config.all; -use work.tdc_version.all; -use work.version.all; - - -entity trb3_periph_32PinAddOn is - port( - --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out - TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - --Serdes - CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - SERDES_INT_TX : out std_logic_vector(3 downto 0); - SERDES_INT_RX : in std_logic_vector(3 downto 0); - SERDES_ADDON_TX : out std_logic_vector(11 downto 0); - SERDES_ADDON_RX : in std_logic_vector(11 downto 0); - --Inter-FPGA Communication - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - --Connection to ADA AddOn - SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only - INP : in std_logic_vector(63 downto 0); - --DAC - DAC_IN_SDI : in std_logic; - DAC_OUT_SDO : out std_logic; - DAC_OUT_SCK : out std_logic; - DAC_OUT_CS : out std_logic; - DAC_OUT_CLR : out std_logic; - - --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - SUPPL : in std_logic; --terminated diff pair, PCLK, Pads - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of CODE_LINE : signal is false; - attribute syn_useioff of TRIGGER_LEFT : signal is false; - attribute syn_useioff of TRIGGER_RIGHT : signal is false; - --important signals - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of INP : signal is false; - attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of DAC_IN_SDI : signal is true; - attribute syn_useioff of DAC_OUT_SDO : signal is true; - attribute syn_useioff of DAC_OUT_SCK : signal is true; - attribute syn_useioff of DAC_OUT_CS : signal is true; - attribute syn_useioff of DAC_OUT_CLR : signal is true; - - -end entity; - - -architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 0; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - - --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --LVL1 channel - signal timing_trg_received_i : std_logic; - signal trg_data_valid_i : std_logic; - signal trg_timing_valid_i : std_logic; - signal trg_notiming_valid_i : std_logic; - signal trg_invalid_i : std_logic; - signal trg_type_i : std_logic_vector(3 downto 0); - signal trg_number_i : std_logic_vector(15 downto 0); - signal trg_code_i : std_logic_vector(7 downto 0); - signal trg_information_i : std_logic_vector(23 downto 0); - signal trg_int_number_i : std_logic_vector(15 downto 0); - signal trg_multiple_trg_i : std_logic; - signal trg_timeout_detected_i : std_logic; - signal trg_spurious_trg_i : std_logic; - signal trg_missing_tmg_trg_i : std_logic; - signal trg_spike_detected_i : std_logic; - - --Data channel - signal fee_trg_release_i : std_logic; - signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); - signal fee_data_i : std_logic_vector(31 downto 0); - signal fee_data_write_i : std_logic; - signal fee_data_finished_i : std_logic; - signal fee_almost_full_i : std_logic; - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - signal spidac_read_en : std_logic; - signal spidac_write_en : std_logic; - signal spidac_data_in : std_logic_vector(31 downto 0); - signal spidac_addr : std_logic_vector(4 downto 0); - signal spidac_data_out : std_logic_vector(31 downto 0); - signal spidac_ack : std_logic; - signal spidac_busy : std_logic; - - signal dac_cs_i : std_logic_vector(3 downto 0); - signal dac_sck_i : std_logic; - signal dac_sdi_i : std_logic; - - signal hitreg_read_en : std_logic; - signal hitreg_write_en : std_logic; - signal hitreg_addr : std_logic_vector(6 downto 0); - signal hitreg_data_out : std_logic_vector(31 downto 0); - signal hitreg_data_ready : std_logic; - signal hitreg_invalid : std_logic; - - signal srb_read_en : std_logic; - signal srb_write_en : std_logic; - signal srb_addr : std_logic_vector(6 downto 0); - signal srb_data_out : std_logic_vector(31 downto 0); - signal srb_data_ready : std_logic; - signal srb_invalid : std_logic; - - signal cdb_read_en : std_logic; - signal cdb_write_en : std_logic; - signal cdb_addr : std_logic_vector(6 downto 0); - signal cdb_data_out : std_logic_vector(31 downto 0); - signal cdb_data_ready : std_logic; - signal cdb_invalid : std_logic; - - signal lhb_read_en : std_logic; - signal lhb_write_en : std_logic; - signal lhb_addr : std_logic_vector(6 downto 0); - signal lhb_data_out : std_logic_vector(31 downto 0); - signal lhb_data_ready : std_logic; - signal lhb_invalid : std_logic; - - signal esb_read_en : std_logic; - signal esb_write_en : std_logic; - signal esb_addr : std_logic_vector(6 downto 0); - signal esb_data_out : std_logic_vector(31 downto 0); - signal esb_data_ready : std_logic; - signal esb_invalid : std_logic; - - signal efb_read_en : std_logic; - signal efb_write_en : std_logic; - signal efb_addr : std_logic_vector(6 downto 0); - signal efb_data_out : std_logic_vector(31 downto 0); - signal efb_data_ready : std_logic; - signal efb_invalid : std_logic; - - signal tdc_ctrl_read : std_logic; - signal last_tdc_ctrl_read : std_logic; - signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(2 downto 0); - signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); - signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal trig_out : std_logic_vector(3 downto 0); - signal trig_din : std_logic_vector(31 downto 0); - signal trig_dout : std_logic_vector(31 downto 0); - signal trig_write : std_logic := '0'; - signal trig_read : std_logic := '0'; - signal trig_ack : std_logic := '0'; - signal trig_nack : std_logic := '0'; - signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal stat_out : std_logic_vector(3 downto 0); - signal stat_din : std_logic_vector(31 downto 0); - signal stat_dout : std_logic_vector(31 downto 0); - signal stat_write : std_logic := '0'; - signal stat_read : std_logic := '0'; - signal stat_ack : std_logic := '0'; - signal stat_nack : std_logic := '0'; - signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); - - --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal logic_analyser_i : std_logic_vector(15 downto 0); - -begin ---------------------------------------------------------------------------- --- Reset Generation ---------------------------------------------------------------------------- - - GSR_N <= pll_lock; - - THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------------- --- Clock Handling ---------------------------------------------------------------------------- - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_RIGHT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); - - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF - port map ( - OSC => osc_int); - - - - ---------------------------------------------------------------------------- --- The TrbNet media interface (to other FPGA) ---------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_125_MHZ => c_NO, - USE_CTC => c_NO - ) - port map( - CLK => clk_200_i, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - --SFP Connection - SD_RXD_P_IN => SERDES_INT_RX(2), - SD_RXD_N_IN => SERDES_INT_RX(3), - SD_TXD_P_OUT => SERDES_INT_TX(2), - SD_TXD_N_OUT => SERDES_INT_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - REGIO_INIT_ADDRESS => INIT_ADDRESS, - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 12, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**12-400, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, - LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, - LVL1_INVALID_TRG_OUT => trg_invalid_i, - - LVL1_TRG_TYPE_OUT => trg_type_i, - LVL1_TRG_NUMBER_OUT => trg_number_i, - LVL1_TRG_CODE_OUT => trg_code_i, - LVL1_TRG_INFORMATION_OUT => trg_information_i, - LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, - TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, - TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, - TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, - TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - - --Response from FEE - FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, - FEE_DATA_IN => fee_data_i, - FEE_DATA_WRITE_IN(0) => fee_data_write_i, - FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, - FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open - ); - - ---------------------------------------------------------------------------- --- AddOn ---------------------------------------------------------------------------- - timing_trg_received_i <= TRIGGER_LEFT; - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", - 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", 9 => x"c200", --c300 c400 - others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, - 5 => 3, 6 => 6, 7 => 7, 8 => 4, 9 => 7, - others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - --Bus Handler (SPI DAC) - BUS_READ_ENABLE_OUT(2) => spidac_read_en, - BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, - BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, - BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, - BUS_DATAREADY_IN(2) => spidac_ack, - BUS_WRITE_ACK_IN(2) => spidac_ack, - BUS_NO_MORE_DATA_IN(2) => spidac_busy, - BUS_UNKNOWN_ADDR_IN(2) => '0', - --HitRegisters - BUS_READ_ENABLE_OUT(3) => hitreg_read_en, - BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, - BUS_DATA_OUT(3*32+31 downto 3*32) => open, - BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, - BUS_DATAREADY_IN(3) => hitreg_data_ready, - BUS_WRITE_ACK_IN(3) => '0', - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, - --Status Registers - BUS_READ_ENABLE_OUT(4) => srb_read_en, - BUS_WRITE_ENABLE_OUT(4) => srb_write_en, - BUS_DATA_OUT(4*32+31 downto 4*32) => open, - BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, - BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, - BUS_DATAREADY_IN(4) => srb_data_ready, - BUS_WRITE_ACK_IN(4) => '0', - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, - --TDC config registers - BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read, - BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write, - BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out, - BUS_DATAREADY_IN(5) => last_tdc_ctrl_read, - BUS_WRITE_ACK_IN(5) => tdc_ctrl_write, - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => '0', - --Trigger logic registers - BUS_READ_ENABLE_OUT(6) => trig_read, - BUS_WRITE_ENABLE_OUT(6) => trig_write, - BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din, - BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout, - BUS_DATAREADY_IN(6) => trig_ack, - BUS_WRITE_ACK_IN(6) => trig_ack, - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => trig_nack, - --Input statistics - BUS_READ_ENABLE_OUT(7) => stat_read, - BUS_WRITE_ENABLE_OUT(7) => stat_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout, - BUS_DATAREADY_IN(7) => stat_ack, - BUS_WRITE_ACK_IN(7) => stat_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => stat_nack, - --SEU Detection - BUS_READ_ENABLE_OUT(8) => sed_read, - BUS_WRITE_ENABLE_OUT(8) => sed_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => sed_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => sed_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => sed_dout, - BUS_DATAREADY_IN(8) => sed_ack, - BUS_WRITE_ACK_IN(8) => sed_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => sed_nack, - --Channel Debug Registers - BUS_READ_ENABLE_OUT(9) => cdb_read_en, - BUS_WRITE_ENABLE_OUT(9) => cdb_write_en, - BUS_DATA_OUT(9*32+31 downto 9*32) => open, - BUS_ADDR_OUT(9*16+6 downto 9*16) => cdb_addr, - BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => cdb_data_out, - BUS_DATAREADY_IN(9) => cdb_data_ready, - BUS_WRITE_ACK_IN(9) => '0', - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => cdb_invalid, - - ----Encoder Start Registers - --BUS_READ_ENABLE_OUT(5) => esb_read_en, - --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, - --BUS_DATA_OUT(5*32+31 downto 5*32) => open, - --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, - --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, - --BUS_TIMEOUT_OUT(5) => open, - --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, - --BUS_DATAREADY_IN(5) => esb_data_ready, - --BUS_WRITE_ACK_IN(5) => '0', - --BUS_NO_MORE_DATA_IN(5) => '0', - --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, - ----Fifo Write Registers - --BUS_READ_ENABLE_OUT(6) => efb_read_en, - --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, - --BUS_DATA_OUT(6*32+31 downto 6*32) => open, - --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, - --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, - --BUS_TIMEOUT_OUT(6) => open, - --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, - --BUS_DATAREADY_IN(6) => efb_data_ready, - --BUS_WRITE_ACK_IN(6) => '0', - --BUS_NO_MORE_DATA_IN(6) => '0', - --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, - ----Lost Hit Registers - --BUS_READ_ENABLE_OUT(7) => lhb_read_en, - --BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, - --BUS_DATA_OUT(7*32+31 downto 7*32) => open, - --BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, - --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, - --BUS_TIMEOUT_OUT(7) => open, - --BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, - --BUS_DATAREADY_IN(7) => lhb_data_ready, - --BUS_WRITE_ACK_IN(7) => '0', - --BUS_NO_MORE_DATA_IN(7) => '0', - --BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, - - STAT_DEBUG => open - ); - - PROC_TDC_CTRL_REG : process - variable pos : integer; - begin - wait until rising_edge(clk_100_i); - pos := to_integer(unsigned(tdc_ctrl_addr))*32; - tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); - last_tdc_ctrl_read <= tdc_ctrl_read; - if tdc_ctrl_write = '1' then - tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; - end if; - end process; - ---------------------------------------------------------------------------- --- SPI / Flash ---------------------------------------------------------------------------- - - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - - -- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - -------------------------------------------------------------------------------- --- SPI -------------------------------------------------------------------------------- - gen_SPI : if INCLUDE_SPI = 1 generate - DAC_SPI : spi_ltc2600 - generic map ( - BITS => 14, - WAITCYCLES => 100) - port map ( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spidac_read_en, - BUS_WRITE_IN => spidac_write_en, - BUS_BUSY_OUT => spidac_busy, - BUS_ACK_OUT => spidac_ack, - BUS_ADDR_IN => spidac_addr, - BUS_DATA_IN => spidac_data_in, - BUS_DATA_OUT => spidac_data_out, - -- SPI connections - SPI_CS_OUT(0) => DAC_OUT_CS, - SPI_SDI_IN => DAC_IN_SDI, - SPI_SDO_OUT => DAC_OUT_SDO, - SPI_SCK_OUT => DAC_OUT_SCK, - SPI_CLR_OUT(0) => DAC_OUT_CLR - ); - end generate; - - - gen_NO_SPI : if INCLUDE_SPI = 0 generate - DAC_OUT_SDO <= trig_out(0); - DAC_OUT_SCK <= trig_out(1); - DAC_OUT_CS <= trig_out(2); - DAC_OUT_CLR <= trig_out(3); - end generate; - - ---------------------------------------------------------------------------- --- Trigger logic ---------------------------------------------------------------------------- - gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic - generic map( - INPUTS => PHYSICAL_INPUTS, - OUTPUTS => 4 - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), - OUTPUT => trig_out, - - DATA_IN => trig_din, - DATA_OUT => trig_dout, - WRITE_IN => trig_write, - READ_IN => trig_read, - ACK_OUT => trig_ack, - NACK_OUT => trig_nack, - ADDR_IN => trig_addr - ); - FPGA5_COMM(10 downto 7) <= trig_out; - end generate; - ---------------------------------------------------------------------------- --- Input Statistics ---------------------------------------------------------------------------- - gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate - - THE_STAT_LOGIC : entity work.input_statistics - generic map( - INPUTS => PHYSICAL_INPUTS - SINGLE_FIFO_ONLY => USE_SINGLE_FIFO - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), - - DATA_IN => stat_din, - DATA_OUT => stat_dout, - WRITE_IN => stat_write, - READ_IN => stat_read, - ACK_OUT => stat_ack, - NACK_OUT => stat_nack, - ADDR_IN => stat_addr - ); - end generate; - ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - LED_GREEN <= not med_stat_op(9); - LED_ORANGE <= not med_stat_op(10); - LED_RED <= '1'; - LED_YELLOW <= not med_stat_op(11); - ---------------------------------------------------------------------------- --- Test Connector - Logic Analyser ---------------------------------------------------------------------------- - - TEST_LINE <= logic_analyser_i; - -------------------------------------------------------------------------------- --- TDC -------------------------------------------------------------------------------- --- TDC -------------------------------------------------------------------------------- - - THE_TDC : TDC - generic map ( - CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels - STATUS_REG_NR => 21, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => TDC_VERSION, -- TDC version number - SIMULATION => c_NO) - port map ( - RESET => reset_i, - CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement - CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC - TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width - TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width - -- Trigger signals from handler - TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet - VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet - VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet - INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet - TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet - SPIKE_DETECTED_IN => trg_spike_detected_i, - MULTI_TMG_TRG_IN => trg_multiple_trg_i, - SPURIOUS_TRG_IN => trg_spurious_trg_i, - -- - TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package - TRG_CODE_IN => trg_code_i, -- - TRG_INFORMATION_IN => trg_information_i, -- - TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package - -- - --Response to handler - TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal - TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc - DATA_OUT => fee_data_i, -- tdc data - DATA_WRITE_OUT => fee_data_write_i, -- data valid signal - DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal - -- - --Hit Counter Bus - HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe - HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe - HCB_ADDR_IN => hitreg_addr, -- bus address - HCB_DATA_OUT => hitreg_data_out, -- bus data - HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe - HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr - --Status Registers Bus - SRB_READ_EN_IN => srb_read_en, -- bus read en strobe - SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe - SRB_ADDR_IN => srb_addr, -- bus address - SRB_DATA_OUT => srb_data_out, -- bus data - SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe - SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr - --Channel Debug Bus - CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe - CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe - CDB_ADDR_IN => cdb_addr, -- bus address - CDB_DATA_OUT => cdb_data_out, -- bus data - CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe - CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr - --Encoder Start Registers Bus - ESB_READ_EN_IN => esb_read_en, -- bus read en strobe - ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe - ESB_ADDR_IN => esb_addr, -- bus address - ESB_DATA_OUT => esb_data_out, -- bus data - ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe - ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr - --Fifo Write Registers Bus - EFB_READ_EN_IN => efb_read_en, -- bus read en strobe - EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe - EFB_ADDR_IN => efb_addr, -- bus address - EFB_DATA_OUT => efb_data_out, -- bus data - EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe - EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr - --Lost Hit Registers Bus - LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe - LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe - LHB_ADDR_IN => lhb_addr, -- bus address - LHB_DATA_OUT => lhb_data_out, -- bus data - LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe - LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr - -- - LOGIC_ANALYSER_OUT => logic_analyser_i, - CONTROL_REG_IN => tdc_ctrl_reg); - - -- For single edge measurements - gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - hit_in_i <= INP; - end generate; - - -- For ToT Measurements - gen_double : if DOUBLE_EDGE_TYPE = 2 generate - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - end generate Gen_Hit_In_Signals; - end generate; - - -end architecture; diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.7.xx b/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.7.xx deleted file mode 100644 index 44d80cb..0000000 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd.1.7.xx +++ /dev/null @@ -1,999 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.tdc_components.all; -use work.config.all; -use work.tdc_version.all; -use work.version.all; - - -entity trb3_periph_32PinAddOn is - port( - --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out - TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - --Serdes - CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - SERDES_INT_TX : out std_logic_vector(3 downto 0); - SERDES_INT_RX : in std_logic_vector(3 downto 0); - SERDES_ADDON_TX : out std_logic_vector(11 downto 0); - SERDES_ADDON_RX : in std_logic_vector(11 downto 0); - --Inter-FPGA Communication - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - --Connection to ADA AddOn - SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only - INP : in std_logic_vector(63 downto 0); - --DAC - DAC_IN_SDI : in std_logic; - DAC_OUT_SDO : out std_logic; - DAC_OUT_SCK : out std_logic; - DAC_OUT_CS : out std_logic; - DAC_OUT_CLR : out std_logic; - - --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - SUPPL : in std_logic; --terminated diff pair, PCLK, Pads - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of CODE_LINE : signal is false; - attribute syn_useioff of TRIGGER_LEFT : signal is false; - attribute syn_useioff of TRIGGER_RIGHT : signal is false; - --important signals - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of INP : signal is false; - attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of DAC_IN_SDI : signal is true; - attribute syn_useioff of DAC_OUT_SDO : signal is true; - attribute syn_useioff of DAC_OUT_SCK : signal is true; - attribute syn_useioff of DAC_OUT_CS : signal is true; - attribute syn_useioff of DAC_OUT_CLR : signal is true; - - -end entity; - - -architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 0; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - - --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --LVL1 channel - signal timing_trg_received_i : std_logic; - signal trg_data_valid_i : std_logic; - signal trg_timing_valid_i : std_logic; - signal trg_notiming_valid_i : std_logic; - signal trg_invalid_i : std_logic; - signal trg_type_i : std_logic_vector(3 downto 0); - signal trg_number_i : std_logic_vector(15 downto 0); - signal trg_code_i : std_logic_vector(7 downto 0); - signal trg_information_i : std_logic_vector(23 downto 0); - signal trg_int_number_i : std_logic_vector(15 downto 0); - signal trg_multiple_trg_i : std_logic; - signal trg_timeout_detected_i : std_logic; - signal trg_spurious_trg_i : std_logic; - signal trg_missing_tmg_trg_i : std_logic; - signal trg_spike_detected_i : std_logic; - - --Data channel - signal fee_trg_release_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_trg_statusbits_i : std_logic_vector_array_32(0 to NUM_TDC_MODULES); - signal fee_data_i : std_logic_vector_array_32(0 to NUM_TDC_MODULES); - signal fee_data_write_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_data_finished_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_almost_full_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_trg_statusbits : std_logic_vector((NUM_TDC_MODULES+1)*32-1 downto 0); - signal fee_data : std_logic_vector((NUM_TDC_MODULES+1)*32-1 downto 0); - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - signal spidac_read_en : std_logic; - signal spidac_write_en : std_logic; - signal spidac_data_in : std_logic_vector(31 downto 0); - signal spidac_addr : std_logic_vector(4 downto 0); - signal spidac_data_out : std_logic_vector(31 downto 0); - signal spidac_ack : std_logic; - signal spidac_busy : std_logic; - - signal dac_cs_i : std_logic_vector(3 downto 0); - signal dac_sck_i : std_logic; - signal dac_sdi_i : std_logic; - - signal hitreg_read_en : std_logic; - signal hitreg_write_en : std_logic; - signal hitreg_addr : std_logic_vector(6 downto 0); - signal hitreg_data_out : std_logic_vector(31 downto 0); - signal hitreg_data_ready : std_logic; - signal hitreg_invalid : std_logic; - - signal srb_read_en : std_logic; - signal srb_write_en : std_logic; - signal srb_addr : std_logic_vector(6 downto 0); - signal srb_data_out : std_logic_vector(31 downto 0); - signal srb_data_ready : std_logic; - signal srb_invalid : std_logic; - - signal cdb_read_en : std_logic; - signal cdb_write_en : std_logic; - signal cdb_addr : std_logic_vector(6 downto 0); - signal cdb_data_out : std_logic_vector(31 downto 0); - signal cdb_data_ready : std_logic; - signal cdb_invalid : std_logic; - - signal lhb_read_en : std_logic; - signal lhb_write_en : std_logic; - signal lhb_addr : std_logic_vector(6 downto 0); - signal lhb_data_out : std_logic_vector(31 downto 0); - signal lhb_data_ready : std_logic; - signal lhb_invalid : std_logic; - - signal esb_read_en : std_logic; - signal esb_write_en : std_logic; - signal esb_addr : std_logic_vector(6 downto 0); - signal esb_data_out : std_logic_vector(31 downto 0); - signal esb_data_ready : std_logic; - signal esb_invalid : std_logic; - - signal efb_read_en : std_logic; - signal efb_write_en : std_logic; - signal efb_addr : std_logic_vector(6 downto 0); - signal efb_data_out : std_logic_vector(31 downto 0); - signal efb_data_ready : std_logic; - signal efb_invalid : std_logic; - - signal tdc_ctrl_read : std_logic; - signal last_tdc_ctrl_read : std_logic; - signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(2 downto 0); - signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); - signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0); - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal trig_out : std_logic_vector(3 downto 0); - signal trig_din : std_logic_vector(31 downto 0); - signal trig_dout : std_logic_vector(31 downto 0); - signal trig_write : std_logic := '0'; - signal trig_read : std_logic := '0'; - signal trig_ack : std_logic := '0'; - signal trig_nack : std_logic := '0'; - signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal stat_out : std_logic_vector(3 downto 0); - signal stat_din : std_logic_vector(31 downto 0); - signal stat_dout : std_logic_vector(31 downto 0); - signal stat_write : std_logic := '0'; - signal stat_read : std_logic := '0'; - signal stat_ack : std_logic := '0'; - signal stat_nack : std_logic := '0'; - signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); - - --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal logic_analyser_i : std_logic_vector(15 downto 0); - -begin ---------------------------------------------------------------------------- --- Reset Generation ---------------------------------------------------------------------------- - - GSR_N <= pll_lock; - - THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------------- --- Clock Handling ---------------------------------------------------------------------------- - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_RIGHT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); - - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF - port map ( - OSC => osc_int); - - - - ---------------------------------------------------------------------------- --- The TrbNet media interface (to other FPGA) ---------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_125_MHZ => c_NO, - USE_CTC => c_NO - ) - port map( - CLK => clk_200_i, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - --SFP Connection - SD_RXD_P_IN => SERDES_INT_RX(2), - SD_RXD_N_IN => SERDES_INT_RX(3), - SD_TXD_P_OUT => SERDES_INT_TX(2), - SD_TXD_N_OUT => SERDES_INT_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - REGIO_INIT_ADDRESS => INIT_ADDRESS, - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => NUM_TDC_MODULES+1, - DATA_BUFFER_DEPTH => 12, --13, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**12-400, --2**13-800, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, - LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, - LVL1_INVALID_TRG_OUT => trg_invalid_i, - - LVL1_TRG_TYPE_OUT => trg_type_i, - LVL1_TRG_NUMBER_OUT => trg_number_i, - LVL1_TRG_CODE_OUT => trg_code_i, - LVL1_TRG_INFORMATION_OUT => trg_information_i, - LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, - TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, - TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, - TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, - TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - - --Response from FEE - FEE_TRG_RELEASE_IN(NUM_TDC_MODULES downto 0) => fee_trg_release_i, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits, - FEE_DATA_IN => fee_data, - FEE_DATA_WRITE_IN(NUM_TDC_MODULES downto 0) => fee_data_write_i, - FEE_DATA_FINISHED_IN(NUM_TDC_MODULES downto 0) => fee_data_finished_i, - FEE_DATA_ALMOST_FULL_OUT(NUM_TDC_MODULES downto 0) => fee_almost_full_i, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open - ); - - timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- - common_stat_reg <= (others => '0'); - stat_reg <= (others => '0'); - - Allign_Bits : for i in 0 to NUM_TDC_MODULES-1 generate - fee_trg_statusbits((i+1)*32-1 downto i*32) <= fee_trg_statusbits_i(i)(31 downto 0); - fee_data((i+1)*32-1 downto i*32) <= fee_data_i(i)(31 downto 0); - end generate Allign_Bits; - ---------------------------------------------------------------------------- --- AddOn ---------------------------------------------------------------------------- - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", - 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", 9 => x"c200", --c300 c400 - others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, - 5 => 3, 6 => 6, 7 => 7, 8 => 4, 9 => 7, - others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - --Bus Handler (SPI DAC) - BUS_READ_ENABLE_OUT(2) => spidac_read_en, - BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, - BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, - BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, - BUS_DATAREADY_IN(2) => spidac_ack, - BUS_WRITE_ACK_IN(2) => spidac_ack, - BUS_NO_MORE_DATA_IN(2) => spidac_busy, - BUS_UNKNOWN_ADDR_IN(2) => '0', - --HitRegisters - BUS_READ_ENABLE_OUT(3) => hitreg_read_en, - BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, - BUS_DATA_OUT(3*32+31 downto 3*32) => open, - BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, - BUS_DATAREADY_IN(3) => hitreg_data_ready, - BUS_WRITE_ACK_IN(3) => '0', - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, - --Status Registers - BUS_READ_ENABLE_OUT(4) => srb_read_en, - BUS_WRITE_ENABLE_OUT(4) => srb_write_en, - BUS_DATA_OUT(4*32+31 downto 4*32) => open, - BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, - BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, - BUS_DATAREADY_IN(4) => srb_data_ready, - BUS_WRITE_ACK_IN(4) => '0', - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, - --TDC config registers - BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read, - BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write, - BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out, - BUS_DATAREADY_IN(5) => last_tdc_ctrl_read, - BUS_WRITE_ACK_IN(5) => tdc_ctrl_write, - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => '0', - --Trigger logic registers - BUS_READ_ENABLE_OUT(6) => trig_read, - BUS_WRITE_ENABLE_OUT(6) => trig_write, - BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din, - BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout, - BUS_DATAREADY_IN(6) => trig_ack, - BUS_WRITE_ACK_IN(6) => trig_ack, - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => trig_nack, - --Input statistics - BUS_READ_ENABLE_OUT(7) => stat_read, - BUS_WRITE_ENABLE_OUT(7) => stat_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout, - BUS_DATAREADY_IN(7) => stat_ack, - BUS_WRITE_ACK_IN(7) => stat_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => stat_nack, - --SEU Detection - BUS_READ_ENABLE_OUT(8) => sed_read, - BUS_WRITE_ENABLE_OUT(8) => sed_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => sed_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => sed_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => sed_dout, - BUS_DATAREADY_IN(8) => sed_ack, - BUS_WRITE_ACK_IN(8) => sed_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => sed_nack, - --Channel Debug Registers - BUS_READ_ENABLE_OUT(9) => cdb_read_en, - BUS_WRITE_ENABLE_OUT(9) => cdb_write_en, - BUS_DATA_OUT(9*32+31 downto 9*32) => open, - BUS_ADDR_OUT(9*16+6 downto 9*16) => cdb_addr, - BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => cdb_data_out, - BUS_DATAREADY_IN(9) => cdb_data_ready, - BUS_WRITE_ACK_IN(9) => '0', - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => cdb_invalid, - - ----Encoder Start Registers - --BUS_READ_ENABLE_OUT(5) => esb_read_en, - --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, - --BUS_DATA_OUT(5*32+31 downto 5*32) => open, - --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, - --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, - --BUS_TIMEOUT_OUT(5) => open, - --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, - --BUS_DATAREADY_IN(5) => esb_data_ready, - --BUS_WRITE_ACK_IN(5) => '0', - --BUS_NO_MORE_DATA_IN(5) => '0', - --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, - ----Fifo Write Registers - --BUS_READ_ENABLE_OUT(6) => efb_read_en, - --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, - --BUS_DATA_OUT(6*32+31 downto 6*32) => open, - --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, - --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, - --BUS_TIMEOUT_OUT(6) => open, - --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, - --BUS_DATAREADY_IN(6) => efb_data_ready, - --BUS_WRITE_ACK_IN(6) => '0', - --BUS_NO_MORE_DATA_IN(6) => '0', - --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, - ----Lost Hit Registers - --BUS_READ_ENABLE_OUT(7) => lhb_read_en, - --BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, - --BUS_DATA_OUT(7*32+31 downto 7*32) => open, - --BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, - --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, - --BUS_TIMEOUT_OUT(7) => open, - --BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, - --BUS_DATAREADY_IN(7) => lhb_data_ready, - --BUS_WRITE_ACK_IN(7) => '0', - --BUS_NO_MORE_DATA_IN(7) => '0', - --BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, - - STAT_DEBUG => open - ); - - PROC_TDC_CTRL_REG : process - variable pos : integer; - begin - wait until rising_edge(clk_100_i); - pos := to_integer(unsigned(tdc_ctrl_addr))*32; - tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); - last_tdc_ctrl_read <= tdc_ctrl_read; - if tdc_ctrl_write = '1' then - tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; - end if; - end process; - ---------------------------------------------------------------------------- --- SPI / Flash ---------------------------------------------------------------------------- - - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - - -- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - -------------------------------------------------------------------------------- --- SPI -------------------------------------------------------------------------------- - gen_SPI : if INCLUDE_SPI = 1 generate - DAC_SPI : spi_ltc2600 - generic map ( - BITS => 14, - WAITCYCLES => 100) - port map ( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spidac_read_en, - BUS_WRITE_IN => spidac_write_en, - BUS_BUSY_OUT => spidac_busy, - BUS_ACK_OUT => spidac_ack, - BUS_ADDR_IN => spidac_addr, - BUS_DATA_IN => spidac_data_in, - BUS_DATA_OUT => spidac_data_out, - -- SPI connections - SPI_CS_OUT(0) => DAC_OUT_CS, - SPI_SDI_IN => DAC_IN_SDI, - SPI_SDO_OUT => DAC_OUT_SDO, - SPI_SCK_OUT => DAC_OUT_SCK, - SPI_CLR_OUT(0) => DAC_OUT_CLR - ); - end generate; - - - gen_NO_SPI : if INCLUDE_SPI = 0 generate - DAC_OUT_SDO <= trig_out(0); - DAC_OUT_SCK <= trig_out(1); - DAC_OUT_CS <= trig_out(2); - DAC_OUT_CLR <= trig_out(3); - end generate; - - ---------------------------------------------------------------------------- --- Trigger logic ---------------------------------------------------------------------------- - gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic - generic map( - INPUTS => PHYSICAL_INPUTS, - OUTPUTS => 4 - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), - OUTPUT => trig_out, - - DATA_IN => trig_din, - DATA_OUT => trig_dout, - WRITE_IN => trig_write, - READ_IN => trig_read, - ACK_OUT => trig_ack, - NACK_OUT => trig_nack, - ADDR_IN => trig_addr - ); - FPGA5_COMM(10 downto 7) <= trig_out; - end generate; - ---------------------------------------------------------------------------- --- Input Statistics ---------------------------------------------------------------------------- - gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate - - THE_STAT_LOGIC : entity work.input_statistics - generic map( - INPUTS => PHYSICAL_INPUTS - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS downto 1), - - DATA_IN => stat_din, - DATA_OUT => stat_dout, - WRITE_IN => stat_write, - READ_IN => stat_read, - ACK_OUT => stat_ack, - NACK_OUT => stat_nack, - ADDR_IN => stat_addr - ); - end generate; - ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - LED_GREEN <= not med_stat_op(9); - LED_ORANGE <= not med_stat_op(10); - LED_RED <= '1'; - LED_YELLOW <= not med_stat_op(11); - ---------------------------------------------------------------------------- --- Test Connector - Logic Analyser ---------------------------------------------------------------------------- - - TEST_LINE <= logic_analyser_i; - -------------------------------------------------------------------------------- --- TDC -------------------------------------------------------------------------------- - - THE_TDC : TDC - generic map ( - MODULE_NUMBER => NUM_TDC_MODULES, -- Number of TDC modules - CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of channels per module - STATUS_REG_NR => 21, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => TDC_VERSION, -- TDC version number - DEBUG => c_YES, - SIMULATION => c_NO) - port map ( - RESET => reset_i, - CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement - CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(NUM_TDC_MODULES*NUM_TDC_CHANNELS downto 1), -- Channel start signals - HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC - TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width - TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width - -- - -- Trigger signals from handler - TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet - VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet - VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet - INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet - TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet - SPIKE_DETECTED_IN => trg_spike_detected_i, - MULTI_TMG_TRG_IN => trg_multiple_trg_i, - SPURIOUS_TRG_IN => trg_spurious_trg_i, - -- - TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package - TRG_CODE_IN => trg_code_i, -- - TRG_INFORMATION_IN => trg_information_i, -- - TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package - -- - --Response to handler - TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal - TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc - DATA_OUT => fee_data_i, -- tdc data - DATA_WRITE_OUT => fee_data_write_i, -- data valid signal - DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal - -- - --Hit Counter Bus - HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe - HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe - HCB_ADDR_IN => hitreg_addr, -- bus address - HCB_DATA_OUT => hitreg_data_out, -- bus data - HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe - HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr - --Status Registers Bus - SRB_READ_EN_IN => srb_read_en, -- bus read en strobe - SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe - SRB_ADDR_IN => srb_addr, -- bus address - SRB_DATA_OUT => srb_data_out, -- bus data - SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe - SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr - --Channel Debug Bus - CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe - CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe - CDB_ADDR_IN => cdb_addr, -- bus address - CDB_DATA_OUT => cdb_data_out, -- bus data - CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe - CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr - --Encoder Start Registers Bus - ESB_READ_EN_IN => esb_read_en, -- bus read en strobe - ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe - ESB_ADDR_IN => esb_addr, -- bus address - ESB_DATA_OUT => esb_data_out, -- bus data - ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe - ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr - --Fifo Write Registers Bus - EFB_READ_EN_IN => efb_read_en, -- bus read en strobe - EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe - EFB_ADDR_IN => efb_addr, -- bus address - EFB_DATA_OUT => efb_data_out, -- bus data - EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe - EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr - --Lost Hit Registers Bus - LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe - LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe - LHB_ADDR_IN => lhb_addr, -- bus address - LHB_DATA_OUT => lhb_data_out, -- bus data - LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe - LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr - -- - LOGIC_ANALYSER_OUT => logic_analyser_i, - CONTROL_REG_IN => tdc_ctrl_reg); - - -- For single edge measurements - gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - hit_in_i <= INP; - end generate; - - -- For ToT Measurements - gen_double : if DOUBLE_EDGE_TYPE = 2 generate - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - end generate Gen_Hit_In_Signals; - end generate; - - -end architecture; diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd deleted file mode 120000 index dcae83b..0000000 --- a/base/trb3_components.vhd +++ /dev/null @@ -1 +0,0 @@ -trb3_components_1-6-x.vhd \ No newline at end of file diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd new file mode 100644 index 0000000..03601f7 --- /dev/null +++ b/base/trb3_components.vhd @@ -0,0 +1,1929 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.trb_net_std.all; + +package trb3_components is + + type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0); + type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0); + type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0); + type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0); + type std_logic_vector_array_8 is array (integer range <>) of std_logic_vector(7 downto 0); + type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0); + + component oddr is + port ( + clk : in std_logic; + clkout : out std_logic; + da : in std_logic_vector(0 downto 0); + db : in std_logic_vector(0 downto 0); + q : out std_logic_vector(0 downto 0)); + end component; + + component pll_in125_out125 + port ( + CLK : in std_logic; + CLKOP : out std_logic; --125 MHz + CLKOK : out std_logic; --125 MHz, bypass + LOCK : out std_logic + ); + end component; + + component pll_in125_out20 is + port ( + CLK : in std_logic; + CLKOP : out std_logic; -- 20 MHz + CLKOK : out std_logic; -- 125 MHz, bypass + LOCK : out std_logic); + end component pll_in125_out20; + + component OSCF -- internal oscillator with a frequency of 2MHz + port (OSC : out + std_logic); + end component; + + component TDC is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + STATUS_REG_NR : integer range 0 to 31; + CONTROL_REG_NR : integer range 0 to 6; + TDC_VERSION : std_logic_vector(11 downto 0); + DEBUG : integer range 0 to 1 := c_YES; + SIMULATION : integer range 0 to 1 := c_NO); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + REFERENCE_TIME : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); + HIT_CALIBRATION : in std_logic; + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + HCB_READ_EN_IN : in std_logic; + HCB_WRITE_EN_IN : in std_logic; + HCB_ADDR_IN : in std_logic_vector(6 downto 0); + HCB_DATA_OUT : out std_logic_vector(31 downto 0); + HCB_DATAREADY_OUT : out std_logic; + HCB_UNKNOWN_ADDR_OUT : out std_logic; + SRB_READ_EN_IN : in std_logic; + SRB_WRITE_EN_IN : in std_logic; + SRB_ADDR_IN : in std_logic_vector(6 downto 0); + SRB_DATA_OUT : out std_logic_vector(31 downto 0); + SRB_DATAREADY_OUT : out std_logic; + SRB_UNKNOWN_ADDR_OUT : out std_logic; + CDB_READ_EN_IN : in std_logic; + CDB_WRITE_EN_IN : in std_logic; + CDB_ADDR_IN : in std_logic_vector(6 downto 0); + CDB_DATA_OUT : out std_logic_vector(31 downto 0); + CDB_DATAREADY_OUT : out std_logic; + CDB_UNKNOWN_ADDR_OUT : out std_logic; + ESB_READ_EN_IN : in std_logic; + ESB_WRITE_EN_IN : in std_logic; + ESB_ADDR_IN : in std_logic_vector(6 downto 0); + ESB_DATA_OUT : out std_logic_vector(31 downto 0); + ESB_DATAREADY_OUT : out std_logic; + ESB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; + FWB_READ_EN_IN : in std_logic; -- not used after version 1.3 + FWB_WRITE_EN_IN : in std_logic; -- not used after version 1.3 + FWB_ADDR_IN : in std_logic_vector(6 downto 0); -- not used after version 1.3 + FWB_DATA_OUT : out std_logic_vector(31 downto 0); -- not used after version 1.3 + FWB_DATAREADY_OUT : out std_logic; -- not used after version 1.3 + FWB_UNKNOWN_ADDR_OUT : out std_logic; -- not used after version 1.3 + LHB_READ_EN_IN : in std_logic; + LHB_WRITE_EN_IN : in std_logic; + LHB_ADDR_IN : in std_logic_vector(6 downto 0); + LHB_DATA_OUT : out std_logic_vector(31 downto 0); + LHB_DATAREADY_OUT : out std_logic; + LHB_UNKNOWN_ADDR_OUT : out std_logic; + LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); + CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0)); + end component TDC; + + component Reference_Channel + generic ( + CHANNEL_ID : integer range 0 to 0); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; + HIT_IN : in std_logic; + READ_EN_IN : in std_logic; + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_WINDOW_END_IN : in std_logic; + DATA_FINISHED_IN : in std_logic; + RUN_MODE : in std_logic; + TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); + REF_DEBUG_OUT : out std_logic_vector(31 downto 0)); + end component; + + component Reference_Channel_200 + generic ( + CHANNEL_ID : integer range 0 to 0); + port ( + CLK_200 : in std_logic; + RESET_200 : in std_logic; + CLK_100 : in std_logic; + RESET_100 : in std_logic; + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + HIT_IN : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_WINDOW_END_IN : in std_logic; + TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); + DATA_FINISHED_IN : in std_logic; + RUN_MODE : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); + end component; + + component Channel + generic ( + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; + HIT_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_EMPTY_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; + LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); + Channel_200_DEBUG : out std_logic_vector(31 downto 0); + Channel_DEBUG : out std_logic_vector(31 downto 0)); + end component; + + component Channel_200 + generic ( + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + CLK_200 : in std_logic; + RESET_200 : in std_logic; + CLK_100 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + HIT_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; + ENCODER_START_OUT : out std_logic; + ENCODER_FINISHED_OUT : out std_logic; + FIFO_WRITE_OUT : out std_logic; + Channel_200_DEBUG : out std_logic_vector(31 downto 0)); + end component; + + component Readout is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + STATUS_REG_NR : integer range 0 to 31; + TDC_VERSION : std_logic_vector(11 downto 0)); + port ( + RESET_100 : in std_logic; + RESET_200 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; + TRIGGER_RDO_IN : in std_logic; + TRIGGER_TDC_IN : in std_logic; + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRG_DATA_VALID_IN : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TMGTRG_TIMEOUT_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + SPURIOUS_TRG_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_LIMIT_IN : in unsigned(7 downto 0); + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIG_WIN_END_TDC_IN : in std_logic; + TRIG_WIN_END_RDO_IN : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + DEBUG_MODE_EN_IN : in std_logic; + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to STATUS_REG_NR-1); + READOUT_DEBUG : out std_logic_vector(31 downto 0); +-- ports not used after tdc_v1.5.2 + TRIGGER_WIN_END_OUT : out std_logic; + CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); + REFERENCE_TIME : in std_logic; + TRIGGER_TIME_IN : in std_logic_vector(38 downto 0) + ); + end component Readout; + + + component TriggerHandler is + generic ( + TRIGGER_NUM : integer; + PHYSICAL_EVENT_TRG_NUM : integer); + port ( + CLK_TRG : in std_logic; + CLK_RDO : in std_logic; + CLK_TDC : in std_logic; + RESET_TRG : in std_logic; + RESET_RDO : in std_logic; + RESET_TDC : in std_logic; + TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIGGER_WIN_POST_IN : in unsigned(10 downto 0); + TRIGGER_WIN_END_RDO_OUT : out std_logic; + TRIGGER_WIN_END_TDC_OUT : out std_logic); + end component TriggerHandler; + + component LogicAnalyser + generic ( + CHANNEL_NUMBER : integer range 2 to 65); + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_IN : in std_logic_vector(3*32-1 downto 0); + CONTROL_IN : in std_logic_vector(3 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0)); + end component; + + component BusHandler + generic ( + BUS_LENGTH : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic); + end component; + + component ROM_FIFO + port ( + Address : in std_logic_vector(7 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(3 downto 0)); + end component; + + component up_counter + generic ( + NUMBER_OF_BITS : positive); + port ( + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic); + end component; + + component Adder_304 + port ( + CLK : in std_logic; + RESET : in std_logic; + DataA : in std_logic_vector(303 downto 0); + DataB : in std_logic_vector(303 downto 0); + ClkEn : in std_logic; + Result : out std_logic_vector(303 downto 0)); + end component; + + component Encoder_304_Bit is + port ( + RESET : in std_logic; + CLK : in std_logic; + START_IN : in std_logic; + THERMOCODE_IN : in std_logic_vector(303 downto 0); + FINISHED_OUT : out std_logic; + BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); + ENCODER_DEBUG : out std_logic_vector(31 downto 0)); + end component Encoder_304_Bit; + + --component Encoder_304_Bit + -- port ( + -- RESET : in std_logic; + -- CLK : in std_logic; + -- START_IN : in std_logic; + -- THERMOCODE_IN : in std_logic_vector(303 downto 0); + -- FINISHED_OUT : out std_logic; + -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + -- ENCODER_DEBUG : out std_logic_vector(31 downto 0)); + --end component; + + component hit_mux is + port ( + CH_EN_IN : in std_logic; + CALIBRATION_EN_IN : in std_logic; + HIT_CALIBRATION_IN : in std_logic; + HIT_PHYSICAL_IN : in std_logic; + HIT_OUT : out std_logic); + end component hit_mux; + + component FIFO_32x32_OutReg + port ( + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component; + + component FIFO_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x128_OutReg; + + component FIFO_36x64_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic); + end component; + + component FIFO_36x32_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x32_OutReg; + + component FIFO_36x16_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic); + end component; + + component FIFO_DC_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component FIFO_DC_36x128_OutReg; + + component FIFO_DC_36x64_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component FIFO_DC_36x64_OutReg; + + component FIFO_DC_36x32_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component; + + component FIFO_DC_36x16_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component; + + component FIFO_36x128_OutReg_Counter is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x128_OutReg_Counter; + +-- component FIFO_DC_36x32_OutReg is +-- port ( +-- Data : in std_logic_vector(35 downto 0); +-- WrClock : in std_logic; +-- RdClock : in std_logic; +-- WrEn : in std_logic; +-- RdEn : in std_logic; +-- Reset : in std_logic; +-- RPReset : in std_logic; +-- Q : out std_logic_vector(35 downto 0); +-- Empty : out std_logic; +-- Full : out std_logic; +-- AlmostFull : out std_logic); +-- end component; +-- +-- component FIFO_DC_36x16_OutReg is +-- port ( +-- Data : in std_logic_vector(35 downto 0); +-- WrClock : in std_logic; +-- RdClock : in std_logic; +-- WrEn : in std_logic; +-- RdEn : in std_logic; +-- Reset : in std_logic; +-- RPReset : in std_logic; +-- Q : out std_logic_vector(35 downto 0); +-- Empty : out std_logic; +-- Full : out std_logic; +-- AlmostFull : out std_logic); +-- end component; + + --component FIFO_24x2_OutReg + -- port ( + -- Data : in std_logic_vector(23 downto 0); + -- WrClock : in std_logic; + -- RdClock : in std_logic; + -- WrEn : in std_logic; + -- RdEn : in std_logic; + -- Reset : in std_logic; + -- RPReset : in std_logic; + -- Q : out std_logic_vector(23 downto 0); + -- Empty : out std_logic; + -- Full : out std_logic); + --end component; + + component ROM_Encoder + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); + end component; + + component ROM4_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); + end component ROM4_Encoder; + + component bit_sync + generic ( + DEPTH : integer); + port ( + RESET : in std_logic; + CLK0 : in std_logic; + CLK1 : in std_logic; + D_IN : in std_logic; + D_OUT : out std_logic); + end component; + + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + + component risingEdgeDetect is + port ( + CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); + end component risingEdgeDetect; + + component fallingEdgeDetect is + port ( + CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); + end component fallingEdgeDetect; + + component ShiftRegisterSISO + generic ( + DEPTH : integer range 1 to 32; + WIDTH : integer range 1 to 32); + port ( + CLK : in std_logic; + D_IN : in std_logic_vector(WIDTH-1 downto 0); + D_OUT : out std_logic_vector(WIDTH-1 downto 0)); + end component; + + component Stretcher + port ( + PULSE_IN : in std_logic; + PULSE_OUT : out std_logic); + end component; + + component WaveLauncher is + port ( + HIT_IN : in std_logic; + HIT_OUT : out std_logic); + end component WaveLauncher; + + component adc_ad9222 + generic( + CHANNELS : integer range 4 to 4 := 4; + DEVICES : integer range 2 to 2 := 2; + RESOLUTION : integer range 12 to 12 := 12 + ); + port( + CLK : in std_logic; + CLK_ADCREF : in std_logic; + CLK_ADCDAT : in std_logic; + RESTART_IN : in std_logic; + ADCCLK_OUT : out std_logic; + ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0); + ADC_DCO : in std_logic_vector(DEVICES-1 downto 0); + ADC_FCO : in std_logic_vector(DEVICES-1 downto 0); + + DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); + FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0); + DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + + ); + end component; + + component fifo_32x512 + port ( + Data : in std_logic_vector(31 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component; + + component dqsinput + port ( + clk_0 : in std_logic; + clk_1 : in std_logic; + clkdiv_reset : in std_logic; + eclk : in std_logic; + reset_0 : in std_logic; + reset_1 : in std_logic; + sclk : out std_logic; + datain_0 : in std_logic_vector(4 downto 0); + datain_1 : in std_logic_vector(4 downto 0); + q_0 : out std_logic_vector(19 downto 0); + q_1 : out std_logic_vector(19 downto 0) + ); + end component; + + component fifo_cdt_200 + port ( + Data : in std_logic_vector(59 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(59 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component; + + + component med_ecp3_sfp_sync is + generic( + SERDES_NUM : integer range 0 to 3 := 0; +-- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO + IS_SYNC_SLAVE : integer := 0 --select slave mode + ); + port( + CLK : in std_logic; -- _internal_ 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --Internal Connection TX + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic := '0'; + --Internal Connection RX + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic := '0'; + MED_READ_IN : in std_logic; + CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz + CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz + + --Sync operation + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; + + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; --not used + SD_REFCLK_N_IN : in std_logic; --not used + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); + end component; + + + component input_to_trigger_logic is + generic( + INPUTS : integer range 1 to 32 := 24; + OUTPUTS : integer range 1 to 16 := 4 + ); + port( + CLK : in std_logic; + + INPUT : in std_logic_vector(INPUTS-1 downto 0); + OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0); + + DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_IN : in std_logic := '0'; + READ_IN : in std_logic := '0'; + ACK_OUT : out std_logic; + NACK_OUT : out std_logic; + ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') + + ); + end component; + + component input_statistics is + generic ( + INPUTS : integer range 1 to 32); + port ( + CLK : in std_logic; + INPUT : in std_logic_vector(INPUTS-1 downto 0); + DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_IN : in std_logic := '0'; + READ_IN : in std_logic := '0'; + ACK_OUT : out std_logic; + NACK_OUT : out std_logic; + ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0')); + end component input_statistics; + + +component serdes_full_ctc is + GENERIC (USER_CONFIG_FILE : String := "serdes_full_ctc.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + ctc_urun_ch0_s : out std_logic; + ctc_orun_ch0_s : out std_logic; + ctc_ins_ch0_s : out std_logic; + ctc_del_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + ctc_urun_ch1_s : out std_logic; + ctc_orun_ch1_s : out std_logic; + ctc_ins_ch1_s : out std_logic; + ctc_del_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (15 downto 0); + tx_k_ch2 : in std_logic_vector (1 downto 0); + tx_force_disp_ch2 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); + rxdata_ch2 : out std_logic_vector (15 downto 0); + rx_k_ch2 : out std_logic_vector (1 downto 0); + rx_disp_err_ch2 : out std_logic_vector (1 downto 0); + rx_cv_err_ch2 : out std_logic_vector (1 downto 0); + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + ctc_urun_ch2_s : out std_logic; + ctc_orun_ch2_s : out std_logic; + ctc_ins_ch2_s : out std_logic; + ctc_del_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (15 downto 0); + tx_k_ch3 : in std_logic_vector (1 downto 0); + tx_force_disp_ch3 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); + rxdata_ch3 : out std_logic_vector (15 downto 0); + rx_k_ch3 : out std_logic_vector (1 downto 0); + rx_disp_err_ch3 : out std_logic_vector (1 downto 0); + rx_cv_err_ch3 : out std_logic_vector (1 downto 0); + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + ctc_urun_ch3_s : out std_logic; + ctc_orun_ch3_s : out std_logic; + ctc_ins_ch3_s : out std_logic; + ctc_del_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + refclk2fpga : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + +component serdes_full_noctc is + GENERIC (USER_CONFIG_FILE : String := "serdes_full_noctc.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (15 downto 0); + tx_k_ch2 : in std_logic_vector (1 downto 0); + tx_force_disp_ch2 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); + rxdata_ch2 : out std_logic_vector (15 downto 0); + rx_k_ch2 : out std_logic_vector (1 downto 0); + rx_disp_err_ch2 : out std_logic_vector (1 downto 0); + rx_cv_err_ch2 : out std_logic_vector (1 downto 0); + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (15 downto 0); + tx_k_ch3 : in std_logic_vector (1 downto 0); + tx_force_disp_ch3 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); + rxdata_ch3 : out std_logic_vector (15 downto 0); + rx_k_ch3 : out std_logic_vector (1 downto 0); + rx_disp_err_ch3 : out std_logic_vector (1 downto 0); + rx_cv_err_ch3 : out std_logic_vector (1 downto 0); + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + refclk2fpga : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component serdes_onboard_full is + GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (15 downto 0); + tx_k_ch2 : in std_logic_vector (1 downto 0); + tx_force_disp_ch2 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); + rxdata_ch2 : out std_logic_vector (15 downto 0); + rx_k_ch2 : out std_logic_vector (1 downto 0); + rx_disp_err_ch2 : out std_logic_vector (1 downto 0); + rx_cv_err_ch2 : out std_logic_vector (1 downto 0); + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (15 downto 0); + tx_k_ch3 : in std_logic_vector (1 downto 0); + tx_force_disp_ch3 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); + rxdata_ch3 : out std_logic_vector (15 downto 0); + rx_k_ch3 : out std_logic_vector (1 downto 0); + rx_disp_err_ch3 : out std_logic_vector (1 downto 0); + rx_cv_err_ch3 : out std_logic_vector (1 downto 0); + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + refclk2fpga : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component serdes_onboard_full_125 is + GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_125.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (15 downto 0); + tx_k_ch2 : in std_logic_vector (1 downto 0); + tx_force_disp_ch2 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); + rxdata_ch2 : out std_logic_vector (15 downto 0); + rx_k_ch2 : out std_logic_vector (1 downto 0); + rx_disp_err_ch2 : out std_logic_vector (1 downto 0); + rx_cv_err_ch2 : out std_logic_vector (1 downto 0); + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (15 downto 0); + tx_k_ch3 : in std_logic_vector (1 downto 0); + tx_force_disp_ch3 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); + rxdata_ch3 : out std_logic_vector (15 downto 0); + rx_k_ch3 : out std_logic_vector (1 downto 0); + rx_disp_err_ch3 : out std_logic_vector (1 downto 0); + rx_cv_err_ch3 : out std_logic_vector (1 downto 0); + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + refclk2fpga : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component serdes_onboard_full_ctc is + GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_ctc.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + ctc_urun_ch0_s : out std_logic; + ctc_orun_ch0_s : out std_logic; + ctc_ins_ch0_s : out std_logic; + ctc_del_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + ctc_urun_ch1_s : out std_logic; + ctc_orun_ch1_s : out std_logic; + ctc_ins_ch1_s : out std_logic; + ctc_del_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (15 downto 0); + tx_k_ch2 : in std_logic_vector (1 downto 0); + tx_force_disp_ch2 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); + rxdata_ch2 : out std_logic_vector (15 downto 0); + rx_k_ch2 : out std_logic_vector (1 downto 0); + rx_disp_err_ch2 : out std_logic_vector (1 downto 0); + rx_cv_err_ch2 : out std_logic_vector (1 downto 0); + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + ctc_urun_ch2_s : out std_logic; + ctc_orun_ch2_s : out std_logic; + ctc_ins_ch2_s : out std_logic; + ctc_del_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (15 downto 0); + tx_k_ch3 : in std_logic_vector (1 downto 0); + tx_force_disp_ch3 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); + rxdata_ch3 : out std_logic_vector (15 downto 0); + rx_k_ch3 : out std_logic_vector (1 downto 0); + rx_disp_err_ch3 : out std_logic_vector (1 downto 0); + rx_cv_err_ch3 : out std_logic_vector (1 downto 0); + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + ctc_urun_ch3_s : out std_logic; + ctc_orun_ch3_s : out std_logic; + ctc_ins_ch3_s : out std_logic; + ctc_del_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + refclk2fpga : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component serdes_sync_0 is + GENERIC (USER_CONFIG_FILE : String := "serdes_sync_0.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + tx_force_disp_ch0 : in std_logic; + tx_disp_sel_ch0 : in std_logic; + rxdata_ch0 : out std_logic_vector (7 downto 0); + rx_k_ch0 : out std_logic; + rx_disp_err_ch0 : out std_logic; + rx_cv_err_ch0 : out std_logic; + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component serdes_sync_125_0 is + GENERIC (USER_CONFIG_FILE : String := "serdes_sync_125_0.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + tx_force_disp_ch0 : in std_logic; + tx_disp_sel_ch0 : in std_logic; + rxdata_ch0 : out std_logic_vector (7 downto 0); + rx_k_ch0 : out std_logic; + rx_disp_err_ch0 : out std_logic; + rx_cv_err_ch0 : out std_logic; + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component sfp_0_200_ctc is + GENERIC (USER_CONFIG_FILE : String := "sfp_0_200_ctc.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + ctc_urun_ch0_s : out std_logic; + ctc_orun_ch0_s : out std_logic; + ctc_ins_ch0_s : out std_logic; + ctc_del_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component sfp_0_200_int is + generic (USER_CONFIG_FILE : String := "sfp_0_200_int.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component sfp_1_125_int is + GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt"); + port ( +------------------ +-- CH0 -- +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component sfp_1_200_int is + GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt"); + port ( +------------------ +-- CH0 -- +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + + +component sfp_ctc_0_200_int is + GENERIC (USER_CONFIG_FILE : String := "sfp_ctc_0_200_int.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + ctc_urun_ch0_s : out std_logic; + ctc_orun_ch0_s : out std_logic; + ctc_ins_ch0_s : out std_logic; + ctc_del_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + +component trigger_clock_manager is + port ( + TRB_CLK_IN : in std_logic; + INT_CLK_IN : in std_logic; -- dont care which clock, but not faster than TRB_CLK_IN + + RESET_IN : in std_logic; + + -- only single register, so no address + REGIO_ADDRESS_IN : in std_logic_vector( 1 downto 0); + REGIO_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_UNKNOWN_ADDRESS_OUT : out std_logic; + + + RESET_OUT : out std_logic; + TC_SELECT_OUT : out std_logic_vector(31 downto 0) + ); +end component; + +end package; diff --git a/base/trb3_components_1-6-x.vhd b/base/trb3_components_1-6-x.vhd deleted file mode 100644 index 03601f7..0000000 --- a/base/trb3_components_1-6-x.vhd +++ /dev/null @@ -1,1929 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.trb_net_std.all; - -package trb3_components is - - type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0); - type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0); - type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0); - type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0); - type std_logic_vector_array_8 is array (integer range <>) of std_logic_vector(7 downto 0); - type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0); - - component oddr is - port ( - clk : in std_logic; - clkout : out std_logic; - da : in std_logic_vector(0 downto 0); - db : in std_logic_vector(0 downto 0); - q : out std_logic_vector(0 downto 0)); - end component; - - component pll_in125_out125 - port ( - CLK : in std_logic; - CLKOP : out std_logic; --125 MHz - CLKOK : out std_logic; --125 MHz, bypass - LOCK : out std_logic - ); - end component; - - component pll_in125_out20 is - port ( - CLK : in std_logic; - CLKOP : out std_logic; -- 20 MHz - CLKOK : out std_logic; -- 125 MHz, bypass - LOCK : out std_logic); - end component pll_in125_out20; - - component OSCF -- internal oscillator with a frequency of 2MHz - port (OSC : out - std_logic); - end component; - - component TDC is - generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 31; - CONTROL_REG_NR : integer range 0 to 6; - TDC_VERSION : std_logic_vector(11 downto 0); - DEBUG : integer range 0 to 1 := c_YES; - SIMULATION : integer range 0 to 1 := c_NO); - port ( - RESET : in std_logic; - CLK_TDC : in std_logic; - CLK_READOUT : in std_logic; - REFERENCE_TIME : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); - HIT_CALIBRATION : in std_logic; - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); - TRG_DATA_VALID_IN : in std_logic := '0'; - VALID_TIMING_TRG_IN : in std_logic := '0'; - VALID_NOTIMING_TRG_IN : in std_logic := '0'; - INVALID_TRG_IN : in std_logic := '0'; - TMGTRG_TIMEOUT_IN : in std_logic := '0'; - SPIKE_DETECTED_IN : in std_logic := '0'; - MULTI_TMG_TRG_IN : in std_logic := '0'; - SPURIOUS_TRG_IN : in std_logic := '0'; - TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); - TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); - TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); - TRG_RELEASE_OUT : out std_logic; - TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_WRITE_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; - HCB_READ_EN_IN : in std_logic; - HCB_WRITE_EN_IN : in std_logic; - HCB_ADDR_IN : in std_logic_vector(6 downto 0); - HCB_DATA_OUT : out std_logic_vector(31 downto 0); - HCB_DATAREADY_OUT : out std_logic; - HCB_UNKNOWN_ADDR_OUT : out std_logic; - SRB_READ_EN_IN : in std_logic; - SRB_WRITE_EN_IN : in std_logic; - SRB_ADDR_IN : in std_logic_vector(6 downto 0); - SRB_DATA_OUT : out std_logic_vector(31 downto 0); - SRB_DATAREADY_OUT : out std_logic; - SRB_UNKNOWN_ADDR_OUT : out std_logic; - CDB_READ_EN_IN : in std_logic; - CDB_WRITE_EN_IN : in std_logic; - CDB_ADDR_IN : in std_logic_vector(6 downto 0); - CDB_DATA_OUT : out std_logic_vector(31 downto 0); - CDB_DATAREADY_OUT : out std_logic; - CDB_UNKNOWN_ADDR_OUT : out std_logic; - ESB_READ_EN_IN : in std_logic; - ESB_WRITE_EN_IN : in std_logic; - ESB_ADDR_IN : in std_logic_vector(6 downto 0); - ESB_DATA_OUT : out std_logic_vector(31 downto 0); - ESB_DATAREADY_OUT : out std_logic; - ESB_UNKNOWN_ADDR_OUT : out std_logic; - EFB_READ_EN_IN : in std_logic; - EFB_WRITE_EN_IN : in std_logic; - EFB_ADDR_IN : in std_logic_vector(6 downto 0); - EFB_DATA_OUT : out std_logic_vector(31 downto 0); - EFB_DATAREADY_OUT : out std_logic; - EFB_UNKNOWN_ADDR_OUT : out std_logic; - FWB_READ_EN_IN : in std_logic; -- not used after version 1.3 - FWB_WRITE_EN_IN : in std_logic; -- not used after version 1.3 - FWB_ADDR_IN : in std_logic_vector(6 downto 0); -- not used after version 1.3 - FWB_DATA_OUT : out std_logic_vector(31 downto 0); -- not used after version 1.3 - FWB_DATAREADY_OUT : out std_logic; -- not used after version 1.3 - FWB_UNKNOWN_ADDR_OUT : out std_logic; -- not used after version 1.3 - LHB_READ_EN_IN : in std_logic; - LHB_WRITE_EN_IN : in std_logic; - LHB_ADDR_IN : in std_logic_vector(6 downto 0); - LHB_DATA_OUT : out std_logic_vector(31 downto 0); - LHB_DATAREADY_OUT : out std_logic; - LHB_UNKNOWN_ADDR_OUT : out std_logic; - LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); - CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0)); - end component TDC; - - component Reference_Channel - generic ( - CHANNEL_ID : integer range 0 to 0); - port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_WCNT_OUT : out unsigned(7 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; - TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); - REF_DEBUG_OUT : out std_logic_vector(31 downto 0)); - end component; - - component Reference_Channel_200 - generic ( - CHANNEL_ID : integer range 0 to 0); - port ( - CLK_200 : in std_logic; - RESET_200 : in std_logic; - CLK_100 : in std_logic; - RESET_100 : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_WCNT_OUT : out unsigned(7 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); - end component; - - component Channel - generic ( - CHANNEL_ID : integer range 0 to 64; - DEBUG : integer range 0 to 1; - SIMULATION : integer range 0 to 1; - REFERENCE : integer range 0 to 1); - port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; - HIT_IN : in std_logic; - TRIGGER_WIN_END_TDC : in std_logic; - TRIGGER_WIN_END_RDO : in std_logic; - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_DATA_VALID_OUT : out std_logic; - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_EMPTY_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - EPOCH_WRITE_EN_IN : in std_logic; - LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); - ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); - ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); - FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); - Channel_200_DEBUG : out std_logic_vector(31 downto 0); - Channel_DEBUG : out std_logic_vector(31 downto 0)); - end component; - - component Channel_200 - generic ( - CHANNEL_ID : integer range 0 to 64; - DEBUG : integer range 0 to 1; - SIMULATION : integer range 0 to 1; - REFERENCE : integer range 0 to 1); - port ( - CLK_200 : in std_logic; - RESET_200 : in std_logic; - CLK_100 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; - HIT_IN : in std_logic; - TRIGGER_WIN_END_TDC : in std_logic; - TRIGGER_WIN_END_RDO : in std_logic; - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_DATA_VALID_OUT : out std_logic; - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - EPOCH_WRITE_EN_IN : in std_logic; - ENCODER_START_OUT : out std_logic; - ENCODER_FINISHED_OUT : out std_logic; - FIFO_WRITE_OUT : out std_logic; - Channel_200_DEBUG : out std_logic_vector(31 downto 0)); - end component; - - component Readout is - generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 31; - TDC_VERSION : std_logic_vector(11 downto 0)); - port ( - RESET_100 : in std_logic; - RESET_200 : in std_logic; - RESET_COUNTERS : in std_logic; - CLK_100 : in std_logic; - CLK_200 : in std_logic; - TRIGGER_RDO_IN : in std_logic; - TRIGGER_TDC_IN : in std_logic; - CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); - CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); - DATA_LIMIT_IN : in unsigned(7 downto 0); - TRG_RELEASE_OUT : out std_logic; - TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_WRITE_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; - READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); - TRIGGER_WIN_EN_IN : in std_logic; - TRIG_WIN_END_TDC_IN : in std_logic; - TRIG_WIN_END_RDO_IN : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - DEBUG_MODE_EN_IN : in std_logic; - STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to STATUS_REG_NR-1); - READOUT_DEBUG : out std_logic_vector(31 downto 0); --- ports not used after tdc_v1.5.2 - TRIGGER_WIN_END_OUT : out std_logic; - CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); - REFERENCE_TIME : in std_logic; - TRIGGER_TIME_IN : in std_logic_vector(38 downto 0) - ); - end component Readout; - - - component TriggerHandler is - generic ( - TRIGGER_NUM : integer; - PHYSICAL_EVENT_TRG_NUM : integer); - port ( - CLK_TRG : in std_logic; - CLK_RDO : in std_logic; - CLK_TDC : in std_logic; - RESET_TRG : in std_logic; - RESET_RDO : in std_logic; - RESET_TDC : in std_logic; - TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); - TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); - TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); - TRIGGER_WIN_EN_IN : in std_logic; - TRIGGER_WIN_POST_IN : in unsigned(10 downto 0); - TRIGGER_WIN_END_RDO_OUT : out std_logic; - TRIGGER_WIN_END_TDC_OUT : out std_logic); - end component TriggerHandler; - - component LogicAnalyser - generic ( - CHANNEL_NUMBER : integer range 2 to 65); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_IN : in std_logic_vector(3*32-1 downto 0); - CONTROL_IN : in std_logic_vector(3 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0)); - end component; - - component BusHandler - generic ( - BUS_LENGTH : integer range 0 to 64 := 2); - port ( - RESET : in std_logic; - CLK : in std_logic; - DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); - READ_EN_IN : in std_logic; - WRITE_EN_IN : in std_logic; - ADDR_IN : in std_logic_vector(6 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATAREADY_OUT : out std_logic; - UNKNOWN_ADDR_OUT : out std_logic); - end component; - - component ROM_FIFO - port ( - Address : in std_logic_vector(7 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(3 downto 0)); - end component; - - component up_counter - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic); - end component; - - component Adder_304 - port ( - CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0)); - end component; - - component Encoder_304_Bit is - port ( - RESET : in std_logic; - CLK : in std_logic; - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - end component Encoder_304_Bit; - - --component Encoder_304_Bit - -- port ( - -- RESET : in std_logic; - -- CLK : in std_logic; - -- START_IN : in std_logic; - -- THERMOCODE_IN : in std_logic_vector(303 downto 0); - -- FINISHED_OUT : out std_logic; - -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - -- ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - --end component; - - component hit_mux is - port ( - CH_EN_IN : in std_logic; - CALIBRATION_EN_IN : in std_logic; - HIT_CALIBRATION_IN : in std_logic; - HIT_PHYSICAL_IN : in std_logic; - HIT_OUT : out std_logic); - end component hit_mux; - - component FIFO_32x32_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_36x128_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x128_OutReg; - - component FIFO_36x64_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic); - end component; - - component FIFO_36x32_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x32_OutReg; - - component FIFO_36x16_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic); - end component; - - component FIFO_DC_36x128_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component FIFO_DC_36x128_OutReg; - - component FIFO_DC_36x64_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component FIFO_DC_36x64_OutReg; - - component FIFO_DC_36x32_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_DC_36x16_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_36x128_OutReg_Counter is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - WCNT : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x128_OutReg_Counter; - --- component FIFO_DC_36x32_OutReg is --- port ( --- Data : in std_logic_vector(35 downto 0); --- WrClock : in std_logic; --- RdClock : in std_logic; --- WrEn : in std_logic; --- RdEn : in std_logic; --- Reset : in std_logic; --- RPReset : in std_logic; --- Q : out std_logic_vector(35 downto 0); --- Empty : out std_logic; --- Full : out std_logic; --- AlmostFull : out std_logic); --- end component; --- --- component FIFO_DC_36x16_OutReg is --- port ( --- Data : in std_logic_vector(35 downto 0); --- WrClock : in std_logic; --- RdClock : in std_logic; --- WrEn : in std_logic; --- RdEn : in std_logic; --- Reset : in std_logic; --- RPReset : in std_logic; --- Q : out std_logic_vector(35 downto 0); --- Empty : out std_logic; --- Full : out std_logic; --- AlmostFull : out std_logic); --- end component; - - --component FIFO_24x2_OutReg - -- port ( - -- Data : in std_logic_vector(23 downto 0); - -- WrClock : in std_logic; - -- RdClock : in std_logic; - -- WrEn : in std_logic; - -- RdEn : in std_logic; - -- Reset : in std_logic; - -- RPReset : in std_logic; - -- Q : out std_logic_vector(23 downto 0); - -- Empty : out std_logic; - -- Full : out std_logic); - --end component; - - component ROM_Encoder - port ( - Address : in std_logic_vector(9 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0)); - end component; - - component ROM4_Encoder is - port ( - Address : in std_logic_vector(9 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0)); - end component ROM4_Encoder; - - component bit_sync - generic ( - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - component risingEdgeDetect is - port ( - CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component risingEdgeDetect; - - component fallingEdgeDetect is - port ( - CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component fallingEdgeDetect; - - component ShiftRegisterSISO - generic ( - DEPTH : integer range 1 to 32; - WIDTH : integer range 1 to 32); - port ( - CLK : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0)); - end component; - - component Stretcher - port ( - PULSE_IN : in std_logic; - PULSE_OUT : out std_logic); - end component; - - component WaveLauncher is - port ( - HIT_IN : in std_logic; - HIT_OUT : out std_logic); - end component WaveLauncher; - - component adc_ad9222 - generic( - CHANNELS : integer range 4 to 4 := 4; - DEVICES : integer range 2 to 2 := 2; - RESOLUTION : integer range 12 to 12 := 12 - ); - port( - CLK : in std_logic; - CLK_ADCREF : in std_logic; - CLK_ADCDAT : in std_logic; - RESTART_IN : in std_logic; - ADCCLK_OUT : out std_logic; - ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0); - ADC_DCO : in std_logic_vector(DEVICES-1 downto 0); - ADC_FCO : in std_logic_vector(DEVICES-1 downto 0); - - DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); - FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0); - DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0); - DEBUG : out std_logic_vector(31 downto 0) - - ); - end component; - - component fifo_32x512 - port ( - Data : in std_logic_vector(31 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - component dqsinput - port ( - clk_0 : in std_logic; - clk_1 : in std_logic; - clkdiv_reset : in std_logic; - eclk : in std_logic; - reset_0 : in std_logic; - reset_1 : in std_logic; - sclk : out std_logic; - datain_0 : in std_logic_vector(4 downto 0); - datain_1 : in std_logic_vector(4 downto 0); - q_0 : out std_logic_vector(19 downto 0); - q_1 : out std_logic_vector(19 downto 0) - ); - end component; - - component fifo_cdt_200 - port ( - Data : in std_logic_vector(59 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(59 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - - component med_ecp3_sfp_sync is - generic( - SERDES_NUM : integer range 0 to 3 := 0; --- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO - IS_SYNC_SLAVE : integer := 0 --select slave mode - ); - port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - --Internal Connection TX - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic := '0'; - --Internal Connection RX - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); - MED_DATAREADY_OUT : out std_logic := '0'; - MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - - --Sync operation - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; --not used - SD_REFCLK_N_IN : in std_logic; --not used - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable - --Control Interface - SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); - SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); - SCI_READ : in std_logic := '0'; - SCI_WRITE : in std_logic := '0'; - SCI_ACK : out std_logic := '0'; - SCI_NACK : out std_logic := '0'; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); - end component; - - - component input_to_trigger_logic is - generic( - INPUTS : integer range 1 to 32 := 24; - OUTPUTS : integer range 1 to 16 := 4 - ); - port( - CLK : in std_logic; - - INPUT : in std_logic_vector(INPUTS-1 downto 0); - OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0); - - DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_IN : in std_logic := '0'; - READ_IN : in std_logic := '0'; - ACK_OUT : out std_logic; - NACK_OUT : out std_logic; - ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') - - ); - end component; - - component input_statistics is - generic ( - INPUTS : integer range 1 to 32); - port ( - CLK : in std_logic; - INPUT : in std_logic_vector(INPUTS-1 downto 0); - DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_IN : in std_logic := '0'; - READ_IN : in std_logic := '0'; - ACK_OUT : out std_logic; - NACK_OUT : out std_logic; - ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0')); - end component input_statistics; - - -component serdes_full_ctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_full_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - ctc_urun_ch1_s : out std_logic; - ctc_orun_ch1_s : out std_logic; - ctc_ins_ch1_s : out std_logic; - ctc_del_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - ctc_urun_ch2_s : out std_logic; - ctc_orun_ch2_s : out std_logic; - ctc_ins_ch2_s : out std_logic; - ctc_del_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - ctc_urun_ch3_s : out std_logic; - ctc_orun_ch3_s : out std_logic; - ctc_ins_ch3_s : out std_logic; - ctc_del_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component serdes_full_noctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_full_noctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full_125 is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_125.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full_ctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - ctc_urun_ch1_s : out std_logic; - ctc_orun_ch1_s : out std_logic; - ctc_ins_ch1_s : out std_logic; - ctc_del_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - ctc_urun_ch2_s : out std_logic; - ctc_orun_ch2_s : out std_logic; - ctc_ins_ch2_s : out std_logic; - ctc_del_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - ctc_urun_ch3_s : out std_logic; - ctc_orun_ch3_s : out std_logic; - ctc_ins_ch3_s : out std_logic; - ctc_del_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_sync_0 is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_0.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_sync_125_0 is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_125_0.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_0_200_ctc is - GENERIC (USER_CONFIG_FILE : String := "sfp_0_200_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_0_200_int is - generic (USER_CONFIG_FILE : String := "sfp_0_200_int.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_1_125_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_1_200_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_ctc_0_200_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_ctc_0_200_int.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component trigger_clock_manager is - port ( - TRB_CLK_IN : in std_logic; - INT_CLK_IN : in std_logic; -- dont care which clock, but not faster than TRB_CLK_IN - - RESET_IN : in std_logic; - - -- only single register, so no address - REGIO_ADDRESS_IN : in std_logic_vector( 1 downto 0); - REGIO_DATA_IN : in std_logic_vector(31 downto 0); - REGIO_READ_ENABLE_IN : in std_logic; - REGIO_WRITE_ENABLE_IN : in std_logic; - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); - REGIO_DATAREADY_OUT : out std_logic; - REGIO_WRITE_ACK_OUT : out std_logic; - REGIO_UNKNOWN_ADDRESS_OUT : out std_logic; - - - RESET_OUT : out std_logic; - TC_SELECT_OUT : out std_logic_vector(31 downto 0) - ); -end component; - -end package; diff --git a/base/trb3_components_1-7-x.vhd b/base/trb3_components_1-7-x.vhd deleted file mode 100644 index a24ba42..0000000 --- a/base/trb3_components_1-7-x.vhd +++ /dev/null @@ -1,1490 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.trb_net_std.all; - -package trb3_components is - - type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0); - type unsigned_array_5 is array (integer range <>) of unsigned(4 downto 0); - - component oddr is - port ( - clk : in std_logic; - clkout : out std_logic; - da : in std_logic_vector(0 downto 0); - db : in std_logic_vector(0 downto 0); - q : out std_logic_vector(0 downto 0)); - end component; - - component pll_in125_out125 - port ( - CLK : in std_logic; - CLKOP : out std_logic; --125 MHz - CLKOK : out std_logic; --125 MHz, bypass - LOCK : out std_logic - ); - end component; - - component pll_in125_out20 is - port ( - CLK : in std_logic; - CLKOP : out std_logic; -- 20 MHz - CLKOK : out std_logic; -- 125 MHz, bypass - LOCK : out std_logic); - end component pll_in125_out20; - - component OSCF -- internal oscillator with a frequency of 2MHz - port (OSC : out - std_logic); - end component; - - component FIFO_32x32_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_36x128_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x128_OutReg; - - component FIFO_36x64_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - component FIFO_36x32_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x32_OutReg; - - component FIFO_36x16_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - component FIFO_DC_36x128_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component FIFO_DC_36x128_OutReg; - - component FIFO_DC_36x64_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component FIFO_DC_36x64_OutReg; - - component FIFO_DC_36x32_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_DC_36x16_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_36x128_OutReg_Counter is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - WCNT : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component FIFO_36x128_OutReg_Counter; - - component bit_sync - generic ( - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - component risingEdgeDetect is - port ( - CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component risingEdgeDetect; - - component fallingEdgeDetect is - port ( - CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component fallingEdgeDetect; - - component ShiftRegisterSISO - generic ( - DEPTH : integer range 1 to 32; - WIDTH : integer range 1 to 32); - port ( - CLK : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0)); - end component; - - component Stretcher - port ( - PULSE_IN : in std_logic; - PULSE_OUT : out std_logic); - end component; - - component WaveLauncher is - port ( - HIT_IN : in std_logic; - HIT_OUT : out std_logic); - end component WaveLauncher; - - component adc_ad9222 - generic( - CHANNELS : integer range 4 to 4 := 4; - DEVICES : integer range 2 to 2 := 2; - RESOLUTION : integer range 12 to 12 := 12 - ); - port( - CLK : in std_logic; - CLK_ADCREF : in std_logic; - CLK_ADCDAT : in std_logic; - RESTART_IN : in std_logic; - ADCCLK_OUT : out std_logic; - ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0); - ADC_DCO : in std_logic_vector(DEVICES-1 downto 0); - ADC_FCO : in std_logic_vector(DEVICES-1 downto 0); - - DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); - FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0); - DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0); - DEBUG : out std_logic_vector(31 downto 0) - - ); - end component; - - component fifo_32x512 - port ( - Data : in std_logic_vector(31 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - component dqsinput - port ( - clk_0 : in std_logic; - clk_1 : in std_logic; - clkdiv_reset : in std_logic; - eclk : in std_logic; - reset_0 : in std_logic; - reset_1 : in std_logic; - sclk : out std_logic; - datain_0 : in std_logic_vector(4 downto 0); - datain_1 : in std_logic_vector(4 downto 0); - q_0 : out std_logic_vector(19 downto 0); - q_1 : out std_logic_vector(19 downto 0) - ); - end component; - - component fifo_cdt_200 - port ( - Data : in std_logic_vector(59 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(59 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; - - - component med_ecp3_sfp_sync is - generic( - SERDES_NUM : integer range 0 to 3 := 0; --- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO - IS_SYNC_SLAVE : integer := 0 --select slave mode - ); - port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - --Internal Connection TX - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic := '0'; - --Internal Connection RX - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); - MED_DATAREADY_OUT : out std_logic := '0'; - MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - - --Sync operation - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; --not used - SD_REFCLK_N_IN : in std_logic; --not used - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable - --Control Interface - SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); - SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); - SCI_READ : in std_logic := '0'; - SCI_WRITE : in std_logic := '0'; - SCI_ACK : out std_logic := '0'; - SCI_NACK : out std_logic := '0'; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); - end component; - - - component input_to_trigger_logic is - generic( - INPUTS : integer range 1 to 32 := 24; - OUTPUTS : integer range 1 to 16 := 4 - ); - port( - CLK : in std_logic; - - INPUT : in std_logic_vector(INPUTS-1 downto 0); - OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0); - - DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_IN : in std_logic := '0'; - READ_IN : in std_logic := '0'; - ACK_OUT : out std_logic; - NACK_OUT : out std_logic; - ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') - - ); - end component; - - component input_statistics is - generic ( - INPUTS : integer range 1 to 32); - port ( - CLK : in std_logic; - INPUT : in std_logic_vector(INPUTS-1 downto 0); - DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_IN : in std_logic := '0'; - READ_IN : in std_logic := '0'; - ACK_OUT : out std_logic; - NACK_OUT : out std_logic; - ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0')); - end component input_statistics; - - -component serdes_full_ctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_full_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - ctc_urun_ch1_s : out std_logic; - ctc_orun_ch1_s : out std_logic; - ctc_ins_ch1_s : out std_logic; - ctc_del_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - ctc_urun_ch2_s : out std_logic; - ctc_orun_ch2_s : out std_logic; - ctc_ins_ch2_s : out std_logic; - ctc_del_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - ctc_urun_ch3_s : out std_logic; - ctc_orun_ch3_s : out std_logic; - ctc_ins_ch3_s : out std_logic; - ctc_del_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component serdes_full_noctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_full_noctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full_125 is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_125.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_onboard_full_ctc is - GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - ctc_urun_ch1_s : out std_logic; - ctc_orun_ch1_s : out std_logic; - ctc_ins_ch1_s : out std_logic; - ctc_del_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- - hdinp_ch2, hdinn_ch2 : in std_logic; - hdoutp_ch2, hdoutn_ch2 : out std_logic; - sci_sel_ch2 : in std_logic; - rxiclk_ch2 : in std_logic; - txiclk_ch2 : in std_logic; - rx_full_clk_ch2 : out std_logic; - rx_half_clk_ch2 : out std_logic; - tx_full_clk_ch2 : out std_logic; - tx_half_clk_ch2 : out std_logic; - fpga_rxrefclk_ch2 : in std_logic; - txdata_ch2 : in std_logic_vector (15 downto 0); - tx_k_ch2 : in std_logic_vector (1 downto 0); - tx_force_disp_ch2 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch2 : in std_logic_vector (1 downto 0); - rxdata_ch2 : out std_logic_vector (15 downto 0); - rx_k_ch2 : out std_logic_vector (1 downto 0); - rx_disp_err_ch2 : out std_logic_vector (1 downto 0); - rx_cv_err_ch2 : out std_logic_vector (1 downto 0); - sb_felb_ch2_c : in std_logic; - sb_felb_rst_ch2_c : in std_logic; - tx_pwrup_ch2_c : in std_logic; - rx_pwrup_ch2_c : in std_logic; - rx_los_low_ch2_s : out std_logic; - lsm_status_ch2_s : out std_logic; - ctc_urun_ch2_s : out std_logic; - ctc_orun_ch2_s : out std_logic; - ctc_ins_ch2_s : out std_logic; - ctc_del_ch2_s : out std_logic; - rx_cdr_lol_ch2_s : out std_logic; - tx_div2_mode_ch2_c : in std_logic; - rx_div2_mode_ch2_c : in std_logic; --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (15 downto 0); - tx_k_ch3 : in std_logic_vector (1 downto 0); - tx_force_disp_ch3 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch3 : in std_logic_vector (1 downto 0); - rxdata_ch3 : out std_logic_vector (15 downto 0); - rx_k_ch3 : out std_logic_vector (1 downto 0); - rx_disp_err_ch3 : out std_logic_vector (1 downto 0); - rx_cv_err_ch3 : out std_logic_vector (1 downto 0); - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - ctc_urun_ch3_s : out std_logic; - ctc_orun_ch3_s : out std_logic; - ctc_ins_ch3_s : out std_logic; - ctc_del_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_sync_0 is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_0.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component serdes_sync_125_0 is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_125_0.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_0_200_ctc is - GENERIC (USER_CONFIG_FILE : String := "sfp_0_200_ctc.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_0_200_int is - generic (USER_CONFIG_FILE : String := "sfp_0_200_int.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_1_125_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_1_200_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- - hdinp_ch1, hdinn_ch1 : in std_logic; - hdoutp_ch1, hdoutn_ch1 : out std_logic; - sci_sel_ch1 : in std_logic; - rxiclk_ch1 : in std_logic; - txiclk_ch1 : in std_logic; - rx_full_clk_ch1 : out std_logic; - rx_half_clk_ch1 : out std_logic; - tx_full_clk_ch1 : out std_logic; - tx_half_clk_ch1 : out std_logic; - fpga_rxrefclk_ch1 : in std_logic; - txdata_ch1 : in std_logic_vector (15 downto 0); - tx_k_ch1 : in std_logic_vector (1 downto 0); - tx_force_disp_ch1 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); - rxdata_ch1 : out std_logic_vector (15 downto 0); - rx_k_ch1 : out std_logic_vector (1 downto 0); - rx_disp_err_ch1 : out std_logic_vector (1 downto 0); - rx_cv_err_ch1 : out std_logic_vector (1 downto 0); - sb_felb_ch1_c : in std_logic; - sb_felb_rst_ch1_c : in std_logic; - tx_pwrup_ch1_c : in std_logic; - rx_pwrup_ch1_c : in std_logic; - rx_los_low_ch1_s : out std_logic; - lsm_status_ch1_s : out std_logic; - rx_cdr_lol_ch1_s : out std_logic; - tx_div2_mode_ch1_c : in std_logic; - rx_div2_mode_ch1_c : in std_logic; --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - - -component sfp_ctc_0_200_int is - GENERIC (USER_CONFIG_FILE : String := "sfp_ctc_0_200_int.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - ctc_urun_ch0_s : out std_logic; - ctc_orun_ch0_s : out std_logic; - ctc_ins_ch0_s : out std_logic; - ctc_del_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component trigger_clock_manager is - port ( - TRB_CLK_IN : in std_logic; - INT_CLK_IN : in std_logic; -- dont care which clock, but not faster than TRB_CLK_IN - - RESET_IN : in std_logic; - - -- only single register, so no address - REGIO_ADDRESS_IN : in std_logic_vector( 1 downto 0); - REGIO_DATA_IN : in std_logic_vector(31 downto 0); - REGIO_READ_ENABLE_IN : in std_logic; - REGIO_WRITE_ENABLE_IN : in std_logic; - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); - REGIO_DATAREADY_OUT : out std_logic; - REGIO_WRITE_ACK_OUT : out std_logic; - REGIO_UNKNOWN_ADDRESS_OUT : out std_logic; - - RESET_OUT : out std_logic; - TC_SELECT_OUT : out std_logic_vector(31 downto 0) - ); -end component; -end package; diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd deleted file mode 120000 index fa658ea..0000000 --- a/wasa/trb3_periph_padiwa.vhd +++ /dev/null @@ -1 +0,0 @@ -trb3_periph_padiwa.vhd.1.6.xx \ No newline at end of file diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd new file mode 100644 index 0000000..8ca8b77 --- /dev/null +++ b/wasa/trb3_periph_padiwa.vhd @@ -0,0 +1,1026 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.config.all; +use work.tdc_version.all; +use work.version.all; + + +entity trb3_periph_padiwa is + generic( + SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. + ); + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 6 + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Manager 3 + CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1 + --CLK_PCLK_RIGHT is the only clock with external termination !? + CLK_EXTERNAL : in std_logic; --Clock Manager 9 + + +-- --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out +-- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + + --Serdes + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used + SERDES_TX : out std_logic_vector(3 downto 2); + SERDES_RX : in std_logic_vector(3 downto 2); + + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + + + --Connections + SPARE_LINE : inout std_logic_vector(3 downto 0); + INP : in std_logic_vector(63 downto 0); + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --DAC + OUT_SDO : out std_logic_vector(4 downto 1); + IN_SDI : in std_logic_vector(4 downto 1); + OUT_SCK : out std_logic_vector(4 downto 1); + OUT_CS : out std_logic_vector(4 downto 1); + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of OUT_SCK : signal is true; + attribute syn_useioff of OUT_CS : signal is true; + attribute syn_useioff of OUT_SDO : signal is true; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + + +end entity; + +architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 2; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + signal clk_100_internal : std_logic; + signal clk_200_internal : std_logic; + signal rx_clock_100 : std_logic; + signal rx_clock_200 : std_logic; + signal clk_tdc : std_logic; + signal time_counter, time_counter2 : unsigned(31 downto 0); + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal dac_read_en : std_logic; + signal dac_write_en : std_logic; + signal dac_data_in : std_logic_vector(31 downto 0); + signal dac_addr : std_logic_vector(4 downto 0); + signal dac_data_out : std_logic_vector(31 downto 0); + signal dac_ack : std_logic; + signal dac_busy : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_data_in : std_logic_vector(31 downto 0); + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_data_in : std_logic_vector(31 downto 0); + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal cdb_read_en : std_logic; + signal cdb_write_en : std_logic; + signal cdb_data_in : std_logic_vector(31 downto 0); + signal cdb_addr : std_logic_vector(6 downto 0); + signal cdb_data_out : std_logic_vector(31 downto 0); + signal cdb_data_ready : std_logic; + signal cdb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_data_in : std_logic_vector(31 downto 0); + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_data_in : std_logic_vector(31 downto 0); + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_data_in : std_logic_vector(31 downto 0); + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal sci1_ack : std_logic; + signal sci1_write : std_logic; + signal sci1_read : std_logic; + signal sci1_data_in : std_logic_vector(7 downto 0); + signal sci1_data_out : std_logic_vector(7 downto 0); + signal sci1_addr : std_logic_vector(8 downto 0); + + signal padiwa_cs : std_logic_vector(3 downto 0); + signal padiwa_sck : std_logic; + signal padiwa_sdi : std_logic; + signal padiwa_sdo : std_logic; + + signal trig_out : std_logic_vector(3 downto 0); + signal trig_din : std_logic_vector(31 downto 0); + signal trig_dout : std_logic_vector(31 downto 0); + signal trig_write : std_logic := '0'; + signal trig_read : std_logic := '0'; + signal trig_ack : std_logic := '0'; + signal trig_nack : std_logic := '0'; + signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal stat_out : std_logic_vector(3 downto 0); + signal stat_din : std_logic_vector(31 downto 0); + signal stat_dout : std_logic_vector(31 downto 0); + signal stat_write : std_logic := '0'; + signal stat_read : std_logic := '0'; + signal stat_ack : std_logic := '0'; + signal stat_nack : std_logic := '0'; + signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal sed_error : std_logic; + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal input_i : std_logic_vector(64 downto 1); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_internal, + CLKOK => clk_200_internal, + LOCK => pll_lock + ); + + -- internal oscillator with frequency of 2.5MHz for tdc calibration + OSCInst0 : OSCF + port map ( + OSC => osc_int); + + gen_sync_clocks : if SYNC_MODE = c_YES generate + clk_100_i <= rx_clock_100; + clk_200_i <= rx_clock_200; + clk_tdc <= rx_clock_200; + end generate; + + gen_local_clocks : if SYNC_MODE = c_NO generate + clk_100_i <= clk_100_internal; + clk_200_i <= clk_200_internal; + clk_tdc <= CLK_PCLK_LEFT; + end generate; + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_CTC => c_NO, + USE_SLAVE => SYNC_MODE + ) + port map( + CLK => clk_200_internal, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + CLK_RX_HALF_OUT => rx_clock_100, + CLK_RX_FULL_OUT => rx_clock_200, + + --SFP Connection + SD_RXD_P_IN => SERDES_RX(2), + SD_RXD_N_IN => SERDES_RX(3), + SD_TXD_P_OUT => SERDES_TX(2), + SD_TXD_N_OUT => SERDES_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + + SCI_DATA_IN => sci1_data_in, + SCI_DATA_OUT => sci1_data_out, + SCI_ADDR => sci1_addr, + SCI_READ => sci1_read, + SCI_WRITE => sci1_write, + SCI_ACK => sci1_ack, + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, + REGIO_INIT_ADDRESS => INIT_ADDRESS, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 12, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**12-400, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + timing_trg_received_i <= TRIGGER_LEFT; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 11, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", + 5 => x"b000", 6 => x"c800", 7 => x"cf00", 8 => x"cf80", 9 => x"d500", + 10 => x"c200", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, + 5 => 9, 6 => 3, 7 => 6, 8 => 7, 9 => 4, + 10 => 7, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --DAC + BUS_READ_ENABLE_OUT(2) => dac_read_en, + BUS_WRITE_ENABLE_OUT(2) => dac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => dac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => dac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => dac_data_out, + BUS_DATAREADY_IN(2) => dac_ack, + BUS_WRITE_ACK_IN(2) => dac_ack, + BUS_NO_MORE_DATA_IN(2) => dac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + ----Encoder Start Registers + --BUS_READ_ENABLE_OUT(5) => esb_read_en, + --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + --BUS_DATA_OUT(5*32+31 downto 5*32) => open, + --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + --BUS_TIMEOUT_OUT(5) => open, + --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + --BUS_DATAREADY_IN(5) => esb_data_ready, + --BUS_WRITE_ACK_IN(5) => '0', + --BUS_NO_MORE_DATA_IN(5) => '0', + --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + ----Fifo Write Registers + --BUS_READ_ENABLE_OUT(6) => efb_read_en, + --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + --BUS_DATA_OUT(6*32+31 downto 6*32) => open, + --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + --BUS_TIMEOUT_OUT(6) => open, + --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + --BUS_DATAREADY_IN(6) => efb_data_ready, + --BUS_WRITE_ACK_IN(6) => '0', + --BUS_NO_MORE_DATA_IN(6) => '0', + --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + --SCI first Media Interface + BUS_READ_ENABLE_OUT(5) => sci1_read, + BUS_WRITE_ENABLE_OUT(5) => sci1_write, + BUS_DATA_OUT(5*32+7 downto 5*32) => sci1_data_in, + BUS_DATA_OUT(5*32+31 downto 5*32+8) => open, + BUS_ADDR_OUT(5*16+8 downto 5*16) => sci1_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+7 downto 5*32) => sci1_data_out, + BUS_DATAREADY_IN(5) => sci1_ack, + BUS_WRITE_ACK_IN(5) => sci1_ack, + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => '0', + --TDC config registers + BUS_READ_ENABLE_OUT(6) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(6) => tdc_ctrl_write, + BUS_DATA_OUT(6*32+31 downto 6*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(6*16+2 downto 6*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+3) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(6) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(6) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(7) => trig_read, + BUS_WRITE_ENABLE_OUT(7) => trig_write, + BUS_DATA_OUT(7*32+31 downto 7*32) => trig_din, + BUS_ADDR_OUT(7*16+15 downto 7*16) => trig_addr, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => trig_dout, + BUS_DATAREADY_IN(7) => trig_ack, + BUS_WRITE_ACK_IN(7) => trig_ack, + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => trig_nack, + --Input statistics + BUS_READ_ENABLE_OUT(8) => stat_read, + BUS_WRITE_ENABLE_OUT(8) => stat_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => stat_din, + BUS_ADDR_OUT(8*16+15 downto 8*16) => stat_addr, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => stat_dout, + BUS_DATAREADY_IN(8) => stat_ack, + BUS_WRITE_ACK_IN(8) => stat_ack, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => stat_nack, + --SEU Detection + BUS_READ_ENABLE_OUT(9) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(9) => bussed_rx.write, + BUS_DATA_OUT(9*32+31 downto 9*32) => bussed_rx.data, + BUS_ADDR_OUT(9*16+15 downto 9*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(9) => bussed_rx.timeout, + BUS_DATA_IN(9*32+31 downto 9*32) => bussed_tx.data, + BUS_DATAREADY_IN(9) => bussed_tx.ack, + BUS_WRITE_ACK_IN(9) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(9) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(9) => bussed_tx.unknown, + --Channel Debug Registers + BUS_READ_ENABLE_OUT(10) => cdb_read_en, + BUS_WRITE_ENABLE_OUT(10) => cdb_write_en, + BUS_DATA_OUT(10*32+31 downto 10*32) => open, + BUS_ADDR_OUT(10*16+6 downto 10*16) => cdb_addr, + BUS_ADDR_OUT(10*16+15 downto 10*16+7) => open, + BUS_TIMEOUT_OUT(10) => open, + BUS_DATA_IN(10*32+31 downto 10*32) => cdb_data_out, + BUS_DATAREADY_IN(10) => cdb_data_ready, + BUS_WRITE_ACK_IN(10) => '0', + BUS_NO_MORE_DATA_IN(10) => '0', + BUS_UNKNOWN_ADDR_IN(10) => cdb_invalid, + + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + +-- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +--------------------------------------------------------------------------- +-- DAC +--------------------------------------------------------------------------- + gen_SPI : if INCLUDE_SPI = 1 generate + THE_DAC_SPI : spi_ltc2600 + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => dac_addr, + BUS_READ_IN => dac_read_en, + BUS_WRITE_IN => dac_write_en, + BUS_ACK_OUT => dac_ack, + BUS_BUSY_OUT => dac_busy, + BUS_DATA_IN => dac_data_in, + BUS_DATA_OUT => dac_data_out, + -- SPI connections + SPI_CS_OUT(3 downto 0) => padiwa_cs, + SPI_SDI_IN => padiwa_sdi, + SPI_SDO_OUT => padiwa_sdo, + SPI_SCK_OUT => padiwa_sck + ); + OUT_CS <= padiwa_cs(3 downto 0); + OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck; + OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo; + padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); + end generate; + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- + gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => PHYSICAL_INPUTS, + OUTPUTS => 4 + ) + port map( + CLK => clk_100_i, + + INPUT => input_i(PHYSICAL_INPUTS downto 1), + OUTPUT => trig_out, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); + FPGA5_COMM(10 downto 7) <= trig_out; + end generate; + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- + gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => PHYSICAL_INPUTS + ) + port map( + CLK => clk_100_i, + + INPUT => input_i(PHYSICAL_INPUTS downto 1), + + DATA_IN => stat_din, + DATA_OUT => stat_dout, + WRITE_IN => stat_write, + READ_IN => stat_read, + ACK_OUT => stat_ack, + NACK_OUT => stat_nack, + ADDR_IN => stat_addr + ); + end generate; + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_ORANGE <= not reset_i when rising_edge(clk_100_internal); + LED_YELLOW <= '1'; + LED_GREEN <= not med_stat_op(9); + LED_RED <= not (med_stat_op(10) or med_stat_op(11)); + +--------------------------------------------------------------------------- +-- Test Connector +--------------------------------------------------------------------------- +-- TEST_LINE(15 downto 0) <= (others => '0'); +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_100_internal); + time_counter <= time_counter + 1; + end process; + + + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels + STATUS_REG_NR => 21, -- Number of status regs + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => TDC_VERSION, -- TDC version number + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_tdc, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Channel Debug Bus + CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe + CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe + CDB_ADDR_IN => cdb_addr, -- bus address + CDB_DATA_OUT => cdb_data_out, -- bus data + CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe + CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address + LHB_DATA_OUT => open, -- lhb_data_out, -- bus data + LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => TEST_LINE, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INP; + input_i <= INP; + end generate; + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + input_i(i) <= INP(i-1); + end generate Gen_Hit_In_Signals; + end generate; + + gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate + Gen_Hit_Fast_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i*2-2); + hit_in_i(i*2) <= not INP(i*2-2); + input_i(i) <= INP(i*2-2); + end generate; + end generate; + + +end architecture; diff --git a/wasa/trb3_periph_padiwa.vhd.1.6.xx b/wasa/trb3_periph_padiwa.vhd.1.6.xx deleted file mode 100644 index 98632b1..0000000 --- a/wasa/trb3_periph_padiwa.vhd.1.6.xx +++ /dev/null @@ -1,1045 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.config.all; -use work.tdc_version.all; -use work.version.all; - - -entity trb3_periph_padiwa is - generic( - SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. - ); - port( - --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 6 - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Manager 3 - CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1 - --CLK_PCLK_RIGHT is the only clock with external termination !? - CLK_EXTERNAL : in std_logic; --Clock Manager 9 - - --- --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out --- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - - --Serdes - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used - SERDES_TX : out std_logic_vector(3 downto 2); - SERDES_RX : in std_logic_vector(3 downto 2); - - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - - - --Connections - SPARE_LINE : inout std_logic_vector(3 downto 0); - INP : in std_logic_vector(63 downto 0); - - --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - - --DAC - OUT_SDO : out std_logic_vector(4 downto 1); - IN_SDI : in std_logic_vector(4 downto 1); - OUT_SCK : out std_logic_vector(4 downto 1); - OUT_CS : out std_logic_vector(4 downto 1); - --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - - - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of OUT_SCK : signal is true; - attribute syn_useioff of OUT_CS : signal is true; - attribute syn_useioff of OUT_SDO : signal is true; - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of INP : signal is false; - - -end entity; - -architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 2; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - signal clk_100_internal : std_logic; - signal clk_200_internal : std_logic; - signal rx_clock_100 : std_logic; - signal rx_clock_200 : std_logic; - signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); - --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --LVL1 channel - signal timing_trg_received_i : std_logic; - signal trg_data_valid_i : std_logic; - signal trg_timing_valid_i : std_logic; - signal trg_notiming_valid_i : std_logic; - signal trg_invalid_i : std_logic; - signal trg_type_i : std_logic_vector(3 downto 0); - signal trg_number_i : std_logic_vector(15 downto 0); - signal trg_code_i : std_logic_vector(7 downto 0); - signal trg_information_i : std_logic_vector(23 downto 0); - signal trg_int_number_i : std_logic_vector(15 downto 0); - signal trg_multiple_trg_i : std_logic; - signal trg_timeout_detected_i : std_logic; - signal trg_spurious_trg_i : std_logic; - signal trg_missing_tmg_trg_i : std_logic; - signal trg_spike_detected_i : std_logic; - - --Data channel - signal fee_trg_release_i : std_logic; - signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); - signal fee_data_i : std_logic_vector(31 downto 0); - signal fee_data_write_i : std_logic; - signal fee_data_finished_i : std_logic; - signal fee_almost_full_i : std_logic; - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal my_address : std_logic_vector (15 downto 0); - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal dac_read_en : std_logic; - signal dac_write_en : std_logic; - signal dac_data_in : std_logic_vector(31 downto 0); - signal dac_addr : std_logic_vector(4 downto 0); - signal dac_data_out : std_logic_vector(31 downto 0); - signal dac_ack : std_logic; - signal dac_busy : std_logic; - - signal hitreg_read_en : std_logic; - signal hitreg_write_en : std_logic; - signal hitreg_data_in : std_logic_vector(31 downto 0); - signal hitreg_addr : std_logic_vector(6 downto 0); - signal hitreg_data_out : std_logic_vector(31 downto 0); - signal hitreg_data_ready : std_logic; - signal hitreg_invalid : std_logic; - - signal srb_read_en : std_logic; - signal srb_write_en : std_logic; - signal srb_data_in : std_logic_vector(31 downto 0); - signal srb_addr : std_logic_vector(6 downto 0); - signal srb_data_out : std_logic_vector(31 downto 0); - signal srb_data_ready : std_logic; - signal srb_invalid : std_logic; - - signal cdb_read_en : std_logic; - signal cdb_write_en : std_logic; - signal cdb_data_in : std_logic_vector(31 downto 0); - signal cdb_addr : std_logic_vector(6 downto 0); - signal cdb_data_out : std_logic_vector(31 downto 0); - signal cdb_data_ready : std_logic; - signal cdb_invalid : std_logic; - - signal lhb_read_en : std_logic; - signal lhb_write_en : std_logic; - signal lhb_data_in : std_logic_vector(31 downto 0); - signal lhb_addr : std_logic_vector(6 downto 0); - signal lhb_data_out : std_logic_vector(31 downto 0); - signal lhb_data_ready : std_logic; - signal lhb_invalid : std_logic; - - signal esb_read_en : std_logic; - signal esb_write_en : std_logic; - signal esb_data_in : std_logic_vector(31 downto 0); - signal esb_addr : std_logic_vector(6 downto 0); - signal esb_data_out : std_logic_vector(31 downto 0); - signal esb_data_ready : std_logic; - signal esb_invalid : std_logic; - - signal efb_read_en : std_logic; - signal efb_write_en : std_logic; - signal efb_data_in : std_logic_vector(31 downto 0); - signal efb_addr : std_logic_vector(6 downto 0); - signal efb_data_out : std_logic_vector(31 downto 0); - signal efb_data_ready : std_logic; - signal efb_invalid : std_logic; - - signal tdc_ctrl_read : std_logic; - signal last_tdc_ctrl_read : std_logic; - signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(2 downto 0); - signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); - signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal sci1_ack : std_logic; - signal sci1_write : std_logic; - signal sci1_read : std_logic; - signal sci1_data_in : std_logic_vector(7 downto 0); - signal sci1_data_out : std_logic_vector(7 downto 0); - signal sci1_addr : std_logic_vector(8 downto 0); - - signal padiwa_cs : std_logic_vector(3 downto 0); - signal padiwa_sck : std_logic; - signal padiwa_sdi : std_logic; - signal padiwa_sdo : std_logic; - - signal trig_out : std_logic_vector(3 downto 0); - signal trig_din : std_logic_vector(31 downto 0); - signal trig_dout : std_logic_vector(31 downto 0); - signal trig_write : std_logic := '0'; - signal trig_read : std_logic := '0'; - signal trig_ack : std_logic := '0'; - signal trig_nack : std_logic := '0'; - signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal stat_out : std_logic_vector(3 downto 0); - signal stat_din : std_logic_vector(31 downto 0); - signal stat_dout : std_logic_vector(31 downto 0); - signal stat_write : std_logic := '0'; - signal stat_read : std_logic := '0'; - signal stat_ack : std_logic := '0'; - signal stat_nack : std_logic := '0'; - signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); - - --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal input_i : std_logic_vector(64 downto 1); - -begin ---------------------------------------------------------------------------- --- Reset Generation ---------------------------------------------------------------------------- - - GSR_N <= pll_lock; - - THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------------- --- Clock Handling ---------------------------------------------------------------------------- - - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_RIGHT, - CLKOP => clk_100_internal, - CLKOK => clk_200_internal, - LOCK => pll_lock - ); - - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF - port map ( - OSC => osc_int); - - gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_100_i <= rx_clock_100; - clk_200_i <= rx_clock_200; - clk_tdc <= rx_clock_200; - end generate; - - gen_local_clocks : if SYNC_MODE = c_NO generate - clk_100_i <= clk_100_internal; - clk_200_i <= clk_200_internal; - clk_tdc <= CLK_PCLK_LEFT; - end generate; - ---------------------------------------------------------------------------- --- The TrbNet media interface (to other FPGA) ---------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_CTC => c_NO, - USE_SLAVE => SYNC_MODE - ) - port map( - CLK => clk_200_internal, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - CLK_RX_HALF_OUT => rx_clock_100, - CLK_RX_FULL_OUT => rx_clock_200, - - --SFP Connection - SD_RXD_P_IN => SERDES_RX(2), - SD_RXD_N_IN => SERDES_RX(3), - SD_TXD_P_OUT => SERDES_TX(2), - SD_TXD_N_OUT => SERDES_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - - SCI_DATA_IN => sci1_data_in, - SCI_DATA_OUT => sci1_data_out, - SCI_ADDR => sci1_addr, - SCI_READ => sci1_read, - SCI_WRITE => sci1_write, - SCI_ACK => sci1_ack, - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); - - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - REGIO_INIT_ADDRESS => INIT_ADDRESS, - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 12, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**12-400, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, - LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, - LVL1_INVALID_TRG_OUT => trg_invalid_i, - - LVL1_TRG_TYPE_OUT => trg_type_i, - LVL1_TRG_NUMBER_OUT => trg_number_i, - LVL1_TRG_CODE_OUT => trg_code_i, - LVL1_TRG_INFORMATION_OUT => trg_information_i, - LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, - TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, - TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, - TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, - TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - - --Response from FEE - FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, - FEE_DATA_IN => fee_data_i, - FEE_DATA_WRITE_IN(0) => fee_data_write_i, - FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, - FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open - ); - - ---------------------------------------------------------------------------- --- I/O ---------------------------------------------------------------------------- - timing_trg_received_i <= TRIGGER_LEFT; - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 11, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", - 5 => x"b000", 6 => x"c800", 7 => x"cf00", 8 => x"cf80", 9 => x"d500", - 10 => x"c200", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, - 5 => 9, 6 => 3, 7 => 6, 8 => 7, 9 => 4, - 10 => 7, others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - --DAC - BUS_READ_ENABLE_OUT(2) => dac_read_en, - BUS_WRITE_ENABLE_OUT(2) => dac_write_en, - BUS_DATA_OUT(2*32+31 downto 2*32) => dac_data_in, - BUS_ADDR_OUT(2*16+4 downto 2*16) => dac_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => dac_data_out, - BUS_DATAREADY_IN(2) => dac_ack, - BUS_WRITE_ACK_IN(2) => dac_ack, - BUS_NO_MORE_DATA_IN(2) => dac_busy, - BUS_UNKNOWN_ADDR_IN(2) => '0', - --HitRegisters - BUS_READ_ENABLE_OUT(3) => hitreg_read_en, - BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, - BUS_DATA_OUT(3*32+31 downto 3*32) => open, - BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, - BUS_DATAREADY_IN(3) => hitreg_data_ready, - BUS_WRITE_ACK_IN(3) => '0', - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, - --Status Registers - BUS_READ_ENABLE_OUT(4) => srb_read_en, - BUS_WRITE_ENABLE_OUT(4) => srb_write_en, - BUS_DATA_OUT(4*32+31 downto 4*32) => open, - BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, - BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, - BUS_DATAREADY_IN(4) => srb_data_ready, - BUS_WRITE_ACK_IN(4) => '0', - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, - ----Encoder Start Registers - --BUS_READ_ENABLE_OUT(5) => esb_read_en, - --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, - --BUS_DATA_OUT(5*32+31 downto 5*32) => open, - --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, - --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, - --BUS_TIMEOUT_OUT(5) => open, - --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, - --BUS_DATAREADY_IN(5) => esb_data_ready, - --BUS_WRITE_ACK_IN(5) => '0', - --BUS_NO_MORE_DATA_IN(5) => '0', - --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, - ----Fifo Write Registers - --BUS_READ_ENABLE_OUT(6) => efb_read_en, - --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, - --BUS_DATA_OUT(6*32+31 downto 6*32) => open, - --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, - --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, - --BUS_TIMEOUT_OUT(6) => open, - --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, - --BUS_DATAREADY_IN(6) => efb_data_ready, - --BUS_WRITE_ACK_IN(6) => '0', - --BUS_NO_MORE_DATA_IN(6) => '0', - --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, - --SCI first Media Interface - BUS_READ_ENABLE_OUT(5) => sci1_read, - BUS_WRITE_ENABLE_OUT(5) => sci1_write, - BUS_DATA_OUT(5*32+7 downto 5*32) => sci1_data_in, - BUS_DATA_OUT(5*32+31 downto 5*32+8) => open, - BUS_ADDR_OUT(5*16+8 downto 5*16) => sci1_addr, - BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(5*32+7 downto 5*32) => sci1_data_out, - BUS_DATAREADY_IN(5) => sci1_ack, - BUS_WRITE_ACK_IN(5) => sci1_ack, - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => '0', - --TDC config registers - BUS_READ_ENABLE_OUT(6) => tdc_ctrl_read, - BUS_WRITE_ENABLE_OUT(6) => tdc_ctrl_write, - BUS_DATA_OUT(6*32+31 downto 6*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(6*16+2 downto 6*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(6*16+15 downto 6*16+3) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => tdc_ctrl_data_out, - BUS_DATAREADY_IN(6) => last_tdc_ctrl_read, - BUS_WRITE_ACK_IN(6) => tdc_ctrl_write, - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => '0', - --Trigger logic registers - BUS_READ_ENABLE_OUT(7) => trig_read, - BUS_WRITE_ENABLE_OUT(7) => trig_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => trig_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => trig_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => trig_dout, - BUS_DATAREADY_IN(7) => trig_ack, - BUS_WRITE_ACK_IN(7) => trig_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => trig_nack, - --Input statistics - BUS_READ_ENABLE_OUT(8) => stat_read, - BUS_WRITE_ENABLE_OUT(8) => stat_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => stat_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => stat_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => stat_dout, - BUS_DATAREADY_IN(8) => stat_ack, - BUS_WRITE_ACK_IN(8) => stat_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => stat_nack, - --SEU Detection - BUS_READ_ENABLE_OUT(9) => sed_read, - BUS_WRITE_ENABLE_OUT(9) => sed_write, - BUS_DATA_OUT(9*32+31 downto 9*32) => sed_din, - BUS_ADDR_OUT(9*16+15 downto 9*16) => sed_addr, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => sed_dout, - BUS_DATAREADY_IN(9) => sed_ack, - BUS_WRITE_ACK_IN(9) => sed_ack, - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => sed_nack, - --Channel Debug Registers - BUS_READ_ENABLE_OUT(10) => cdb_read_en, - BUS_WRITE_ENABLE_OUT(10) => cdb_write_en, - BUS_DATA_OUT(10*32+31 downto 10*32) => open, - BUS_ADDR_OUT(10*16+6 downto 10*16) => cdb_addr, - BUS_ADDR_OUT(10*16+15 downto 10*16+7) => open, - BUS_TIMEOUT_OUT(10) => open, - BUS_DATA_IN(10*32+31 downto 10*32) => cdb_data_out, - BUS_DATAREADY_IN(10) => cdb_data_ready, - BUS_WRITE_ACK_IN(10) => '0', - BUS_NO_MORE_DATA_IN(10) => '0', - BUS_UNKNOWN_ADDR_IN(10) => cdb_invalid, - - - STAT_DEBUG => open - ); - - PROC_TDC_CTRL_REG : process - variable pos : integer; - begin - wait until rising_edge(clk_100_i); - pos := to_integer(unsigned(tdc_ctrl_addr))*32; - tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); - last_tdc_ctrl_read <= tdc_ctrl_read; - if tdc_ctrl_write = '1' then - tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; - end if; - end process; - ---------------------------------------------------------------------------- --- SPI / Flash ---------------------------------------------------------------------------- - - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - --- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - ---------------------------------------------------------------------------- --- DAC ---------------------------------------------------------------------------- - gen_SPI : if INCLUDE_SPI = 1 generate - THE_DAC_SPI : spi_ltc2600 - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => dac_addr, - BUS_READ_IN => dac_read_en, - BUS_WRITE_IN => dac_write_en, - BUS_ACK_OUT => dac_ack, - BUS_BUSY_OUT => dac_busy, - BUS_DATA_IN => dac_data_in, - BUS_DATA_OUT => dac_data_out, - -- SPI connections - SPI_CS_OUT(3 downto 0) => padiwa_cs, - SPI_SDI_IN => padiwa_sdi, - SPI_SDO_OUT => padiwa_sdo, - SPI_SCK_OUT => padiwa_sck - ); - OUT_CS <= padiwa_cs(3 downto 0); - OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck; - OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo; - padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); - end generate; - ---------------------------------------------------------------------------- --- Trigger logic ---------------------------------------------------------------------------- - gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic - generic map( - INPUTS => PHYSICAL_INPUTS, - OUTPUTS => 4 - ) - port map( - CLK => clk_100_i, - - INPUT => input_i(PHYSICAL_INPUTS downto 1), - OUTPUT => trig_out, - - DATA_IN => trig_din, - DATA_OUT => trig_dout, - WRITE_IN => trig_write, - READ_IN => trig_read, - ACK_OUT => trig_ack, - NACK_OUT => trig_nack, - ADDR_IN => trig_addr - ); - FPGA5_COMM(10 downto 7) <= trig_out; - end generate; - ---------------------------------------------------------------------------- --- Input Statistics ---------------------------------------------------------------------------- - gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate - - THE_STAT_LOGIC : entity work.input_statistics - generic map( - INPUTS => PHYSICAL_INPUTS - ) - port map( - CLK => clk_100_i, - - INPUT => input_i(PHYSICAL_INPUTS downto 1), - - DATA_IN => stat_din, - DATA_OUT => stat_dout, - WRITE_IN => stat_write, - READ_IN => stat_read, - ACK_OUT => stat_ack, - NACK_OUT => stat_nack, - ADDR_IN => stat_addr - ); - end generate; - ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); - - - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - LED_ORANGE <= not reset_i when rising_edge(clk_100_internal); - LED_YELLOW <= '1'; - LED_GREEN <= not med_stat_op(9); - LED_RED <= not (med_stat_op(10) or med_stat_op(11)); - ---------------------------------------------------------------------------- --- Test Connector ---------------------------------------------------------------------------- --- TEST_LINE(15 downto 0) <= (others => '0'); ---------------------------------------------------------------------------- --- Test Circuits ---------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_internal); - time_counter <= time_counter + 1; - end process; - - - -------------------------------------------------------------------------------- --- TDC -------------------------------------------------------------------------------- - THE_TDC : TDC - generic map ( - CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels - STATUS_REG_NR => 21, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => TDC_VERSION, -- TDC version number - DEBUG => c_YES, - SIMULATION => c_NO) - port map ( - RESET => reset_i, - CLK_TDC => clk_tdc, -- Clock used for the time measurement - CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC - TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width - TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width - -- - -- Trigger signals from handler - TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet - VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet - VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet - INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet - TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet - SPIKE_DETECTED_IN => trg_spike_detected_i, - MULTI_TMG_TRG_IN => trg_multiple_trg_i, - SPURIOUS_TRG_IN => trg_spurious_trg_i, - -- - TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package - TRG_CODE_IN => trg_code_i, -- - TRG_INFORMATION_IN => trg_information_i, -- - TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package - -- - --Response to handler - TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal - TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc - DATA_OUT => fee_data_i, -- tdc data - DATA_WRITE_OUT => fee_data_write_i, -- data valid signal - DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal - -- - --Hit Counter Bus - HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe - HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe - HCB_ADDR_IN => hitreg_addr, -- bus address - HCB_DATA_OUT => hitreg_data_out, -- bus data - HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe - HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr - --Status Registers Bus - SRB_READ_EN_IN => srb_read_en, -- bus read en strobe - SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe - SRB_ADDR_IN => srb_addr, -- bus address - SRB_DATA_OUT => srb_data_out, -- bus data - SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe - SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr - --Channel Debug Bus - CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe - CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe - CDB_ADDR_IN => cdb_addr, -- bus address - CDB_DATA_OUT => cdb_data_out, -- bus data - CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe - CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr - --Encoder Start Registers Bus - ESB_READ_EN_IN => esb_read_en, -- bus read en strobe - ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe - ESB_ADDR_IN => esb_addr, -- bus address - ESB_DATA_OUT => esb_data_out, -- bus data - ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe - ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr - --Fifo Write Registers Bus - EFB_READ_EN_IN => efb_read_en, -- bus read en strobe - EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe - EFB_ADDR_IN => efb_addr, -- bus address - EFB_DATA_OUT => efb_data_out, -- bus data - EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe - EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr - --Lost Hit Registers Bus - LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe - LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe - LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address - LHB_DATA_OUT => open, -- lhb_data_out, -- bus data - LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe - LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr - -- - LOGIC_ANALYSER_OUT => TEST_LINE, - CONTROL_REG_IN => tdc_ctrl_reg); - - -- For single edge measurements - gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - hit_in_i <= INP; - input_i <= INP; - end generate; - - -- For ToT Measurements - gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - input_i(i) <= INP(i-1); - end generate Gen_Hit_In_Signals; - end generate; - - gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate - Gen_Hit_Fast_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i*2-2); - hit_in_i(i*2) <= not INP(i*2-2); - input_i(i) <= INP(i*2-2); - end generate; - end generate; - - -end architecture; diff --git a/wasa/trb3_periph_padiwa.vhd.1.7.xx b/wasa/trb3_periph_padiwa.vhd.1.7.xx deleted file mode 100644 index adfaa1e..0000000 --- a/wasa/trb3_periph_padiwa.vhd.1.7.xx +++ /dev/null @@ -1,1063 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.tdc_components.all; -use work.config.all; -use work.tdc_version.all; -use work.version.all; - - -entity trb3_periph_padiwa is - generic( - SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. - ); - port( - --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 6 - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Manager 3 - CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1 - --CLK_PCLK_RIGHT is the only clock with external termination !? - CLK_EXTERNAL : in std_logic; --Clock Manager 9 - - --- --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out --- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - - --Serdes - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used - SERDES_TX : out std_logic_vector(3 downto 2); - SERDES_RX : in std_logic_vector(3 downto 2); - - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - - - --Connections - SPARE_LINE : inout std_logic_vector(3 downto 0); - INP : in std_logic_vector(63 downto 0); - - --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - - --DAC - OUT_SDO : out std_logic_vector(4 downto 1); - IN_SDI : in std_logic_vector(4 downto 1); - OUT_SCK : out std_logic_vector(4 downto 1); - OUT_CS : out std_logic_vector(4 downto 1); - --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - - - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of OUT_SCK : signal is true; - attribute syn_useioff of OUT_CS : signal is true; - attribute syn_useioff of OUT_SDO : signal is true; - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of INP : signal is false; - - -end entity; - -architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 2; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - signal clk_100_internal : std_logic; - signal clk_200_internal : std_logic; - signal rx_clock_100 : std_logic; - signal rx_clock_200 : std_logic; - signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); - --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --LVL1 channel - signal timing_trg_received_i : std_logic; - signal trg_data_valid_i : std_logic; - signal trg_timing_valid_i : std_logic; - signal trg_notiming_valid_i : std_logic; - signal trg_invalid_i : std_logic; - signal trg_type_i : std_logic_vector(3 downto 0); - signal trg_number_i : std_logic_vector(15 downto 0); - signal trg_code_i : std_logic_vector(7 downto 0); - signal trg_information_i : std_logic_vector(23 downto 0); - signal trg_int_number_i : std_logic_vector(15 downto 0); - signal trg_multiple_trg_i : std_logic; - signal trg_timeout_detected_i : std_logic; - signal trg_spurious_trg_i : std_logic; - signal trg_missing_tmg_trg_i : std_logic; - signal trg_spike_detected_i : std_logic; - - --Data channel - signal fee_trg_release_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_trg_statusbits_i : std_logic_vector_array_32(0 to NUM_TDC_MODULES); - signal fee_data_i : std_logic_vector_array_32(0 to NUM_TDC_MODULES); - signal fee_data_write_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_data_finished_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_almost_full_i : std_logic_vector(NUM_TDC_MODULES downto 0); - signal fee_trg_statusbits : std_logic_vector((NUM_TDC_MODULES+1)*32-1 downto 0); - signal fee_data : std_logic_vector((NUM_TDC_MODULES+1)*32-1 downto 0); - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal my_address : std_logic_vector (15 downto 0); - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal dac_read_en : std_logic; - signal dac_write_en : std_logic; - signal dac_data_in : std_logic_vector(31 downto 0); - signal dac_addr : std_logic_vector(4 downto 0); - signal dac_data_out : std_logic_vector(31 downto 0); - signal dac_ack : std_logic; - signal dac_busy : std_logic; - - signal hitreg_read_en : std_logic; - signal hitreg_write_en : std_logic; - signal hitreg_data_in : std_logic_vector(31 downto 0); - signal hitreg_addr : std_logic_vector(6 downto 0); - signal hitreg_data_out : std_logic_vector(31 downto 0); - signal hitreg_data_ready : std_logic; - signal hitreg_invalid : std_logic; - - signal srb_read_en : std_logic; - signal srb_write_en : std_logic; - signal srb_data_in : std_logic_vector(31 downto 0); - signal srb_addr : std_logic_vector(6 downto 0); - signal srb_data_out : std_logic_vector(31 downto 0); - signal srb_data_ready : std_logic; - signal srb_invalid : std_logic; - - signal cdb_read_en : std_logic; - signal cdb_write_en : std_logic; - signal cdb_data_in : std_logic_vector(31 downto 0); - signal cdb_addr : std_logic_vector(6 downto 0); - signal cdb_data_out : std_logic_vector(31 downto 0); - signal cdb_data_ready : std_logic; - signal cdb_invalid : std_logic; - - signal lhb_read_en : std_logic; - signal lhb_write_en : std_logic; - signal lhb_data_in : std_logic_vector(31 downto 0); - signal lhb_addr : std_logic_vector(6 downto 0); - signal lhb_data_out : std_logic_vector(31 downto 0); - signal lhb_data_ready : std_logic; - signal lhb_invalid : std_logic; - - signal esb_read_en : std_logic; - signal esb_write_en : std_logic; - signal esb_data_in : std_logic_vector(31 downto 0); - signal esb_addr : std_logic_vector(6 downto 0); - signal esb_data_out : std_logic_vector(31 downto 0); - signal esb_data_ready : std_logic; - signal esb_invalid : std_logic; - - signal efb_read_en : std_logic; - signal efb_write_en : std_logic; - signal efb_data_in : std_logic_vector(31 downto 0); - signal efb_addr : std_logic_vector(6 downto 0); - signal efb_data_out : std_logic_vector(31 downto 0); - signal efb_data_ready : std_logic; - signal efb_invalid : std_logic; - - signal tdc_ctrl_read : std_logic; - signal last_tdc_ctrl_read : std_logic; - signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(2 downto 0); - signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); - signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal sci1_ack : std_logic; - signal sci1_write : std_logic; - signal sci1_read : std_logic; - signal sci1_data_in : std_logic_vector(7 downto 0); - signal sci1_data_out : std_logic_vector(7 downto 0); - signal sci1_addr : std_logic_vector(8 downto 0); - - signal padiwa_cs : std_logic_vector(3 downto 0); - signal padiwa_sck : std_logic; - signal padiwa_sdi : std_logic; - signal padiwa_sdo : std_logic; - - signal trig_out : std_logic_vector(3 downto 0); - signal trig_din : std_logic_vector(31 downto 0); - signal trig_dout : std_logic_vector(31 downto 0); - signal trig_write : std_logic := '0'; - signal trig_read : std_logic := '0'; - signal trig_ack : std_logic := '0'; - signal trig_nack : std_logic := '0'; - signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal stat_out : std_logic_vector(3 downto 0); - signal stat_din : std_logic_vector(31 downto 0); - signal stat_dout : std_logic_vector(31 downto 0); - signal stat_write : std_logic := '0'; - signal stat_read : std_logic := '0'; - signal stat_ack : std_logic := '0'; - signal stat_nack : std_logic := '0'; - signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); - - --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal input_i : std_logic_vector(64 downto 1); - -begin ---------------------------------------------------------------------------- --- Reset Generation ---------------------------------------------------------------------------- - - GSR_N <= pll_lock; - - THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------------- --- Clock Handling ---------------------------------------------------------------------------- - - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_RIGHT, - CLKOP => clk_100_internal, - CLKOK => clk_200_internal, - LOCK => pll_lock - ); - - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF - port map ( - OSC => osc_int); - - gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_100_i <= rx_clock_100; - clk_200_i <= rx_clock_200; - clk_tdc <= rx_clock_200; - end generate; - - gen_local_clocks : if SYNC_MODE = c_NO generate - clk_100_i <= clk_100_internal; - clk_200_i <= clk_200_internal; - clk_tdc <= CLK_PCLK_LEFT; - end generate; - ---------------------------------------------------------------------------- --- The TrbNet media interface (to other FPGA) ---------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_CTC => c_NO, - USE_SLAVE => SYNC_MODE - ) - port map( - CLK => clk_200_internal, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - CLK_RX_HALF_OUT => rx_clock_100, - CLK_RX_FULL_OUT => rx_clock_200, - - --SFP Connection - SD_RXD_P_IN => SERDES_RX(2), - SD_RXD_N_IN => SERDES_RX(3), - SD_TXD_P_OUT => SERDES_TX(2), - SD_TXD_N_OUT => SERDES_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - - SCI_DATA_IN => sci1_data_in, - SCI_DATA_OUT => sci1_data_out, - SCI_ADDR => sci1_addr, - SCI_READ => sci1_read, - SCI_WRITE => sci1_write, - SCI_ACK => sci1_ack, - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); - - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - REGIO_INIT_ADDRESS => INIT_ADDRESS, - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => NUM_TDC_MODULES+1, - DATA_BUFFER_DEPTH => 12, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**12-400, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, - LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, - LVL1_INVALID_TRG_OUT => trg_invalid_i, - - LVL1_TRG_TYPE_OUT => trg_type_i, - LVL1_TRG_NUMBER_OUT => trg_number_i, - LVL1_TRG_CODE_OUT => trg_code_i, - LVL1_TRG_INFORMATION_OUT => trg_information_i, - LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, - TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, - TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, - TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, - TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - - --Response from FEE - FEE_TRG_RELEASE_IN(NUM_TDC_MODULES downto 0) => fee_trg_release_i, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits, - FEE_DATA_IN => fee_data, - FEE_DATA_WRITE_IN(NUM_TDC_MODULES downto 0) => fee_data_write_i, - FEE_DATA_FINISHED_IN(NUM_TDC_MODULES downto 0) => fee_data_finished_i, - FEE_DATA_ALMOST_FULL_OUT(NUM_TDC_MODULES downto 0) => fee_almost_full_i, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open - ); - - Allign_Bits : for i in 0 to NUM_TDC_MODULES-1 generate --- fee_trg_statusbits((i+1)*32-1 downto i*32) <= fee_trg_statusbits_i(i)(31 downto 0); --- fee_data((i+1)*32-1 downto i*32) <= fee_data_i(i)(31 downto 0); - end generate Allign_Bits; - fee_trg_statusbits(31 downto 0) <= fee_trg_statusbits_i(0); - fee_trg_statusbits(63 downto 32) <= fee_trg_statusbits_i(1); - fee_trg_statusbits(95 downto 64) <= fee_trg_statusbits_i(2); - fee_trg_statusbits(127 downto 96) <= fee_trg_statusbits_i(3); - - fee_data(31 downto 0) <= fee_data_i(0); - fee_data(63 downto 32) <= fee_data_i(0); - fee_data(95 downto 64) <= fee_data_i(0); - fee_data(127 downto 96) <= fee_data_i(0); - - ---------------------------------------------------------------------------- --- I/O ---------------------------------------------------------------------------- - timing_trg_received_i <= TRIGGER_LEFT; - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 11, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", - 5 => x"b000", 6 => x"c800", 7 => x"cf00", 8 => x"cf80", 9 => x"d500", - 10 => x"c200", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, - 5 => 9, 6 => 3, 7 => 6, 8 => 7, 9 => 4, - 10 => 7, others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - --DAC - BUS_READ_ENABLE_OUT(2) => dac_read_en, - BUS_WRITE_ENABLE_OUT(2) => dac_write_en, - BUS_DATA_OUT(2*32+31 downto 2*32) => dac_data_in, - BUS_ADDR_OUT(2*16+4 downto 2*16) => dac_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => dac_data_out, - BUS_DATAREADY_IN(2) => dac_ack, - BUS_WRITE_ACK_IN(2) => dac_ack, - BUS_NO_MORE_DATA_IN(2) => dac_busy, - BUS_UNKNOWN_ADDR_IN(2) => '0', - --HitRegisters - BUS_READ_ENABLE_OUT(3) => hitreg_read_en, - BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, - BUS_DATA_OUT(3*32+31 downto 3*32) => open, - BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, - BUS_DATAREADY_IN(3) => hitreg_data_ready, - BUS_WRITE_ACK_IN(3) => '0', - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, - --Status Registers - BUS_READ_ENABLE_OUT(4) => srb_read_en, - BUS_WRITE_ENABLE_OUT(4) => srb_write_en, - BUS_DATA_OUT(4*32+31 downto 4*32) => open, - BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, - BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, - BUS_DATAREADY_IN(4) => srb_data_ready, - BUS_WRITE_ACK_IN(4) => '0', - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, - ----Encoder Start Registers - --BUS_READ_ENABLE_OUT(5) => esb_read_en, - --BUS_WRITE_ENABLE_OUT(5) => esb_write_en, - --BUS_DATA_OUT(5*32+31 downto 5*32) => open, - --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, - --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, - --BUS_TIMEOUT_OUT(5) => open, - --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, - --BUS_DATAREADY_IN(5) => esb_data_ready, - --BUS_WRITE_ACK_IN(5) => '0', - --BUS_NO_MORE_DATA_IN(5) => '0', - --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, - ----Fifo Write Registers - --BUS_READ_ENABLE_OUT(6) => efb_read_en, - --BUS_WRITE_ENABLE_OUT(6) => efb_write_en, - --BUS_DATA_OUT(6*32+31 downto 6*32) => open, - --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, - --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, - --BUS_TIMEOUT_OUT(6) => open, - --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, - --BUS_DATAREADY_IN(6) => efb_data_ready, - --BUS_WRITE_ACK_IN(6) => '0', - --BUS_NO_MORE_DATA_IN(6) => '0', - --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, - --SCI first Media Interface - BUS_READ_ENABLE_OUT(5) => sci1_read, - BUS_WRITE_ENABLE_OUT(5) => sci1_write, - BUS_DATA_OUT(5*32+7 downto 5*32) => sci1_data_in, - BUS_DATA_OUT(5*32+31 downto 5*32+8) => open, - BUS_ADDR_OUT(5*16+8 downto 5*16) => sci1_addr, - BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(5*32+7 downto 5*32) => sci1_data_out, - BUS_DATAREADY_IN(5) => sci1_ack, - BUS_WRITE_ACK_IN(5) => sci1_ack, - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => '0', - --TDC config registers - BUS_READ_ENABLE_OUT(6) => tdc_ctrl_read, - BUS_WRITE_ENABLE_OUT(6) => tdc_ctrl_write, - BUS_DATA_OUT(6*32+31 downto 6*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(6*16+2 downto 6*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(6*16+15 downto 6*16+3) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => tdc_ctrl_data_out, - BUS_DATAREADY_IN(6) => last_tdc_ctrl_read, - BUS_WRITE_ACK_IN(6) => tdc_ctrl_write, - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => '0', - --Trigger logic registers - BUS_READ_ENABLE_OUT(7) => trig_read, - BUS_WRITE_ENABLE_OUT(7) => trig_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => trig_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => trig_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => trig_dout, - BUS_DATAREADY_IN(7) => trig_ack, - BUS_WRITE_ACK_IN(7) => trig_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => trig_nack, - --Input statistics - BUS_READ_ENABLE_OUT(8) => stat_read, - BUS_WRITE_ENABLE_OUT(8) => stat_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => stat_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => stat_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => stat_dout, - BUS_DATAREADY_IN(8) => stat_ack, - BUS_WRITE_ACK_IN(8) => stat_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => stat_nack, - --SEU Detection - BUS_READ_ENABLE_OUT(9) => sed_read, - BUS_WRITE_ENABLE_OUT(9) => sed_write, - BUS_DATA_OUT(9*32+31 downto 9*32) => sed_din, - BUS_ADDR_OUT(9*16+15 downto 9*16) => sed_addr, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => sed_dout, - BUS_DATAREADY_IN(9) => sed_ack, - BUS_WRITE_ACK_IN(9) => sed_ack, - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => sed_nack, - --Channel Debug Registers - BUS_READ_ENABLE_OUT(10) => cdb_read_en, - BUS_WRITE_ENABLE_OUT(10) => cdb_write_en, - BUS_DATA_OUT(10*32+31 downto 10*32) => open, - BUS_ADDR_OUT(10*16+6 downto 10*16) => cdb_addr, - BUS_ADDR_OUT(10*16+15 downto 10*16+7) => open, - BUS_TIMEOUT_OUT(10) => open, - BUS_DATA_IN(10*32+31 downto 10*32) => cdb_data_out, - BUS_DATAREADY_IN(10) => cdb_data_ready, - BUS_WRITE_ACK_IN(10) => '0', - BUS_NO_MORE_DATA_IN(10) => '0', - BUS_UNKNOWN_ADDR_IN(10) => cdb_invalid, - - - STAT_DEBUG => open - ); - - PROC_TDC_CTRL_REG : process - variable pos : integer; - begin - wait until rising_edge(clk_100_i); - pos := to_integer(unsigned(tdc_ctrl_addr))*32; - tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); - last_tdc_ctrl_read <= tdc_ctrl_read; - if tdc_ctrl_write = '1' then - tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; - end if; - end process; - ---------------------------------------------------------------------------- --- SPI / Flash ---------------------------------------------------------------------------- - - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - --- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - ---------------------------------------------------------------------------- --- DAC ---------------------------------------------------------------------------- - gen_SPI : if INCLUDE_SPI = 1 generate - THE_DAC_SPI : spi_ltc2600 - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => dac_addr, - BUS_READ_IN => dac_read_en, - BUS_WRITE_IN => dac_write_en, - BUS_ACK_OUT => dac_ack, - BUS_BUSY_OUT => dac_busy, - BUS_DATA_IN => dac_data_in, - BUS_DATA_OUT => dac_data_out, - -- SPI connections - SPI_CS_OUT(3 downto 0) => padiwa_cs, - SPI_SDI_IN => padiwa_sdi, - SPI_SDO_OUT => padiwa_sdo, - SPI_SCK_OUT => padiwa_sck - ); - OUT_CS <= padiwa_cs(3 downto 0); - OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck; - OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo; - padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); - end generate; - ---------------------------------------------------------------------------- --- Trigger logic ---------------------------------------------------------------------------- - gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic - generic map( - INPUTS => PHYSICAL_INPUTS, - OUTPUTS => 4 - ) - port map( - CLK => clk_100_i, - - INPUT => input_i(PHYSICAL_INPUTS downto 1), - OUTPUT => trig_out, - - DATA_IN => trig_din, - DATA_OUT => trig_dout, - WRITE_IN => trig_write, - READ_IN => trig_read, - ACK_OUT => trig_ack, - NACK_OUT => trig_nack, - ADDR_IN => trig_addr - ); - FPGA5_COMM(10 downto 7) <= trig_out; - end generate; - ---------------------------------------------------------------------------- --- Input Statistics ---------------------------------------------------------------------------- - gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate - - THE_STAT_LOGIC : entity work.input_statistics - generic map( - INPUTS => PHYSICAL_INPUTS - ) - port map( - CLK => clk_100_i, - - INPUT => input_i(PHYSICAL_INPUTS downto 1), - - DATA_IN => stat_din, - DATA_OUT => stat_dout, - WRITE_IN => stat_write, - READ_IN => stat_read, - ACK_OUT => stat_ack, - NACK_OUT => stat_nack, - ADDR_IN => stat_addr - ); - end generate; - ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); - - - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - LED_ORANGE <= not reset_i when rising_edge(clk_100_internal); - LED_YELLOW <= '1'; - LED_GREEN <= not med_stat_op(9); - LED_RED <= not (med_stat_op(10) or med_stat_op(11)); - ---------------------------------------------------------------------------- --- Test Connector ---------------------------------------------------------------------------- --- TEST_LINE(15 downto 0) <= (others => '0'); ---------------------------------------------------------------------------- --- Test Circuits ---------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_internal); - time_counter <= time_counter + 1; - end process; - - - -------------------------------------------------------------------------------- --- TDC -------------------------------------------------------------------------------- - THE_TDC : TDC - generic map ( - MODULE_NUMBER => NUM_TDC_MODULES, -- Number of TDC modules - CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels - STATUS_REG_NR => 21, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => TDC_VERSION, -- TDC version number - DEBUG => c_YES, - SIMULATION => c_NO) - port map ( - RESET => reset_i, - CLK_TDC => clk_tdc, -- Clock used for the time measurement - CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(NUM_TDC_MODULES*NUM_TDC_CHANNELS downto 1), -- Channel start signals - HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC - TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width - TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width - -- - -- Trigger signals from handler - TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet - VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet - VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet - INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet - TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet - SPIKE_DETECTED_IN => trg_spike_detected_i, - MULTI_TMG_TRG_IN => trg_multiple_trg_i, - SPURIOUS_TRG_IN => trg_spurious_trg_i, - -- - TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package - TRG_CODE_IN => trg_code_i, -- - TRG_INFORMATION_IN => trg_information_i, -- - TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package - -- - --Response to handler - TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal - TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc - DATA_OUT => fee_data_i, -- tdc data - DATA_WRITE_OUT => fee_data_write_i, -- data valid signal - DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal - -- - --Hit Counter Bus - HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe - HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe - HCB_ADDR_IN => hitreg_addr, -- bus address - HCB_DATA_OUT => hitreg_data_out, -- bus data - HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe - HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr - --Status Registers Bus - SRB_READ_EN_IN => srb_read_en, -- bus read en strobe - SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe - SRB_ADDR_IN => srb_addr, -- bus address - SRB_DATA_OUT => srb_data_out, -- bus data - SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe - SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr - --Channel Debug Bus - CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe - CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe - CDB_ADDR_IN => cdb_addr, -- bus address - CDB_DATA_OUT => cdb_data_out, -- bus data - CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe - CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr - --Encoder Start Registers Bus - ESB_READ_EN_IN => esb_read_en, -- bus read en strobe - ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe - ESB_ADDR_IN => esb_addr, -- bus address - ESB_DATA_OUT => esb_data_out, -- bus data - ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe - ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr - --Fifo Write Registers Bus - EFB_READ_EN_IN => efb_read_en, -- bus read en strobe - EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe - EFB_ADDR_IN => efb_addr, -- bus address - EFB_DATA_OUT => efb_data_out, -- bus data - EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe - EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr - --Lost Hit Registers Bus - LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe - LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe - LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address - LHB_DATA_OUT => open, -- lhb_data_out, -- bus data - LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe - LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr - -- - LOGIC_ANALYSER_OUT => TEST_LINE, - CONTROL_REG_IN => tdc_ctrl_reg); - - -- For single edge measurements - gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - hit_in_i <= INP; - input_i <= INP; - end generate; - - -- For ToT Measurements - gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - input_i(i) <= INP(i-1); - end generate Gen_Hit_In_Signals; - end generate; - - gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate - Gen_Hit_Fast_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i*2-2); - hit_in_i(i*2) <= not INP(i*2-2); - input_i(i) <= INP(i*2-2); - end generate; - end generate; - - -end architecture;