From: Adrian Weber Date: Wed, 15 Jun 2022 09:17:32 +0000 (+0200) Subject: improve timing of cbmrich trb5sc X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3232fd69bc3ed18a2db0a5bb75215d923a07f9ae;p=trb5sc.git improve timing of cbmrich trb5sc --- diff --git a/cbmrich/config_compile_giessen.pl b/cbmrich/config_compile_giessen.pl index 903b491..8a51e04 100644 --- a/cbmrich/config_compile_giessen.pl +++ b/cbmrich/config_compile_giessen.pl @@ -12,7 +12,7 @@ synplify_path => '/usr/local/diamond/3.11_x64/synpbase', synplify_command => "synpwrap -fg -options", #synplify_command => "ssh adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"", -nodelist_file => '../nodes_lxhadeb07.txt', +nodelist_file => '../nodelist_giessen.txt', par_options => '../par.p2t', #Include only necessary lpf files diff --git a/cbmrich/nodelist_giessen.txt b/cbmrich/nodelist_giessen.txt new file mode 100644 index 0000000..aa23d58 --- /dev/null +++ b/cbmrich/nodelist_giessen.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + + +[fb07pc-u102325] +SYSTEM = linux +CORENUM = 12 +WORKDIR = /home/adrian/trbvhdl/trb5sc/cbmrich/workdir diff --git a/cbmrich/trb5sc_cbmrich.lpf b/cbmrich/trb5sc_cbmrich.lpf index b6be2d6..60a5200 100644 --- a/cbmrich/trb5sc_cbmrich.lpf +++ b/cbmrich/trb5sc_cbmrich.lpf @@ -26,7 +26,7 @@ BLOCK PATH FROM PORT "TEMP_LINE"; BLOCK PATH TO PORT "TEST_LINE*"; #MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; -#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; #MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; #MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; @@ -41,3 +41,10 @@ GSR_NET NET "clear_i"; REGION "MEDIA" "R81C44D" 13 25; LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; + +BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*.FC/FF*"; +BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/TheTriggerHandler/trg_in_r[0]"; + +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/sd_los_i" 2x; diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj index 11a145b..728ad6a 100644 --- a/cbmrich/trb5sc_cbmrich.prj +++ b/cbmrich/trb5sc_cbmrich.prj @@ -267,7 +267,7 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" #TDC Calibration add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Calibration.vhd" -add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Cal_Limits_v2.vhd" +add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Cal_Limits_v2_1.vhd" add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/cnt_val.vhd" add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/default_val.vhd" add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/LUT.vhd" diff --git a/cbmrich/trb5sc_cbmrich.vhd b/cbmrich/trb5sc_cbmrich.vhd index 3ecd028..b6df9a8 100644 --- a/cbmrich/trb5sc_cbmrich.vhd +++ b/cbmrich/trb5sc_cbmrich.vhd @@ -635,46 +635,46 @@ THE_CTS : CTS -- MBS --------------------------------------------------------------------------- - THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator - generic map( - INCL_REGIO => c_YES - ) - port map ( - CLK => clk_sys, - RESET_IN => reset_i, - - -- recovered clock, synchronous to DLM @240MHz - CLK_RCV => med2int(INTERFACE_NUM).clk_full, - - --DLM inputs - DLM_IN => dlm_rx_i, - DLM_MSG_IN => dlm_rx_word, - - --trigger outputs - TRG_ASYNC_OUT => async_ext_trig, - TRG_SYNC_OUT => cts_ext_trigger, - - --data output for read-out - TRIGGER_IN => cts_rdo_rx.data_valid, - TRIGGER_TYPE => cts_rdo_rx.trg_type, - - -- Data connection to Streamer - DATA_OUT => cts_rdo_additional(0).data, - WRITE_OUT => cts_rdo_additional(0).data_write, - STATUSBIT_OUT => cts_rdo_additional(0).statusbits, - FINISHED_OUT => cts_rdo_additional(0).data_finished, - - --Registers / Debug - REGIO_IN => bus_mbs_rx, - REGIO_OUT => bus_mbs_tx, - - -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode) - CONTROL_REG_IN => cts_ext_control, - STATUS_REG_OUT => cts_ext_status, - HEADER_REG_OUT => cts_ext_header, - DEBUG => cts_ext_debug - ); - + THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator + generic map( + INCL_REGIO => c_YES + ) + port map ( + CLK => clk_sys, + RESET_IN => reset_i, + + -- recovered clock, synchronous to DLM @240MHz + CLK_RCV => med2int(INTERFACE_NUM).clk_full, + + --DLM inputs + DLM_IN => dlm_rx_i, + DLM_MSG_IN => dlm_rx_word, + + --trigger outputs + TRG_ASYNC_OUT => async_ext_trig, + TRG_SYNC_OUT => cts_ext_trigger, + + --data output for read-out + TRIGGER_IN => cts_rdo_rx.data_valid, + TRIGGER_TYPE => cts_rdo_rx.trg_type, + + -- Data connection to Streamer + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + + --Registers / Debug + REGIO_IN => bus_mbs_rx, + REGIO_OUT => bus_mbs_tx, + + -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode) + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + HEADER_REG_OUT => cts_ext_header, + DEBUG => cts_ext_debug + ); + --------------------------------------------------------------------------- -- Bus Handler ---------------------------------------------------------------------------