From: Peter Lemmens
Date: Thu, 11 Dec 2014 14:19:46 +0000 (+0100)
Subject: FEE_adc32 added to the soda-git
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3271956e008104d766fb65f58130d6d360d92695;p=soda.git
FEE_adc32 added to the soda-git
---
diff --git a/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd b/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd
new file mode 100644
index 0000000..3eaa682
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd
@@ -0,0 +1,186 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-11-2014
+-- Module Name: FEE_SODAfrequencydiv5
+-- Description: Converts 200MHz from GTX to 40 MHz SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_SODAfrequencydiv5
+-- Measures the number of pulses in one second
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : recovered clock
+-- data : data from GTX
+-- kchar : k-character signal from GTX
+--
+-- Outputs:
+-- clockdiv5 : input clock divided by 5 and synchronous to SODA
+-- error : error in incoming data or phase
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_SODAfrequencydiv5 is
+ port (
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic
+ );
+end FEE_SODAfrequencydiv5;
+
+architecture Behavioral of FEE_SODAfrequencydiv5 is
+constant KCHARSODA : std_logic_vector(7 downto 0) := x"DC";
+
+signal clockdiv5_S : std_logic;
+signal div5count0_S : std_logic;
+signal clock5div2_S : std_logic := '0';
+signal prev_clock5div2_S : std_logic := '0';
+signal clockdiv5_reset_S : std_logic;
+signal SODA_kchar_S : std_logic;
+signal disable_SODAcheck_S : std_logic := '0';
+signal disable_clock5check_S : std_logic := '0';
+signal SODA40_signal_S : std_logic;
+signal div5count_S : std_logic_vector(2 downto 0) := (others => '0');
+signal SODA_count_S : std_logic_vector(3 downto 0) := (others => '0');
+signal SODAerror_S : std_logic;
+signal clockdiv5error_S : std_logic;
+signal clockbiterror_S : std_logic;
+
+begin
+
+error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_S='1') else '0';
+clockdiv5 <= clockdiv5_S;
+
+rxrecclk_bufrdiv5_i : BUFR
+ generic map ( BUFR_DIVIDE => "5" )
+ port map (
+ CE => '1',
+ CLR => clockdiv5_reset_S,
+ I => clock,
+ O => clockdiv5_S);
+
+process_checkSODA: process(clock)
+variable disable_count_V : std_logic_vector(1 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ div5count0_S <= '0';
+ clockbiterror_S <= '0';
+ if div5count_S/="100" then
+ if (disable_SODAcheck_S='0') and (SODA40_signal_S='1') then -- wrong phase
+ div5count_S <= "000";
+ disable_SODAcheck_S <= '1';
+ disable_count_V := (others => '0');
+ clockbiterror_S <= '1';
+ else
+ div5count_S <= div5count_S+1;
+ end if;
+ else
+ div5count_S <= "000";
+ div5count0_S <= '1';
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_SODAcheck_S <= '0';
+ end if;
+ end if;
+ prev_clock5div2_S <= clock5div2_S;
+ end if;
+end process;
+
+
+
+process_checkdiv5: process(clock)
+variable disable_count_V : std_logic_vector(3 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ clockdiv5_reset_S <= '0';
+ clockdiv5error_S <= '0';
+ if (disable_SODAcheck_S='0') and (disable_clock5check_S='0') then
+ if (clock5div2_S/=prev_clock5div2_S) and div5count0_S='0' then -- div5 clock wrong phase : reset
+ clockdiv5_reset_S <= '1';
+ disable_clock5check_S <= '1';
+ disable_count_V := (others => '0');
+ clockdiv5error_S <= '1';
+ end if;
+ else
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_clock5check_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+process_SODAchar: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ if (kchar='1') and (data=KCHARSODA) then
+ SODA_kchar_S <= '1';
+ else
+ SODA_kchar_S <= '0';
+ end if;
+ end if;
+end process;
+
+process_SODAstart: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ SODA40_signal_S <= '0';
+ SODAerror_S <= '0';
+ if (SODA_count_S="0000") and (SODA_kchar_S='1') then
+ SODA40_signal_S <= '1';
+ SODA_count_S <= SODA_count_S+1;
+ elsif SODA_count_S(0)='1' then -- SODA data
+ if SODA_kchar_S='1' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(2 downto 1)/="00") then -- SODA k-char
+ if SODA_kchar_S='0' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(3)='1') then -- end SODA packet
+ SODA_count_S <= "0000";
+ if SODA_kchar_S='1' then -- error
+ SODAerror_S <= '1';
+ end if;
+ end if;
+ end if;
+end process;
+
+process_clock5div2: process(clockdiv5_S)
+begin
+ if (rising_edge(clockdiv5_S)) then
+ clock5div2_S <= not clock5div2_S;
+ end if;
+end process;
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd b/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd
new file mode 100644
index 0000000..cdb51cb
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd
@@ -0,0 +1,610 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 15-02-2012
+-- Module Name: FEE_adc32_module
+-- Description: Module with Front End Electronics
+-- Modifications:
+-- 15-09-2014 New datafromat for fibers, removed ZPU
+-- 16-09-2014 name changed from FEE_V2_adc32_module to FEE_adc32_module
+-- 22-09-2014 single clock
+-- 23-09-2014 system monitor module moved to top-level
+-- 01-10-2014 request_init added: request initialize FEE
+-- 02-10-2014 onesecondpulse, errorbyte
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_adc32_module
+-- Module for Front End Electronics: fiber connection, adc waveform reading & multiplexers & feature extraction.
+-- ADC data is analysed or put in waveforms if regarded as pileup.
+--
+-- The data is sent to the GTP/GTX transceiver in packets
+-- Slow control processes slow-control packets on the fiber to/from the multiplexer board.
+-- The clock from the GTP/GTX receiver is used to synchronise the SODA-clock. This should be used for the ADC's if that is possible with the hardware.
+-- Special SODA package can start/stop data transmitting and reset the timepstamp.
+-- The from the fiber also SODA packets.
+--
+-- The addresses that are used:
+-- board_register A: write/read
+-- bit0: reset all
+-- bit2: clear errors
+-- bit3: enable waveforms
+-- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
+-- bit 18 = reset/initializes FPGA System monitor
+-- board_register B: read
+-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
+-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
+-- bit 15..6 = ADC value from FPGA System monitor
+-- bit23..16 : error occurred bits: in case of error a bit is set. Clearing is done with ADDRESS_FEE_CONTROL
+-- bit16 : error : NotInTable
+-- bit17 : error : receive data error (slowcontrol)
+-- bit18 : error : slowcontrol buffer overrun
+-- bit19 : error : not used
+-- bit20 : error : transmit data error, multiplexer error
+-- bit21 : error : receive data buffer overrun
+-- bit22 : error : adc data buffer overrun
+-- bit23 : error : data taken disabled
+-- board_register C: automatically sent
+-- data not important; this slowcontrol command indicates buffer full
+-- board_register D: read
+-- bit 31..0 = Number of pulses in 1 second on selected input
+--
+-- Each ADC has its own set of registers. See module FEE_pulse_and_pileup_waveforms for addresses.
+--
+--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+-- NROFADCS : number of the adc's, probably 16
+-- ADCBITS : number of ADC-bits
+-- BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
+-- CF_DELAYBITS : number of bits for the constant fraction delay
+-- CF_FRACTIONBIT : number of bits for the calculated fraction of the precise timestamp
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--
+-- Inputs:
+-- clock : clock for everything
+-- reset : reset all
+-- enable_data : enable data, controlled by SODA
+-- ADCdata : parallel sampling adc data
+-- rxNotInTable : error in received fiber data, used for status
+-- superburst_start : Signal to indicate start of new superburst, received (back) from pin
+-- superburst_received : superburstnumber
+-- startupready : startup procedure is finished: ready to send data
+-- request_init : send a request to the DC to initialize all registers
+-- packet_in_data : 32 bits data input from fiber module
+-- packet_in_present : data available from fiber module
+-- packet_out_fifofull : connected fifo for packet data is full
+-- errorbyte_in : errors occurred for slow control reply
+-- smaart_in : serial input from external TMP104 sensor
+-- sysmon_data : data from the FPGA system monitor module
+--
+-- Outputs:
+-- packet_in_read : read signal to fiber module to read next data
+-- packet_out_data : packet data to fiber module
+-- packet_out_first : first 32-bit data word of a packet
+-- packet_out_last : last 32-bit data word of a packet
+-- packet_out_write : write signal for packet data
+-- errorbyte_out : errors occurred: adjust with other FE instances for comparison
+-- smaart_out : serial output to external TMP104 sensor
+-- sysmon_reset : reset signal to the FPGA system monitor module
+-- sysmon_address : selection address for the FPGA system monitor module
+-- sysmon_read : read signal to the FPGA system monitor module
+--
+-- Components:
+-- FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
+-- FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
+-- FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream
+-- FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX
+-- FEE_measure_frequency : measure frequency of hits
+-- TMP104module : module to access external temperature sensor TMP104
+--
+----------------------------------------------------------------------------------
+
+entity FEE_adc32_module is
+ generic (
+ NROFADCS : natural := 32;
+ ADCBITS : natural := 14;
+ BASELINE_BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ ADCCLOCKFREQUENCY : natural := 80000000;
+ CF_DELAYBITS : natural := 4;
+ CF_FRACTIONBIT : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable_data : in std_logic;
+ ADCdata : in array_adc_type;
+ superburst_start : in std_logic;
+ superburst_received : in std_logic_vector(30 downto 0);
+ onesecondpulse : in std_logic;
+ rxNotInTable : in std_logic;
+ startupready : in std_logic;
+ request_init : in std_logic;
+ packet_in_data : in std_logic_vector (31 downto 0);
+ packet_in_present : in std_logic;
+ packet_in_read : out std_logic;
+ packet_out_data : out std_logic_vector(31 downto 0);
+ packet_out_first : out std_logic;
+ packet_out_last : out std_logic;
+ packet_out_write : out std_logic;
+ packet_out_fifofull : in std_logic;
+ errorbyte_out : out std_logic_vector(7 downto 0);
+ errorbyte_in : in std_logic_vector(7 downto 0);
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ sysmon_data : in std_logic_vector(15 downto 0);
+ sysmon_reset : out std_logic;
+ sysmon_address : out std_logic_vector(6 downto 0);
+ sysmon_read : out std_logic;
+ testindex : in integer range 0 to NROFADCS/2-1;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end FEE_adc32_module;
+
+architecture Behavioral of FEE_adc32_module is
+
+
+component FEE_board_slowcontrol is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ overflow_in : in std_logic;
+ request_init : in std_logic;
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ slowcontrol_read : in std_logic;
+ slowcontrol_notpresent : out std_logic;
+ slowcontrol_data : out std_logic_vector (31 downto 0);
+ slowcontrol_address : out std_logic_vector (7 downto 0);
+ slowcontrol_reply : out std_logic;
+ board_status_A : in std_logic_vector(31 downto 0);
+ board_status_B : in std_logic_vector(31 downto 0);
+ board_status_C : in std_logic_vector(31 downto 0);
+ board_status_D : in std_logic_vector(31 downto 0);
+ board_control_A : out std_logic_vector(31 downto 0);
+ board_control_B : out std_logic_vector(31 downto 0);
+ board_control_C : out std_logic_vector(31 downto 0);
+ board_control_D : out std_logic_vector(31 downto 0);
+ overflow_out : out std_logic
+ );
+end component;
+
+component FEE_slowcontrol_packet_receiver is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ packet_data_in : in std_logic_vector (31 downto 0);
+ packet_data_present : in std_logic;
+ packet_data_read : out std_logic;
+ byte_data : out std_logic_vector(7 downto 0);
+ byte_write : out std_logic;
+ byte_request : out std_logic;
+ data_error : out std_logic;
+ overflow : out std_logic);
+end component;
+
+component FEE_pulse_and_pileup_waveforms is
+ generic (
+ NROFADCS : natural := NROFADCS;
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BASELINE_BWBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADCdata : in array_adc_type;
+ enable_data : in std_logic;
+ slowcontrol_byte_data : in std_logic_vector (7 downto 0);
+ slowcontrol_byte_write : in std_logic;
+ slowcontrol_byte_request: in std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_read : in std_logic;
+ pulsedata_available : out std_logic;
+ pulsedata_inpipe : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_read : in std_logic;
+ pileupdata_available : out std_logic;
+ pileupdata_inpipe : out std_logic;
+ pulsedetect : out std_logic_vector(0 to NROFADCS-1);
+ overflow : out std_logic;
+ testindex : in integer range 0 to NROFADCS/2-1;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_combine_data is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ -- signals to/from data fifo :
+ pulse_data : in std_logic_vector(35 downto 0);
+ pulse_notpresent : in std_logic; -- empty signal from fifo
+ pulse_inpipe : in std_logic;
+ pulse_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data : in std_logic_vector(31 downto 0);
+ slowcontrol_address : in std_logic_vector(7 downto 0);
+ slowcontrol_reply : in std_logic;
+ slowcontrol_notpresent : in std_logic; -- empty signal from fifo
+ slowcontrol_read : out std_logic; -- read from normal fifo
+ -- signals to/from waveform fifo
+ wave_data : in std_logic_vector(35 downto 0);
+ wave_notpresent : in std_logic; -- empty signal from fifo
+ wave_inpipe : in std_logic;
+ wave_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from fiber module
+ packet_data_out : out std_logic_vector(31 downto 0);
+ packet_firstword : out std_logic;
+ packet_lastword : out std_logic;
+ packet_datawrite : out std_logic;
+ packet_fifofull : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_measure_frequency is
+ generic (
+ CLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY
+ );
+ port (
+ clock : in std_logic;
+ pulse : in std_logic;
+ onesecondpulse : in std_logic;
+ frequency : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+
+component TMP104module is
+ generic (
+ TMP104CLOCKDIVIDER : natural := 2500;
+ TMP104INTERVAL : natural := 50
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ temperature : out std_logic_vector (7 downto 0)
+ );
+end component;
+
+constant init_frequency_in_kHz : integer := 30;
+constant init_freqnr : integer := init_frequency_in_kHz * 83322;
+
+signal error_occurred_S : std_logic_vector (7 downto 0) := (others => '0');
+signal enable_data_S : std_logic := '0';
+signal startupready_S : std_logic := '0';
+
+signal rxAsyncDataRead_S : std_logic := '0';
+signal rxAsyncData_S : std_logic_vector (31 downto 0) := (others => '0');
+
+signal packet_in_read_S : std_logic;
+
+signal superburstnumber_s : std_logic_vector(30 downto 0);
+
+signal SODA_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
+signal SODA_cmd_valid_S : std_logic := '0';
+
+signal slowcontrol_error1_S : std_logic := '0';
+
+signal clear_errors_S : std_logic := '0';
+
+signal pulsedata_out_S : std_logic_vector(35 downto 0);
+signal pulsedata_read_S : std_logic;
+signal pulsedata_available_S : std_logic;
+signal pulsedata_inpipe_S : std_logic;
+signal pileupdata_out_S : std_logic_vector(35 downto 0);
+signal pileupdata_read_S : std_logic;
+signal pileupdata_available_S : std_logic;
+signal pulse_notpresent_S : std_logic;
+signal pileupdata_inpipe_s : std_logic;
+signal overflow_S : std_logic;
+
+signal slowcontrol_data_S : std_logic_vector(31 downto 0);
+signal slowcontrol_address_S : std_logic_vector(7 downto 0);
+signal slowcontrol_reply_S : std_logic;
+signal slowcontrol_notpresent_S : std_logic;
+signal slowcontrol_read_S : std_logic;
+signal receive_overflow_S : std_logic;
+
+signal slowcontrol_byte_data_S : std_logic_vector(7 downto 0);
+signal slowcontrol_byte_write_S : std_logic;
+signal slowcontrol_byte_request_S : std_logic;
+signal slowcontrol_overflow_S : std_logic;
+
+signal board_status_A_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_B_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_C_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_D_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_control_A_S : std_logic_vector(31 downto 0);
+signal board_control_B_S : std_logic_vector(31 downto 0);
+signal board_control_C_S : std_logic_vector(31 downto 0);
+signal board_control_D_S : std_logic_vector(31 downto 0);
+
+
+signal timestampcounter_s : std_logic_vector(15 downto 0) := (others => '0');
+signal start_of_superburst_S : std_logic := '0';
+
+signal MUX_error_S : std_logic := '0';
+
+signal enable_waveform_S : std_logic := '0';
+signal wave_notpresent_S : std_logic := '0';
+signal wave_read_S : std_logic := '0';
+
+signal pulsedetect_S : std_logic_vector(0 to NROFADCS-1);
+signal pulsedetectmux_S : std_logic := '0';
+signal pulsefrequency_S : std_logic_vector (31 downto 0);
+
+signal sysmon_address_S : std_logic_vector(6 downto 0);
+signal sysmon_address_saved_S : std_logic_vector(6 downto 0);
+signal temperature_S : std_logic_vector (7 downto 0) := (others => '0');
+signal testword0_S : std_logic_vector(35 downto 0);
+signal testword1_S : std_logic_vector(35 downto 0);
+
+constant DEBUG : std_logic := '0';
+begin
+
+
+timestampcounter: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if superburst_start='1' then
+ timestampcounter_S <= (others => '0');
+ superburstnumber_S <= superburst_received;
+ else
+ timestampcounter_S <= timestampcounter_S+1;
+ end if;
+ end if;
+end process;
+
+
+gendebug2: if DEBUG='0' generate
+
+
+FEE_slowcontrol_packet_receiver1: FEE_slowcontrol_packet_receiver port map(
+ clock => clock,
+ reset => reset,
+ enable => startupready,
+ packet_data_in => packet_in_data,
+ packet_data_present => packet_in_present,
+ packet_data_read => packet_in_read_S,
+ byte_data => slowcontrol_byte_data_S,
+ byte_write => slowcontrol_byte_write_S,
+ byte_request => slowcontrol_byte_request_S,
+ data_error => slowcontrol_error1_S,
+ overflow => receive_overflow_S);
+packet_in_read <= packet_in_read_S;
+
+FEE_board_slowcontrol1: FEE_board_slowcontrol port map(
+ clock => clock,
+ reset => reset,
+ enable => startupready,
+ overflow_in => receive_overflow_S,
+ request_init => request_init,
+ byte_data => slowcontrol_byte_data_S,
+ byte_write => slowcontrol_byte_write_S,
+ byte_request => slowcontrol_byte_request_S,
+ slowcontrol_read => slowcontrol_read_S,
+ slowcontrol_notpresent => slowcontrol_notpresent_S,
+ slowcontrol_data => slowcontrol_data_S,
+ slowcontrol_address => slowcontrol_address_S,
+ slowcontrol_reply => slowcontrol_reply_S,
+ board_status_A => board_status_A_S,
+ board_status_B => board_status_B_S,
+ board_status_C => board_status_C_S,
+ board_status_D => board_status_D_S,
+ board_control_A => board_control_A_S,
+ board_control_B => board_control_B_S,
+ board_control_C => board_control_C_S,
+ board_control_D => board_control_D_S,
+ overflow_out => slowcontrol_overflow_S);
+
+
+
+slowcontrolhandling: process(clock)
+variable clear_timeout_V : integer range 0 to 15 := 15;
+begin
+ if (rising_edge(clock)) then
+ if (clear_errors_S='1') or (reset='1') then
+ error_occurred_S <= (others => '0');
+ else
+ if rxNotInTable='1' then
+ error_occurred_S(0) <= '1';
+ end if;
+ if slowcontrol_error1_S='1' then
+ error_occurred_S(1) <= '1';
+ end if;
+ if (slowcontrol_overflow_S='1') then
+ error_occurred_S(2) <= '1';
+ end if;
+-- if cf_error_S='1' then
+-- error_occurred_S(3) <= '1';
+-- end if;
+ if MUX_error_S='1' then
+ error_occurred_S(4) <= '1';
+ end if;
+-- if (rxAsyncDataOverflow_S='1') then
+-- error_occurred_S(5) <= '1';
+-- end if;
+ if overflow_S='1' then
+ error_occurred_S(6) <= '1';
+ end if;
+ error_occurred_S(7) <= not enable_data;
+ end if;
+ end if;
+end process;
+
+
+
+
+clear_errors_S <= board_control_A_S(2);
+enable_waveform_S <= board_control_A_S(3);
+pulsedetectmux_S <= pulsedetect_S(conv_integer(unsigned(board_control_A_S(20 downto 16))));
+sysmon_reset <= '1' when (reset='1') or (board_control_A_S(21)='1') else '0';
+sysmon_address_S(1 downto 0) <= board_control_A_S(23 downto 22);
+sysmon_address_S(6 downto 2) <= (others => '0');
+
+checksysmonchange: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if sysmon_address_S(1 downto 0)/=sysmon_address_saved_S(1 downto 0) then
+ sysmon_read <= '1';
+ else
+ sysmon_read <= '0';
+ end if;
+ sysmon_address_saved_S(1 downto 0) <= sysmon_address_S(1 downto 0);
+ end if;
+end process;
+sysmon_address <= sysmon_address_S;
+
+
+board_status_A_S <= board_control_A_S;
+
+board_status_B_S(0) <= '0';
+board_status_B_S(1) <= enable_data;
+board_status_B_S(3 downto 2) <= (others => '0');
+board_status_B_S(5 downto 4) <= sysmon_address_saved_S(1 downto 0);
+board_status_B_S(15 downto 6) <= sysmon_data(15 downto 6);
+board_status_B_S(23 downto 16) <= errorbyte_in;
+board_status_B_S(31 downto 24) <= temperature_S;
+errorbyte_out <= error_occurred_S;
+
+
+board_status_D_S(31 downto 0) <= pulsefrequency_S;
+
+
+FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms port map(
+ clock => clock,
+ reset => reset,
+ superburstnumber => superburstnumber_S,
+ timestampcounter => timestampcounter_S,
+ ADCdata => ADCdata,
+ enable_data => enable_data,
+ slowcontrol_byte_data => slowcontrol_byte_data_S,
+ slowcontrol_byte_write => slowcontrol_byte_write_S,
+ slowcontrol_byte_request => slowcontrol_byte_request_S,
+ pulsedata_out => pulsedata_out_S,
+ pulsedata_read => pulsedata_read_S,
+ pulsedata_available => pulsedata_available_S,
+ pulsedata_inpipe => pulsedata_inpipe_S,
+ pileupdata_out => pileupdata_out_S,
+ pileupdata_read => pileupdata_read_S,
+ pileupdata_available => pileupdata_available_S,
+ pileupdata_inpipe => pileupdata_inpipe_S,
+ pulsedetect => pulsedetect_S,
+ overflow => overflow_S,
+ testindex => testindex,
+ testword0 => testword0,
+ testword1 => testword1,
+ testword2 => testword2
+ );
+
+pulse_notpresent_S <= not pulsedata_available_S;
+FEE_combine_data1: FEE_combine_data port map(
+ clock => clock,
+ reset => reset,
+ -- signals to/from data fifo :
+ pulse_data => pulsedata_out_S,
+ pulse_notpresent => pulse_notpresent_S,
+ pulse_inpipe => pulsedata_inpipe_S,
+ pulse_read => pulsedata_read_S,
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data => slowcontrol_data_S,
+ slowcontrol_address => slowcontrol_address_S,
+ slowcontrol_reply => slowcontrol_reply_S,
+ slowcontrol_notpresent => slowcontrol_notpresent_S,
+ slowcontrol_read => slowcontrol_read_S,
+ -- signals to/from waveform fifo
+ wave_data => pileupdata_out_S,
+ wave_notpresent => wave_notpresent_S,
+ wave_inpipe => pileupdata_inpipe_S,
+ wave_read => wave_read_S,
+ -- signals to/from fiber module
+ packet_data_out => packet_out_data,
+ packet_firstword => packet_out_first,
+ packet_lastword => packet_out_last,
+ packet_datawrite => packet_out_write,
+ packet_fifofull => packet_out_fifofull,
+ error => MUX_error_S,
+ testword0 => open);
+
+wave_notpresent_S <= '1' when (pileupdata_available_S='0') or (enable_waveform_S='0') else '0';
+pileupdata_read_S <= '1' when (enable_waveform_S='0') and (pileupdata_available_S='1') else wave_read_S;
+
+--gtpClk_I : IBUFDS port map(
+-- O => gtpClk_S,
+-- I => gtpClkP0,
+-- IB => gtpClkN0);
+
+--GTX_refclock: IBUFDS_GTXE1 port map(
+-- O => gtpClk_S,
+-- ODIV2 => open,
+-- CEB => '0',
+-- I => MGTREFCLK_P,
+-- IB => MGTREFCLK_N);
+end generate; --debug
+
+gendebug3: if DEBUG='0' generate
+FEE_measure_frequency1: FEE_measure_frequency port map(
+ clock => clock,
+ pulse => pulsedetectmux_S,
+ onesecondpulse => onesecondpulse,
+ frequency => pulsefrequency_S);
+end generate; -- debug
+
+--TMP104module1: TMP104module port map(
+-- clock => clock,
+-- reset => reset,
+-- smaart_in => smaart_in,
+-- smaart_out => smaart_out,
+-- temperature => temperature_S);
+--testword0(34 downto 0) <= testword0_S(34 downto 0);
+--testword0(35) <= enable_waveform_S;
+
+--testword1(15 downto 0) <= packet_in_data(31 downto 16);
+--testword1(16) <= packet_in_present;
+--testword1(17) <= packet_in_read_S;
+--testword1(18) <= slowcontrol_byte_write_S;
+--testword1(19) <= slowcontrol_byte_request_S;
+--testword1(27 downto 20) <= slowcontrol_byte_data_S;
+--testword1(28) <= slowcontrol_error1_S;
+--testword1(29) <= receive_overflow_S;
+--testword1(34 downto 30) <= testword1_S(4 downto 0);
+--testword1(35) <= '1' when testword1_S(23 downto 0)=x"000000" else '0';
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd b/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd
new file mode 100644
index 0000000..e350749
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd
@@ -0,0 +1,158 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 27-01-2012
+-- Module Name: FEE_baselinefollower_eventdetector
+-- Description: Baseline reconstruction, pulse detection
+-- Modifications:
+-- 16-09-2014 name changed from baselinefollower_eventdetector to FEE_baselinefollower_eventdetector
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+----------------------------------------------------------------------------------
+-- FEE_baselinefollower_eventdetector
+-- Baseline reconstruction, pulse detection
+--
+-- generics
+-- ADCBITS : number of ADC bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- enable : enable detection of pulses
+-- ADCdata : ADC sampling data
+-- threshold : threshold above baseline for start of pulse
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+--
+-- outputs
+-- baseline : resulting corrected baseline
+-- ADC_delayed : ADC data delayed with 1 clock
+-- ADC_minus_baseline : ADC values delayed minus baseline
+-- baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
+-- pulse_active : the ADC-signal exceeds the trigger-level
+-- pulse_rising : the pulse has not yet reached its maximum
+-- max_data : maximum value of waveform
+--
+-- components
+-- IIRfilter_1order : IIR filter for the baseline
+-- FEE_eventdetector : detection of pulse
+--
+----------------------------------------------------------------------------------
+
+
+
+entity FEE_baselinefollower_eventdetector is
+ generic (
+ ADCBITS : natural := 16;
+ BWBITS : natural := 10
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold : in std_logic_vector((ADCBITS-1) downto 0);
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ baseline : out std_logic_vector((ADCBITS-1) downto 0);
+ ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
+ ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
+ baseline_inhibit : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end FEE_baselinefollower_eventdetector;
+
+architecture Behavioral of FEE_baselinefollower_eventdetector is
+
+component iirfilter_1order_selectBW is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector ((ADCBITS-1) downto 0);
+ BWidx : in std_logic_vector (2 downto 0);
+ inhibit : in std_logic;
+ data_out : out std_logic_vector ((ADCBITS-1) downto 0));
+end component;
+
+component FEE_eventdetector is
+ generic (
+ ADCBITS : natural := ADCBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector (ADCBITS downto 0);
+ threshold : in std_logic_vector ((ADCBITS-1) downto 0);
+ maxabovebaseline : in std_logic_vector (3 downto 0);
+ baseline_freeze : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end component;
+
+signal ADC_delayed_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
+signal baseline_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
+signal ADC_minusbaseline_S : std_logic_vector(ADCBITS downto 0) := (others => '0');
+signal baseline_inhibit_S : std_logic := '0';
+signal pulse_active_S : std_logic := '0';
+signal enable_S : std_logic := '0';
+
+
+
+begin
+
+
+
+baselinefilter: iirfilter_1order_selectBW port map(
+ clock => clock,
+ reset => reset,
+ data_in => ADC_delayed_S,
+ BWidx => IIRfilterBW(2 downto 0),
+ inhibit => baseline_inhibit_S,
+ data_out => baseline_S);
+
+ADC_minusbaseline_S <= conv_std_logic_vector(conv_integer(signed('0' & ADCdata)) - conv_integer(signed('0' & baseline_S)),(ADCBITS+1));
+
+FEE_eventdetector1: FEE_eventdetector port map(
+ clock => clock,
+ reset => reset,
+ data_in => ADC_minusbaseline_S,
+ threshold => threshold,
+ maxabovebaseline => maxabovebaseline,
+ baseline_freeze => baseline_inhibit_S,
+ pulse_active => pulse_active_S,
+ pulse_rising => pulse_rising,
+ max_data => max_data);
+pulse_active <= pulse_active_S when enable_S='1' else '0';
+
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ ADC_delayed_S <= ADCdata;
+ if pulse_active_S='0' then
+ enable_S <= enable;
+ end if;
+ end if;
+end process;
+
+baseline <= baseline_S;
+baseline_inhibit <= baseline_inhibit_S;
+ADC_delayed <= ADC_delayed_S;
+ADC_minus_baseline <= ADC_minusbaseline_S;
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd b/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd
new file mode 100644
index 0000000..2059f59
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd
@@ -0,0 +1,274 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 15-09-2014
+-- Module Name: FEE_board_slowcontrol
+-- Description: Handles FEE board slowcontrol
+-- 22-09-2014 single clock
+-- 01-10-2014 request_init added: request initialize FEE
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_board_slowcontrol
+-- Handles slow control for the FEE board control and status registers.
+--
+-- The slow control commands are receives byte-wise: first 8-bits address, then 4 bytes data, MSB first.
+-- There are four control registers.
+--
+-- The status registers are requested with a request signal and the same 8-bits address, but no data bytes.
+-- There are also four status registers.
+-- These registers are buffered in a fifo.
+--
+-- The slow control output to be send to the Data Concentrator consist of a 8-bits address, a 32 bits data word and a reply bit.
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock input
+-- reset : reset
+-- enable : enable module
+-- overflow_in : overflow from the fiber packet receiver; this will issue an error slow command to be send to the DC
+-- request_init : send a request to the DC to initialize all registers
+-- byte_data : 8-bits slowcontrol data:
+-- Byte0 : 8-bits address, lowest 2 bits selects register A,B,C or D
+-- Byte1,2,3,4 : 32-bits data, MSB first
+-- byte_write : write signal for byte-data
+-- byte_request : request signal for reading data
+-- slowcontrol_read : read signal for the slowcontrol output fifo
+-- board_status_A : status register A
+-- board_status_B : status register B
+-- board_status_C : status register C
+-- board_status_D : status register D
+--
+-- Outputs:
+-- slowcontrol_notpresent : empty signal
+-- slowcontrol_data : slowcontrol 32-bits data
+-- slowcontrol_address : slowcontrol 8-bits address
+-- slowcontrol_reply : slowcontrol reply bit
+-- board_control_A : control register A
+-- board_control_B : control register B
+-- board_control_C : control register C
+-- board_control_D : control register D
+-- overflow_out : buffer overflow form slowcontrol fifo or fiber packet buffer
+--
+-- Components:
+-- sync_fifo_512x41 : fifo for the slowcontrol commands
+--
+----------------------------------------------------------------------------------
+
+entity FEE_board_slowcontrol is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ overflow_in : in std_logic;
+ request_init : in std_logic;
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ slowcontrol_read : in std_logic;
+ slowcontrol_notpresent : out std_logic;
+ slowcontrol_data : out std_logic_vector (31 downto 0);
+ slowcontrol_address : out std_logic_vector (7 downto 0);
+ slowcontrol_reply : out std_logic;
+ board_status_A : in std_logic_vector(31 downto 0);
+ board_status_B : in std_logic_vector(31 downto 0);
+ board_status_C : in std_logic_vector(31 downto 0);
+ board_status_D : in std_logic_vector(31 downto 0);
+ board_control_A : out std_logic_vector(31 downto 0);
+ board_control_B : out std_logic_vector(31 downto 0);
+ board_control_C : out std_logic_vector(31 downto 0);
+ board_control_D : out std_logic_vector(31 downto 0);
+ overflow_out : out std_logic
+ );
+end FEE_board_slowcontrol;
+
+architecture Behavioral of FEE_board_slowcontrol is
+
+component sync_fifo_512x41
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(40 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(40 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+signal enable_S : std_logic;
+
+signal slowpacketvalid_S : std_logic := '0';
+signal slowcontrol_data_S : std_logic_vector (31 downto 0);
+signal slowcontrol_address_S : std_logic_vector (7 downto 0);
+signal slowcontrol_reply_S : std_logic := '0';
+signal slowcontrol_write_S : std_logic;
+signal slowcontrol_fifofull_S : std_logic;
+
+signal board_control_A_S : std_logic_vector (31 downto 0) := x"00000000";
+signal board_control_B_S : std_logic_vector (31 downto 0) := x"00000000";
+signal board_control_C_S : std_logic_vector (31 downto 0) := x"00000000";
+signal board_control_D_S : std_logic_vector (31 downto 0) := x"00000000";
+
+
+signal slowcontrol_read_S : std_logic := '0';
+signal slowcontrol_read_after1clk_S : std_logic := '0';
+signal slowcontrol_fifoempty_S : std_logic := '0';
+
+signal register_buf_S : std_logic_vector (31 downto 0);
+signal byte_idx_S : integer range 0 to 4 := 0;
+signal overflow1_S : std_logic := '0';
+signal overflow2_S : std_logic := '0';
+signal overflow_in_S : std_logic := '0';
+signal selected_S : std_logic := '0';
+signal selected_reg_s : std_logic_vector (1 downto 0);
+signal request_init1_S : std_logic := '0';
+signal request_init_S : std_logic := '0';
+
+signal fifo_in_S : std_logic_vector (40 downto 0);
+signal fifo_out_S : std_logic_vector (40 downto 0);
+
+begin
+
+board_control_A <= board_control_A_S;
+board_control_B <= board_control_B_S;
+board_control_C <= board_control_C_S;
+board_control_D <= board_control_D_S;
+overflow_out <= '1' when (overflow1_S='1') or (overflow2_S='1') else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ enable_S <= enable;
+ end if;
+end process;
+
+read_bytewise_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ slowcontrol_write_S <= '0';
+ if (reset='1') or (enable_S='0') then
+ byte_idx_S <= 0;
+ selected_S <= '0';
+ overflow1_S <= '0';
+ overflow2_S <= '0';
+ request_init1_S <= '0';
+ else
+ if (overflow_in='1') and (overflow_in_S='0') then
+ overflow1_S <= '1';
+ end if;
+ if (request_init='1') and (request_init_S='0') then
+ request_init1_S <= '1';
+ end if;
+ if byte_idx_S=0 then
+ if (byte_write='1') then
+ if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
+ selected_S <= '1';
+ selected_reg_S <= byte_data(1 downto 0);
+ else
+ selected_S <= '0';
+ end if;
+ byte_idx_S <= 1;
+ elsif byte_request='1' then
+ if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
+ case byte_data(1 downto 0) is
+ when "00" => slowcontrol_data_S <= board_status_A;
+ when "01" => slowcontrol_data_S <= board_status_B;
+ when "10" => slowcontrol_data_S <= board_status_C;
+ when "11" => slowcontrol_data_S <= board_status_D;
+ when others =>
+ end case;
+ slowcontrol_address_S <= byte_data;
+ slowcontrol_reply_S <= '1';
+ slowcontrol_write_S <= '1';
+ if slowcontrol_fifofull_S='1' then
+ overflow2_S <= '1';
+ end if;
+ end if;
+ selected_S <= '0';
+ byte_idx_S <= 0;
+ elsif request_init1_S='1' then
+ selected_S <= '0';
+ if (slowcontrol_fifofull_S='0') then -- send request init FEE command
+ request_init1_S <= '0';
+ slowcontrol_data_S <= (others => '0');
+ slowcontrol_address_S <= ADDRESS_FEE_REQUESTALLREGISTERS;
+ slowcontrol_reply_S <= '1';
+ slowcontrol_write_S <= '1';
+ end if;
+ else
+ selected_S <= '0';
+ if (overflow1_S='1') or (overflow2_S='1') then
+ if (slowcontrol_fifofull_S='0') then -- send error slowcontrol command
+ overflow1_S <= '0';
+ overflow2_S <= '0';
+ slowcontrol_data_S <= (others => '0');
+ slowcontrol_address_S <= ADDRESS_FEE_SLOWCONTROLERROR;
+ slowcontrol_reply_S <= '1'; -- ??
+ slowcontrol_write_S <= '1';
+ end if;
+ end if;
+ end if;
+ elsif byte_request='1' then -- unexpected : synchronize
+ byte_idx_S <= 0;
+ else
+ if selected_S='1' then
+ case byte_idx_S is
+ when 1 =>
+ register_buf_S(31 downto 24) <= byte_data;
+ when 2 =>
+ register_buf_S(23 downto 16) <= byte_data;
+ when 3 =>
+ register_buf_S(15 downto 8) <= byte_data;
+ when 4 =>
+ case selected_reg_S is
+ when "00" => board_control_A_S <= register_buf_S(31 downto 8) & byte_data;
+ when "01" => board_control_B_S <= register_buf_S(31 downto 8) & byte_data;
+ when "10" => board_control_C_S <= register_buf_S(31 downto 8) & byte_data;
+ when "11" => board_control_D_S <= register_buf_S(31 downto 8) & byte_data;
+ when others =>
+ end case;
+ when others =>
+ end case;
+ end if;
+ if byte_idx_S<4 then
+ byte_idx_S <= byte_idx_S+1;
+ else
+ byte_idx_S <= 0;
+ end if;
+ end if;
+ end if;
+ overflow_in_S <= overflow_in;
+ request_init_S <= request_init;
+ end if;
+end process;
+
+fifo_in_S <= slowcontrol_reply_S & slowcontrol_address_S & slowcontrol_data_S;
+fifo1: sync_fifo_512x41 port map(
+ rst => reset,
+ clk => clock,
+ din => fifo_in_S,
+ wr_en => slowcontrol_write_S,
+ rd_en => slowcontrol_read,
+ dout => fifo_out_S,
+ full => slowcontrol_fifofull_S,
+ empty => slowcontrol_notpresent);
+
+slowcontrol_data <= fifo_out_S(31 downto 0);
+slowcontrol_address <= fifo_out_S(39 downto 32);
+slowcontrol_reply <= fifo_out_S(40);
+
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd b/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd
new file mode 100644
index 0000000..d186789
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd
@@ -0,0 +1,574 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 28-02-2012
+-- Module Name: FEE_combine_data
+-- Description: Write Front End Data, waveforms and Slow-control commands to fiber to Multiplexer
+-- Modifications:
+-- 09-09-2014 New data formats without hamming code
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 Inpipe signals, better sorting between waveforms and single pulse packets
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_combine_data
+-- Module in the Front End Electronics that builds packets from Pulse data, waveforms and
+-- Slow-control data to send to the fiber module.
+--
+-- The pulse data consists of three successive 36-bits words with bits 35..34 the index:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--
+-- The Slow-control commands consists of address and data plus a bit to indicate reply.
+-- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent
+--
+-- The waveform data consists of 36-bits data with variable length :
+-- bits(35..32)="0000" : bits(31..16)=superburstnumber, bits(31..0)=timestamp inside superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--
+--
+-- The resulting data packets : 4 32-bit words, with CRC8 in last word
+-- 0xDA ADCnumber(7..0) superburstnumber(15..0)
+-- 0000 energy(15..0)
+-- CF_before(15..0) CF_after(15..0)
+-- timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+-- 0xAF ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) 0x00 statusbyte(7..0)
+-- 0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+-- 0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+-- .........
+-- 1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+-- or
+-- 0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock input
+-- reset : synchronous reset
+-- pulse_data : data with results from Feature Extraction
+-- pulse_notpresent : pulse data not available (empty signal from connected fifo)
+-- pulse_inpipe : more single pulse data on its way
+-- slowcontrol_data : slow-control command :
+-- first address-word with bit31=reply, bit30..28=101 and bit23..0=address then data-word
+-- slowcontrol_notpresent : slow-control not available (empty signal from fifo)
+-- wave_data : data with pileup waveforms from pileup multiplexer
+-- wave_notpresent : pileup waveform not available (empty signal from fifo)
+-- wave_inpipe : more wave data on its way
+-- packet_fifofull : connected fifo for packet data is full
+--
+-- Outputs:
+-- pulse_read : read signal for pulse data
+-- slowcontrol_read : read signal for slow-control data
+-- wave_read : read signal for pileup waveform data
+-- packet_data_out : packet data to fiber module
+-- packet_firstword : first 32-bit data word of a packet
+-- packet_lastword : last 32-bit data word of a packet
+-- packet_datawrite : write signal for packet data
+-- error : error on incomming data (no sequential index)
+--
+-- Components:
+-- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words
+-- the check is not used in this module
+--
+----------------------------------------------------------------------------------
+
+entity FEE_combine_data is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ -- signals to/from data fifo :
+ pulse_data : in std_logic_vector(35 downto 0);
+ pulse_notpresent : in std_logic; -- empty signal from fifo
+ pulse_inpipe : in std_logic;
+ pulse_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data : in std_logic_vector(31 downto 0);
+ slowcontrol_address : in std_logic_vector(7 downto 0);
+ slowcontrol_reply : in std_logic;
+ slowcontrol_notpresent : in std_logic; -- empty signal from fifo
+ slowcontrol_read : out std_logic; -- read from normal fifo
+ -- signals to/from waveform fifo
+ wave_data : in std_logic_vector(35 downto 0);
+ wave_notpresent : in std_logic; -- empty signal from fifo
+ wave_inpipe : in std_logic;
+ wave_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from fiber module
+ packet_data_out : out std_logic_vector(31 downto 0);
+ packet_firstword : out std_logic;
+ packet_lastword : out std_logic;
+ packet_datawrite : out std_logic;
+ packet_fifofull : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0));
+end FEE_combine_data;
+
+architecture Behavioral of FEE_combine_data is
+
+component crc8_add_check32 is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;
+ crc_error : out std_logic
+ );
+end component;
+
+constant INPIPE_DELAY : integer := 255;
+
+type tx_state_type is (init,idle,data0,data1,data2,wave0,wave1,wave2,slow0);
+signal tx_state_S : tx_state_type := init;
+
+signal error_S : std_logic := '0';
+signal pulse_read0_S : std_logic := '0';
+signal pulse_read_S : std_logic := '0';
+
+signal crc8_data_in_S : std_logic_vector (31 downto 0);
+signal crc8_reset_S : std_logic := '0';
+signal crc8_clear_S : std_logic := '0';
+signal crc8_data_in_valid_S : std_logic := '0';
+signal crc8_data_in_last_S : std_logic := '0';
+signal crc8_writeword_S : std_logic := '0';
+signal crc8_data_out_valid_S : std_logic := '0';
+signal prev_crc8_data_out_valid_S : std_logic := '0';
+signal crc8_data_out_last_S : std_logic := '0';
+signal prev_crc8_data_out_last_S : std_logic := '0';
+
+signal crc8_lastword_S : std_logic_vector (31 downto 0);
+signal crc8_lastwrite_S : std_logic := '0';
+signal slowcontrol_read_S : std_logic := '0';
+
+signal packet_datawrite_S : std_logic;
+signal packet_lastword_S : std_logic;
+signal packet_firstword_S : std_logic := '1';
+
+
+--signal delay_inpipe_pulse_S : std_logic := '0';
+--signal delay_inpipe_wave_S : std_logic := '0';
+
+signal wave_read0_S : std_logic := '0';
+signal wave_read_S : std_logic := '0';
+signal superburst_S : std_logic_vector (15 downto 0);
+signal timestamp_S : std_logic_vector (15 downto 0);
+signal statusbyte_S : std_logic_vector (7 downto 0);
+--signal channel_S : std_logic_vector (7 downto 0);
+signal energy_S : std_logic_vector (15 downto 0);
+signal CF_before_S : std_logic_vector (15 downto 0);
+signal CF_after_S : std_logic_vector (15 downto 0);
+
+
+signal waveisolder_S : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+crc8_data_in_valid_S <= '1' when (crc8_writeword_S='1') and (packet_fifofull='0') else '0';
+crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
+crc8check: crc8_add_check32 port map(
+ clock => clock,
+ reset => crc8_reset_S,
+ data_in => crc8_data_in_S,
+ data_in_valid => crc8_data_in_valid_S,
+ data_in_last => crc8_data_in_last_S,
+ data_out => packet_data_out,
+ data_out_valid => crc8_data_out_valid_S,
+ data_out_last => crc8_data_out_last_S,
+ crc_error => open); -- only generate, no check
+
+packet_datawrite <= packet_datawrite_S;
+packet_datawrite_S <= '1' when ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) or
+ ((prev_crc8_data_out_valid_S='1') and (packet_fifofull='0')) else '0';
+packet_lastword <= packet_lastword_S;
+packet_lastword_S <= '1' when (crc8_data_out_last_S='1') or (prev_crc8_data_out_last_S='1') else '0';
+packet_firstword <= '1' when (packet_firstword_S='1') and (packet_datawrite_S='1') else '0';
+
+process(clock) -- process to determine firstword
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ packet_firstword_S <= '1';
+ else
+ if (packet_datawrite_S='1') and (packet_lastword_S='1') then
+ packet_firstword_S <= '1';
+ elsif packet_datawrite_S='1' then
+ packet_firstword_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(clock) -- process to freeze output of crc8 in case of packet_fifofull
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ prev_crc8_data_out_valid_S <= '0';
+ prev_crc8_data_out_last_S <= '0';
+ else
+ if ((crc8_data_out_valid_S='1') and (packet_fifofull='1')) then
+ prev_crc8_data_out_valid_S <= '1';
+ prev_crc8_data_out_last_S <= crc8_data_out_last_S;
+ elsif ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) then
+ prev_crc8_data_out_valid_S <= '0';
+ prev_crc8_data_out_last_S <= '0';
+ elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='0')) then
+ prev_crc8_data_out_last_S <= '0';
+ prev_crc8_data_out_valid_S <= '0';
+ elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='1')) then
+ prev_crc8_data_out_valid_S <= prev_crc8_data_out_valid_S;
+ prev_crc8_data_out_last_S <= prev_crc8_data_out_last_S;
+ end if;
+ end if;
+ end if;
+end process;
+
+wave_read <= wave_read_S;
+pulse_read <= pulse_read_S;
+slowcontrol_read <= slowcontrol_read_S;
+
+--process(clock)
+--variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
+--begin
+-- if rising_edge(clock) then
+-- if reset='1' then
+-- inpipe_counter_V := 0;
+-- delay_inpipe_pulse_S <= '0';
+-- else
+-- if (pulse_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
+-- (wave_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
+-- then
+-- inpipe_counter_V := INPIPE_DELAY;
+-- delay_inpipe_pulse_S <= '1';
+-- else
+-- if inpipe_counter_V/=0 then
+-- inpipe_counter_V := inpipe_counter_V-1;
+-- delay_inpipe_pulse_S <= '1';
+-- else
+-- delay_inpipe_pulse_S <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end if;
+--end process;
+--
+--process(clock)
+--variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
+--begin
+-- if rising_edge(clock) then
+-- if reset='1' then
+-- inpipe_counter_V := 0;
+-- delay_inpipe_wave_S <= '0';
+-- else
+-- if (wave_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
+-- (pulse_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
+-- then
+-- inpipe_counter_V := INPIPE_DELAY;
+-- delay_inpipe_wave_S <= '1';
+-- else
+-- if inpipe_counter_V/=0 then
+-- inpipe_counter_V := inpipe_counter_V-1;
+-- delay_inpipe_wave_S <= '1';
+-- else
+-- delay_inpipe_wave_S <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end if;
+--end process;
+
+waveisolder_S <= '1' when ((wave_data(31 downto 16)
+ crc8_data_in_last_S <= '0';
+ timeoutcounter_V := 0;
+ crc8_clear_S <= '1'; -- clear crc
+ error_S <= '0';
+ crc8_lastwrite_S <= '0';
+ tx_state_S <= idle;
+ when idle =>
+ timeoutcounter_V := 0;
+ crc8_clear_S <= '0';
+ if crc8_lastwrite_S='1' then
+ crc8_lastwrite_S <= '0';
+ crc8_data_in_S <= crc8_lastword_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '1';
+ else
+ crc8_data_in_last_S <= '0';
+ end if;
+
+ if pulse_read_S='1' then
+ if pulse_data(35 downto 34)="00" then
+ error_S <= '0';
+-- channel_S(0) <= pulse_data(33);
+ if pulse_data(32)='1' then
+ statusbyte_S <= STATBYTE_FEEPULSESKIPPED;
+ else
+ statusbyte_S <= x"00";
+ end if;
+ superburst_S <= pulse_data(31 downto 16);
+ timestamp_S <= pulse_data(15 downto 0);
+ tx_state_S <= data0;
+ else
+ error_S <= '1';
+ end if;
+ elsif slowcontrol_read_S='1' then
+ error_S <= '0';
+ tx_state_S <= slow0;
+ elsif wave_read_S='1' then
+ if wave_data(35 downto 32)="0000" then
+ superburst_S <= wave_data(31 downto 16);
+ timestamp_S <= wave_data(15 downto 0);
+ error_S <= '0';
+ tx_state_S <= wave0;
+ else
+ error_S <= '1';
+ end if;
+ else
+ end if;
+ when data0 =>
+ if pulse_read_S='1' then
+ timeoutcounter_V := 0;
+ if pulse_data(35 downto 34)="01" then
+-- channel_S(7 downto 0) <= pulse_data(23 downto 16);
+ energy_S <= pulse_data(15 downto 0);
+ crc8_data_in_S <= x"DA" & pulse_data(23 downto 16) & superburst_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when data1 =>
+ if pulse_read_S='1' then
+ timeoutcounter_V := 0;
+ if pulse_data(35 downto 34)="10" then
+ CF_before_S <= pulse_data(31 downto 16);
+ CF_after_S <= pulse_data(15 downto 0);
+ crc8_data_in_S <= x"0000" & energy_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data2;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when data2 =>
+ crc8_data_in_S <= CF_before_S & CF_after_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= timestamp_S & statusbyte_S & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+
+ when wave0 =>
+ if wave_read_S='1' then
+ timeoutcounter_V := 0;
+ if wave_data(35 downto 32)="0001" then
+ statusbyte_S <= wave_data(31 downto 24);
+-- channel_S <= wave_data(7 downto 0);
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave1;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when wave1 =>
+ crc8_data_in_S <= timestamp_S & x"00" & statusbyte_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave2;
+ when wave2 =>
+ if wave_read_S='1' then
+ timeoutcounter_V := 0;
+ if wave_data(35 downto 32)="0010" then -- 2 samples
+ crc8_data_in_S <= '0' & wave_data(30 downto 16) & '0' & wave_data(14 downto 0);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave2;
+ elsif wave_data(35 downto 32)="0100" then -- last sample
+ crc8_data_in_S <= '1' & wave_data(30 downto 16) & "1000" & x"000";
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '1';
+ crc8_lastwrite_S <= '0';
+ tx_state_S <= idle;
+ elsif wave_data(35 downto 32)="0101" then -- last 2 samples, one lastword with crc needed
+ crc8_data_in_S <= '0' & wave_data(30 downto 16) & '0' & wave_data(14 downto 0);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= x"0000" & x"80" & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+
+ when slow0 =>
+ crc8_data_in_S <= x"5c" & slowcontrol_address & slowcontrol_reply & "0000000" & slowcontrol_data(31 downto 24);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= slowcontrol_data(23 downto 0) & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+
+ when others =>
+ error_S <= '1';
+ tx_state_S <= init;
+ end case;
+ end if;
+ end if;
+ end if;
+end process datahandling;
+
+
+
+
+testword0(3 downto 0) <= pulse_data(35 downto 32);
+testword0(4) <= pulse_notpresent;
+testword0(5) <= pulse_inpipe;
+testword0(6) <= pulse_read_S;
+testword0(7) <= pulse_read0_S;
+
+testword0(11 downto 8) <= wave_data(35 downto 32);
+testword0(12) <= wave_notpresent;
+testword0(13) <= wave_inpipe;
+testword0(14) <= wave_read_S;
+testword0(15) <= wave_read0_S;
+
+testword0(19 downto 16) <=
+ x"0" when tx_state_S=init else
+ x"1" when tx_state_S=idle else
+ x"2" when tx_state_S=data0 else
+ x"3" when tx_state_S=data1 else
+ x"4" when tx_state_S=data2 else
+ x"5" when tx_state_S=wave0 else
+ x"6" when tx_state_S=wave1 else
+ x"7" when tx_state_S=wave2 else
+ x"8" when tx_state_S=slow0 else
+ x"f";
+
+testword0(20) <= waveisolder_S;
+testword0(21) <= crc8_reset_S;
+testword0(22) <= crc8_clear_S;
+testword0(23) <= crc8_data_in_valid_S;
+testword0(24) <= crc8_data_in_last_S;
+testword0(25) <= crc8_writeword_S;
+testword0(26) <= crc8_data_out_valid_S;
+testword0(27) <= crc8_data_out_last_S;
+testword0(28) <= '0';
+testword0(29) <= crc8_lastwrite_S;
+testword0(30) <= slowcontrol_notpresent;
+testword0(31) <= slowcontrol_read_S;
+testword0(32) <= packet_datawrite_S;
+testword0(33) <= packet_lastword_S;
+testword0(34) <= packet_firstword_S;
+
+
+testword0(35) <= error_S;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd b/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd
new file mode 100644
index 0000000..eb2e45b
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd
@@ -0,0 +1,782 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 30-01-2012
+-- Module Name: FEE_dual_pulse_waveform
+-- Description: Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs
+-- Modifications:
+-- 08-09-2014 Added: Constant Fraction values before and after zero-crossing
+-- 16-09-2014 name changed from dual_pulse_waveform to FEE_dual_pulse_waveform
+-- 22-09-2014 single clock
+-- 24-09-2014 enable_highgain and enable_lowgain inputs added
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_dual_pulse_waveform
+-- Module to detect pulses and outputs them as waveforms with single pulse or pile-up
+-- Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.
+-- If a pulse or pileup is detected at the low-gain input, the high-gain input is ignored.
+-- Pulses are detected: check if the ADC signal is above the adjustable tresshold.
+-- The samples are stored in buffer memory as waveform.
+-- The actual superburst-number and a timestamp within the superburst is added.
+-- Waveforms longer than an adjustable duration are treated as pileup waveforms,
+-- waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:
+-- The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
+-- The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
+-- From the single pulse waveforms the Constant Fraction values before and after the zero-crossing are put in the
+-- resulting packet, as well as two successive samples containing the maximum of the pulse.
+--
+--
+-- generics
+-- ADCBITS : number of ADC-bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+--
+-- inputs
+-- clock : clock
+-- reset : synchrounous reset
+-- enable : enable pulse detection
+-- superburstnumber : actual superburstnumber
+-- timestampcounter : timestampcounter within superburst
+-- ADCdata_highgain : ADC signal from the high-gain input
+-- ADCdata_lowgain : ADC signal from the low-gain input
+-- threshold_highgain : threshold above baseline for start of pulse (high gain)
+-- threshold_lowgain : threshold above baseline for start of pulse (low gain)
+-- enable_highgain : enable high gain input
+-- enable_lowgain : enable low gain input
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+-- minpulselength : number of samples below which the pulse is ignored
+-- pileuplength : number of samples above which the pulse is treated as pileup
+-- maxwavelength : maximum number of samples that can be saved in one waveform
+-- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
+-- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
+-- fullsize_wave_highgain : take waveforms with maximum size for highgain input
+-- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
+-- pulsedata_allowed : writing of pulse 36-bits data result allowed
+-- pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+-- pileupdata_allowed : writing of pileup 36-bits data result allowed
+-- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--
+-- outputs
+-- ADC_minus_baseline_highgain : baseline compensated signal from high gain input, signed
+-- ADC_minus_baseline_lowgain : baseline compensated signal from low gain input, signed
+-- pulsedata_write : write 36-bits pulse data result
+-- pulsedata_out : 36-bits pulse data result:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- pileupdata_write : write 36-bits pileup data result
+-- pileupdata_out : 36-bits pileup data result:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identification)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input
+-- overflow : pulse or pileup waveform is lost
+--
+-- Components:
+-- FEE_baselinefollower_eventdetector : baseline follower with detection of pulse
+-- FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred
+-- FEE_extract_pulse : perform maximum check and constant fraction
+-- FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added
+-- FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream
+-- FEE_wavemux2to1 : select next waveform, based on timestamp
+-- FEE_pulse2to1_pulse : combine hits from high and low gain ADC inputs to one data packet stream
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_dual_pulse_waveform is
+ generic (
+ ADCBITS : natural := 14;
+ BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ enable_highgain : in std_logic;
+ enable_lowgain : in std_logic;
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
+ ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
+ pulsedata_allowed : in std_logic;
+ pulsedata_almostfull : in std_logic;
+ pulsedata_write : out std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ pileupdata_write : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pulsedetect : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end FEE_dual_pulse_waveform;
+
+architecture Behavioral of FEE_dual_pulse_waveform is
+
+component FEE_baselinefollower_eventdetector is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold : in std_logic_vector((ADCBITS-1) downto 0);
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ baseline : out std_logic_vector((ADCBITS-1) downto 0);
+ ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
+ ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
+ baseline_inhibit : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end component;
+
+component FEE_pileup_check is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_highgain : in std_logic;
+ max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_highgain : in std_logic;
+ pulse_rising_highgain : in std_logic;
+ clipping_highgain : in std_logic;
+ ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_lowgain : in std_logic;
+ max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_lowgain : in std_logic;
+ pulse_rising_lowgain : in std_logic;
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ pulse_valid_highgain : out std_logic;
+ singlepulse_highgain : out std_logic;
+ pileuppulse_highgain : out std_logic;
+ clearpulse_highgain : out std_logic;
+ integral_highgain : out std_logic_vector(15 downto 0);
+ pulse_valid_lowgain : out std_logic;
+ singlepulse_lowgain : out std_logic;
+ pileuppulse_lowgain : out std_logic;
+ clearpulse_lowgain : out std_logic;
+ integral_lowgain : out std_logic_vector(15 downto 0);
+ superburst : out std_logic_vector(15 downto 0);
+ timestamp : out std_logic_vector(15 downto 0);
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+
+component FEE_extract_pulse is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ integral : in std_logic_vector(15 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ pulse_write : out std_logic;
+ pulse_superburst : out std_logic_vector(15 downto 0);
+ pulse_timestamp : out std_logic_vector(15 downto 0);
+ pulse_skipped : out std_logic;
+ pulse_energy : out std_logic_vector(15 downto 0);
+ pulse_CF1 : out std_logic_vector(15 downto 0);
+ pulse_CF2 : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+
+component FEE_pulsewaveform_buffer is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ superburst : in std_logic_vector(15 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_waveform_to_36bits is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ overflow_in : in std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_write : out std_logic;
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ error : out std_logic;
+ overflow_out : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_wavemux2to1 is
+ generic(
+ TIMEOUTBITS : natural := 16
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_pulse2to1_pulse is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ channel : in std_logic_vector(7 downto 0);
+ pulse1_write : in std_logic;
+ pulse1_superburst : in std_logic_vector(15 downto 0);
+ pulse1_timestamp : in std_logic_vector(15 downto 0);
+ pulse1_skipped : in std_logic;
+ pulse1_energy : in std_logic_vector(15 downto 0);
+ pulse1_CF1 : in std_logic_vector(15 downto 0);
+ pulse1_CF2 : in std_logic_vector(15 downto 0);
+ pulse2_write : in std_logic;
+ pulse2_superburst : in std_logic_vector(15 downto 0);
+ pulse2_timestamp : in std_logic_vector(15 downto 0);
+ pulse2_skipped : in std_logic;
+ pulse2_energy : in std_logic_vector(15 downto 0);
+ pulse2_CF1 : in std_logic_vector(15 downto 0);
+ pulse2_CF2 : in std_logic_vector(15 downto 0);
+ pulse_skipped : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_almostfull : in std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+
+
+
+signal pulsedetect_S : std_logic := '0';
+
+signal pulse_active_highgain_S : std_logic := '0';
+signal pulse_rising_highgain0_S : std_logic := '0';
+signal pulse_rising_highgain_S : std_logic := '0';
+signal pulse_active_lowgain_S : std_logic := '0';
+signal pulse_rising_lowgain0_S : std_logic := '0';
+signal pulse_rising_lowgain_S : std_logic := '0';
+signal ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);
+
+signal pulse_valid_highgain0_S : std_logic := '0';
+signal pulse_valid_highgain_S : std_logic := '0';
+signal singlepulse_highgain_S : std_logic := '0';
+signal pileuppulse_highgain_S : std_logic := '0';
+signal clearpulse_highgain_S : std_logic := '0';
+signal integral_highgain_S : std_logic_vector(15 downto 0);
+signal max_data_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal clipping_highgain_S : std_logic := '0';
+
+signal baseline_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal baseline_inhibit_highgain_S : std_logic := '0';
+signal baseline_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal baseline_inhibit_lowgain_S : std_logic := '0';
+
+signal pulse_valid_lowgain0_S : std_logic := '0';
+signal pulse_valid_lowgain_S : std_logic := '0';
+signal singlepulse_lowgain_S : std_logic := '0';
+signal pileuppulse_lowgain_S : std_logic := '0';
+signal clearpulse_lowgain_S : std_logic := '0';
+signal integral_lowgain_S : std_logic_vector(15 downto 0);
+signal max_data_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal superburst_S : std_logic_vector(15 downto 0);
+signal timestamp_S : std_logic_vector(15 downto 0);
+
+signal adcnumber_highgain_S : std_logic_vector(7 downto 0);
+signal data_out_highgain_S : std_logic_vector(35 downto 0);
+signal data_out_available_highgain_S : std_logic := '0';
+signal data_out_read_highgain_S : std_logic := '0';
+signal overflow_highgain_S : std_logic := '0';
+signal overflow_hg_S : std_logic := '0';
+signal pileupdata1_out_S : std_logic_vector(35 downto 0);
+signal pileupdata1_write_S : std_logic := '0';
+signal pileupdata1_allowed_S : std_logic := '0';
+
+signal pulse_write_highgain_S : std_logic;
+signal pulse_superburst_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_timestamp_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_skipped_highgain_S : std_logic;
+signal pulse_energy_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF1_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF2_highgain_S : std_logic_vector(15 downto 0);
+
+signal pulse_write_lowgain_S : std_logic;
+signal pulse_superburst_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_timestamp_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_skipped_lowgain_S : std_logic;
+signal pulse_energy_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF1_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF2_lowgain_S : std_logic_vector(15 downto 0);
+
+
+
+signal adcnumber_lowgain_S : std_logic_vector(7 downto 0);
+signal data_out_lowgain_S : std_logic_vector(35 downto 0);
+signal data_out_available_lowgain_S : std_logic := '0';
+signal data_out_read_lowgain_S : std_logic := '0';
+signal overflow_lowgain_S : std_logic := '0';
+signal overflow_lg_S : std_logic := '0';
+signal pileupdata2_out_S : std_logic_vector(35 downto 0);
+signal pileupdata2_write_S : std_logic := '0';
+signal pileupdata2_allowed_S : std_logic := '0';
+
+signal pulsedata_out_S : std_logic_vector(35 downto 0);
+signal pulsedata_write_S : std_logic := '0';
+signal pileupdata_out_S : std_logic_vector(35 downto 0);
+signal pileupdata_write_S : std_logic := '0';
+
+signal error_pulse_S : std_logic := '0';
+signal error_pileup_S : std_logic := '0';
+signal error_to36_1_S : std_logic := '0';
+signal error_to36_2_S : std_logic := '0';
+
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword2_S : std_logic_vector(35 downto 0) := (others => '0');
+
+begin
+
+pulsedetect <= pulsedetect_S;
+pulsedetect_S <= '1' when (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1')
+ or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else '0';
+
+FEE_baselinefollower_eventdetector_highgain: FEE_baselinefollower_eventdetector port map(
+ clock => clock,
+ reset => reset,
+ enable => enable,
+ ADCdata => ADCdata_highgain,
+ threshold => threshold_highgain,
+ IIRfilterBW => IIRfilterBW,
+ maxabovebaseline => maxabovebaseline,
+ baseline => baseline_highgain_S,
+ ADC_delayed => open,
+ ADC_minus_baseline => ADC_minus_baseline_highgain0_S,
+ baseline_inhibit => baseline_inhibit_highgain_S,
+ pulse_active => pulse_active_highgain_S,
+ pulse_rising => pulse_rising_highgain0_S,
+ max_data => max_data_highgain_S);
+ADC_minus_baseline_highgain <= ADC_minus_baseline_highgain_S;
+
+FEE_baselinefollower_eventdetector_lowgain: FEE_baselinefollower_eventdetector port map(
+ clock => clock,
+ reset => reset,
+ enable => enable,
+ ADCdata => ADCdata_lowgain,
+ threshold => threshold_lowgain,
+ IIRfilterBW => IIRfilterBW,
+ maxabovebaseline => maxabovebaseline,
+ baseline => baseline_lowgain_S,
+ ADC_delayed => open,
+ ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,
+ baseline_inhibit => baseline_inhibit_lowgain_S,
+ pulse_active => pulse_active_lowgain_S,
+ pulse_rising => pulse_rising_lowgain0_S,
+ max_data => max_data_lowgain_S);
+ADC_minus_baseline_lowgain <= ADC_minus_baseline_lowgain_S;
+
+FEE_pileup_check1: FEE_pileup_check port map(
+ clock => clock,
+ reset => reset,
+ superburstnumber => superburstnumber,
+ timestampcounter => timestampcounter,
+ ADC_highgain => ADC_minus_baseline_highgain0_S,
+ enable_highgain => enable_highgain,
+ max_data_highgain => max_data_highgain_S,
+ pulse_active_highgain => pulse_active_highgain_S,
+ pulse_rising_highgain => pulse_rising_highgain0_S,
+ clipping_highgain => clipping_highgain_S,
+ ADC_lowgain => ADC_minus_baseline_lowgain0_S,
+ enable_lowgain => enable_lowgain,
+ max_data_lowgain => max_data_lowgain_S,
+ pulse_active_lowgain => pulse_active_lowgain_S,
+ pulse_rising_lowgain => pulse_rising_lowgain0_S,
+ minpulselength => minpulselength,
+ pileuplength => pileuplength,
+ maxwavelength => maxwavelength,
+ IdivMAX_discard => IdivMAX_discard,
+ IdivMAX_pileup => IdivMAX_pileup,
+ fullsize_wave_highgain => fullsize_wave_highgain,
+ fullsize_wave_lowgain => fullsize_wave_lowgain,
+ pulse_valid_highgain => pulse_valid_highgain0_S,
+ singlepulse_highgain => singlepulse_highgain_S,
+ pileuppulse_highgain => pileuppulse_highgain_S,
+ clearpulse_highgain => clearpulse_highgain_S,
+ integral_highgain => integral_highgain_S,
+ pulse_valid_lowgain => pulse_valid_lowgain0_S,
+ singlepulse_lowgain => singlepulse_lowgain_S,
+ pileuppulse_lowgain => pileuppulse_lowgain_S,
+ clearpulse_lowgain => clearpulse_lowgain_S,
+ integral_lowgain => integral_lowgain_S,
+ superburst => superburst_S,
+ timestamp => timestamp_S,
+ testword0 => open);
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if enable_highgain='1' then
+ pulse_valid_highgain_S <= pulse_valid_highgain0_S;
+ pulse_rising_highgain_S <= pulse_rising_highgain0_S;
+ else
+ pulse_valid_highgain_S <= '0';
+ pulse_rising_highgain_S <= '0';
+ end if;
+ ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;
+ if enable_lowgain='1' then
+ pulse_valid_lowgain_S <= pulse_valid_lowgain0_S;
+ pulse_rising_lowgain_S <= pulse_rising_lowgain0_S;
+ else
+ pulse_valid_lowgain_S <= '0';
+ pulse_rising_lowgain_S <= '0';
+ end if;
+ ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;
+ if pulse_active_highgain_S='1' then
+ if ADCdata_highgain((ADCBITS-1) downto (ADCBITS-4)) = "1111" then
+ clipping_highgain_S <= '1';
+ end if;
+ else
+ clipping_highgain_S <= '0';
+ end if;
+ end if;
+end process;
+
+FEE_extract_pulse1: FEE_extract_pulse port map(
+ clock => clock,
+ reset => reset,
+ cf_delay => cf_delay,
+ pulse_valid => pulse_valid_highgain_S,
+ pulse_rising => pulse_rising_highgain_S,
+ pulse_detected => singlepulse_highgain_S,
+ pileup_detected => pileuppulse_highgain_S,
+ clear_waveform => clearpulse_highgain_S,
+ data_in => ADC_minus_baseline_highgain_S,
+ integral => integral_highgain_S,
+ superburstnumber => superburstnumber,
+ timestamp => timestampcounter,
+ pulse_write => pulse_write_highgain_S,
+ pulse_superburst => pulse_superburst_highgain_S,
+ pulse_timestamp => pulse_timestamp_highgain_S,
+ pulse_skipped => pulse_skipped_highgain_S,
+ pulse_energy => pulse_energy_highgain_S,
+ pulse_CF1 => pulse_CF1_highgain_S,
+ pulse_CF2 => pulse_CF2_highgain_S);
+
+FEE_extract_pulse2: FEE_extract_pulse port map(
+ clock => clock,
+ reset => reset,
+ cf_delay => cf_delay,
+ pulse_valid => pulse_valid_lowgain_S,
+ pulse_rising => pulse_rising_lowgain_S,
+ pulse_detected => singlepulse_lowgain_S,
+ pileup_detected => pileuppulse_lowgain_S,
+ clear_waveform => clearpulse_lowgain_S,
+ data_in => ADC_minus_baseline_lowgain_S,
+ integral => integral_lowgain_S,
+ superburstnumber => superburstnumber,
+ timestamp => timestampcounter,
+ pulse_write => pulse_write_lowgain_S,
+ pulse_superburst => pulse_superburst_lowgain_S,
+ pulse_timestamp => pulse_timestamp_lowgain_S,
+ pulse_skipped => pulse_skipped_lowgain_S,
+ pulse_energy => pulse_energy_lowgain_S,
+ pulse_CF1 => pulse_CF1_lowgain_S,
+ pulse_CF2 => pulse_CF2_lowgain_S);
+
+FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(
+ clock => clock,
+ reset => reset,
+ pulse_valid => pulse_valid_highgain_S,
+ pulse_rising => pulse_rising_highgain_S,
+ pulse_detected => singlepulse_highgain_S,
+ pileup_detected => pileuppulse_highgain_S,
+ clear_waveform => clearpulse_highgain_S,
+ data_in => ADC_minus_baseline_highgain_S,
+ superburst => superburst_S,
+ timestamp => timestamp_S,
+ data_out => data_out_highgain_S,
+ data_out_read => data_out_read_highgain_S,
+ data_out_available => data_out_available_highgain_S,
+ overflow => overflow_highgain_S,
+ testword0 => testword1);
+
+FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(
+ clock => clock,
+ reset => reset,
+ pulse_valid => pulse_valid_lowgain_S,
+ pulse_rising => pulse_rising_lowgain_S,
+ pulse_detected => singlepulse_lowgain_S,
+ pileup_detected => pileuppulse_lowgain_S,
+ clear_waveform => clearpulse_lowgain_S,
+ data_in => ADC_minus_baseline_lowgain_S,
+ superburst => superburst_S,
+ timestamp => timestamp_S,
+ data_out => data_out_lowgain_S,
+ data_out_read => data_out_read_lowgain_S,
+ data_out_available => data_out_available_lowgain_S,
+ overflow => overflow_lowgain_S,
+ testword0 => open);
+
+FEE_pulse2to1_pulse1: FEE_pulse2to1_pulse port map(
+ clock => clock,
+ reset => reset,
+ channel => adcnumber,
+ pulse1_write => pulse_write_highgain_S,
+ pulse1_superburst => pulse_superburst_highgain_S,
+ pulse1_timestamp => pulse_timestamp_highgain_S,
+ pulse1_skipped => pulse_skipped_highgain_S,
+ pulse1_energy => pulse_energy_highgain_S,
+ pulse1_CF1 => pulse_CF1_highgain_S,
+ pulse1_CF2 => pulse_CF2_highgain_S,
+ pulse2_write => pulse_write_lowgain_S,
+ pulse2_superburst => pulse_superburst_lowgain_S,
+ pulse2_timestamp => pulse_timestamp_lowgain_S,
+ pulse2_skipped => pulse_skipped_lowgain_S,
+ pulse2_energy => pulse_energy_lowgain_S,
+ pulse2_CF1 => pulse_CF1_lowgain_S,
+ pulse2_CF2 => pulse_CF2_lowgain_S,
+ pulse_skipped => open,
+ data_out => pulsedata_out_S,
+ data_out_write => pulsedata_write_S,
+ data_out_almostfull => pulsedata_almostfull,
+ data_out_allowed => pulsedata_allowed);
+pulsedata_out <= pulsedata_out_S;
+pulsedata_write <= pulsedata_write_S;
+
+
+
+adcnumber_highgain_S <= adcnumber AND x"fe";
+FEE_waveform_to_36bits1: FEE_waveform_to_36bits port map(
+ clock => clock,
+ reset => reset,
+ adcnumber => adcnumber_highgain_S,
+ data_in => data_out_highgain_S,
+ data_in_available => data_out_available_highgain_S,
+ data_in_read => data_out_read_highgain_S,
+ overflow_in => overflow_highgain_S,
+ pileupdata_out => pileupdata1_out_S,
+ pileupdata_write => pileupdata1_write_S,
+ pileupdata_allowed => pileupdata1_allowed_S,
+ pileupdata_almostfull => pileupdata_almostfull,
+ overflow_out => overflow_hg_S,
+ error => error_to36_1_S,
+ testword0 => open);
+
+adcnumber_lowgain_S <= adcnumber OR x"01";
+FEE_waveform_to_36bits2: FEE_waveform_to_36bits port map(
+ clock => clock,
+ reset => reset,
+ adcnumber => adcnumber_lowgain_S,
+ data_in => data_out_lowgain_S,
+ data_in_available => data_out_available_lowgain_S,
+ data_in_read => data_out_read_lowgain_S,
+ overflow_in => overflow_lowgain_S,
+ pileupdata_out => pileupdata2_out_S,
+ pileupdata_write => pileupdata2_write_S,
+ pileupdata_allowed => pileupdata2_allowed_S,
+ pileupdata_almostfull => pileupdata_almostfull,
+ overflow_out => overflow_lg_S,
+ error => error_to36_2_S,
+ testword0 => open);
+overflow <= '1' when (overflow_highgain_S='1') or (overflow_lowgain_S='1') or (overflow_hg_S='1') or (overflow_lg_S='1') else '0';
+
+FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(
+ clock => clock,
+ reset => reset,
+ data1_in => pileupdata1_out_S,
+ data1_in_write => pileupdata1_write_S,
+ data1_in_available => data_out_available_highgain_S, -- '0',
+ data1_in_allowed => pileupdata1_allowed_S,
+ data2_in => pileupdata2_out_S,
+ data2_in_write => pileupdata2_write_S,
+ data2_in_available => data_out_available_lowgain_S, -- '0',
+ data2_in_allowed => pileupdata2_allowed_S,
+ data_out => pileupdata_out_S,
+ data_out_write => pileupdata_write_S,
+ data_out_available => open,
+ data_out_allowed => pileupdata_allowed,
+ error => error_pileup_S,
+ testword0 => testword2);
+pileupdata_out <= pileupdata_out_S;
+pileupdata_write <= pileupdata_write_S;
+
+-----------------------------------------------------------------
+-- tests:
+
+process(clock)
+variable prev_data_V : std_logic_vector(3 downto 0);
+begin
+ if rising_edge(clock) then
+ testword0_S(35) <= '0';
+ if pileupdata_write_S='1' then
+ case pileupdata_out_S(35 downto 32) is
+ when "0000" =>
+ if (prev_data_V/="0100") and (prev_data_V/="0101") then
+ testword0_S(35) <= '1';
+ end if;
+ when "0001" =>
+ if (prev_data_V/="0000") then
+ testword0_S(35) <= '1';
+ end if;
+ when "0010" =>
+ if (prev_data_V/="0001") and (prev_data_V/="0010") then
+ testword0_S(35) <= '1';
+ end if;
+ when "0100" =>
+ if (prev_data_V/="0010") then
+ testword0_S(35) <= '1';
+ end if;
+ when "0101" =>
+ if (prev_data_V/="0010") then
+ testword0_S(35) <= '1';
+ end if;
+ when others =>
+ testword0_S(35) <= '1';
+ end case;
+ prev_data_V := pileupdata_out_S(35 downto 32);
+ end if;
+ end if;
+end process;
+
+
+testword0 <= testword0_S;
+
+
+
+testword0_S(3 downto 0) <= data_out_highgain_S(35 downto 32);
+testword0_S(4) <= data_out_read_highgain_S;
+testword0_S(5) <= data_out_available_highgain_S;
+--testword0_S(6) <= overflow_highgain_S;
+testword0_S(9 downto 6) <= data_out_lowgain_S(35 downto 32);
+testword0_S(10) <= data_out_read_lowgain_S;
+testword0_S(11) <= data_out_available_lowgain_S;
+--testword0_S(13) <= overflow_lowgain_S;
+
+testword0_S(15 downto 12) <= pileupdata1_out_S(35 downto 32);
+testword0_S(16) <= pileupdata1_write_S;
+testword0_S(17) <= pileupdata1_allowed_S;
+testword0_S(18) <= pileupdata_almostfull;
+--testword0_S(21) <= overflow_hg_S;
+testword0_S(19) <= error_to36_1_S;
+
+testword0_S(23 downto 20) <= pileupdata2_out_S(35 downto 32);
+testword0_S(24) <= pileupdata2_write_S;
+testword0_S(25) <= pileupdata2_allowed_S;
+testword0_S(26) <= pileupdata_almostfull;
+--testword0_S(30) <= overflow_lg_S;
+testword0_S(27) <= error_to36_2_S;
+testword0_S(28) <= error_pileup_S;
+
+testword0_S(32 downto 29) <= pileupdata_out_S(35 downto 32);
+testword0_S(33) <= pileupdata_write_S;
+testword0_S(34) <= pileupdata_allowed;
+
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd b/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd
new file mode 100644
index 0000000..6a0d996
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd
@@ -0,0 +1,145 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 27-01-2012
+-- Module Name: FEE_eventdetector
+-- Description: Detect pulses by comparing ADC-signal with threshold
+-- Modifications:
+-- 16-09-2014: name changed from eventdetector to FEE_eventdetector
+-- 10-10-2014: threshold for end of pulse is half the normal threshold
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- FEE_eventdetector
+-- Detect pulses by comparing ADC-signal with threshold
+-- Generates inhibit for baseline IIR filter
+--
+--
+-- generics
+-- ADCBITS : number of ADC bits
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : signed ADC sampling data : minus baseline
+-- threshold : threshold above baseline
+-- maxabovebaseline : 2^ maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+--
+-- outputs
+-- baseline_freeze : detected signal pulse is busy : inhibit baseline IIR filter
+-- pulse_active : the ADC-signal exceeds the trigger-level
+-- pulse_rising : the pulse has not yet reached its maximum
+-- max_data : maximum value of waveform
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+entity FEE_eventdetector is
+ generic (
+ ADCBITS : natural := 14
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector (ADCBITS downto 0);
+ threshold : in std_logic_vector ((ADCBITS-1) downto 0);
+ maxabovebaseline : in std_logic_vector (3 downto 0);
+ baseline_freeze : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end FEE_eventdetector;
+
+architecture Behavioral of FEE_eventdetector is
+
+signal abovetriggerlevel_S : std_logic;
+signal freeze_extend_S : std_logic;
+signal pulsetoolong_S : std_logic;
+signal data_below_max_S : std_logic;
+signal counter_S : std_logic_vector(2**4-1 downto 0);
+signal max_data_S : std_logic_vector(ADCBITS downto 0);
+signal half_threshold_S : std_logic;
+
+begin
+
+max_data <= max_data_S(ADCBITS-1 downto 0); -- unsigned, should be always positive
+pulse_active <= abovetriggerlevel_S;
+
+baseline_freeze <= '1' when ((abovetriggerlevel_S='1') or (freeze_extend_S='1')) and (pulsetoolong_S='0') else '0';
+abovetriggerlevel_S <= '1'
+ when ((conv_integer(signed(data_in))>conv_integer(signed('0' & threshold))) and (half_threshold_S='0')) or
+ ((conv_integer(signed(data_in))>conv_integer(signed("00" & threshold(ADCBITS-1 downto 1)))) and (half_threshold_S='1'))
+ else '0';
+
+process(clock)
+variable counter_V : std_logic_vector(3 downto 0);
+--variable below_zero_V : std_logic;
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ freeze_extend_S <= '0';
+ else
+ if abovetriggerlevel_S='1' then
+ freeze_extend_S <= '1';
+ counter_V := (others => '0');
+ -- below_zero_V := '0';
+ elsif counter_V(counter_V'left)='0' then
+ -- if (conv_integer(signed(data_in))>0) and (below_zero_V='0') then
+ -- counter_V := (others => '0');
+ -- else
+ -- below_zero_V := '1';
+ counter_V := counter_V+1;
+ -- end if;
+ freeze_extend_S <= '1';
+ else
+ freeze_extend_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+pulsetoolong_S <= counter_S(conv_integer(unsigned(maxabovebaseline)));
+data_below_max_S <= '1' when conv_integer(signed(data_in))<=conv_integer(signed(max_data_S)) else '0';
+pulse_rising <= '1'
+ when (data_below_max_S='0')
+ and (abovetriggerlevel_S='1')
+ and (pulsetoolong_S='0')
+ else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ counter_S <= (others => '0');
+ max_data_S <= data_in;
+ half_threshold_S <= '0';
+ else
+ if abovetriggerlevel_S='0' then
+ counter_S <= (others => '0');
+ max_data_S <= data_in;
+ half_threshold_S <= '0';
+ elsif pulsetoolong_S='0' then
+ if (half_threshold_S='0') and (counter_S(2)='1') then
+ half_threshold_S <= '1';
+ end if;
+ counter_S <= counter_S+1;
+ if data_below_max_S='0' then
+ max_data_S <= data_in;
+ end if;
+ else
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd b/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd
new file mode 100644
index 0000000..09f1ac0
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd
@@ -0,0 +1,272 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 02-09-2014
+-- Module Name: FEE_extract_pulse
+-- Description: Extract pulse components from ADC data: time, maximum(2*), Constant Fraction signals
+-- Modifications:
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 27-10-2014 Constant Fraction with negative or equal instead of negative
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_extract_pulse
+-- Extract pulse components from ADC data: time, maximum(2*), Constant Fraction signals
+--
+-- The integral of the pulse is passed on as the energy of the pulse.
+---
+-- The Constant Fraction signal for precise time measurement is done with the formula:
+-- CF_signal = -ADCvalue + 4*ADCvalue'delayed
+-- This results in a signal that has a zero-crossing near the rising edge of the pulse.
+-- The CF_signal before and after the zero-crossing are passed on to calculate the precise timestamp.
+--
+--
+-- generics
+-- ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- cf_delay : delay (number of ADC samples) for the constant fraction
+-- pulse_valid : input data is valid pulse data
+-- pulse_rising : the pulse has not yet reached its maximum
+-- pulse_detected : previous samples are regarded as valid pulse data
+-- pileup_detected : previous samples are regarded as pileup waveform data
+-- clear_waveform : previous samples do not give valid data, clear this data
+-- data_in : input data: adc values minus baseline: signed data
+-- integral : scaled integral of the waveform
+-- superburstnumber : actual superburstnumber from SODA
+-- timestamp : actual 16-bits time inside the superburst
+--
+-- outputs
+-- pulse_write : write signal for the output signals
+-- pulse_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse_energy : energy of the pulse, calculated from integeral
+-- pulse_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse_CF2 : CF_signal value of the value after the zero-crossing
+--
+--
+-- components
+-- shift_register : shift register for the constant fraction delay
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_extract_pulse is
+ generic (
+ ADCBITS : natural := 14;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ integral : in std_logic_vector(15 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ pulse_write : out std_logic;
+ pulse_superburst : out std_logic_vector(15 downto 0);
+ pulse_timestamp : out std_logic_vector(15 downto 0);
+ pulse_skipped : out std_logic;
+ pulse_energy : out std_logic_vector(15 downto 0);
+ pulse_CF1 : out std_logic_vector(15 downto 0);
+ pulse_CF2 : out std_logic_vector(15 downto 0)
+ );
+end FEE_extract_pulse;
+
+architecture Behavioral of FEE_extract_pulse is
+
+component shift_register is
+ generic (
+ width : natural := ADCBITS+1; -- signed signal
+ depthbits : natural := CF_DELAYBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ hold : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end component;
+
+
+constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+
+signal pulse_write_S : std_logic;
+signal pulse_superburst_S : std_logic_vector(15 downto 0);
+signal pulse_timestamp_S : std_logic_vector(15 downto 0);
+signal pulse_max_S : std_logic_vector(ADCBITS downto 0);
+signal pulse_CF1_S : std_logic_vector(15 downto 0);
+signal pulse_CF2_S : std_logic_vector(15 downto 0);
+
+signal prev_setmax_S : std_logic; -- maximum set in previous clock cycle
+signal prev_pulse_valid_S : std_logic; -- valid signal in previous clock cycle
+signal after_max_counter_S : std_logic_vector(CF_DELAYBITS downto 0) := (others => '0');
+
+signal pulse_skipped_S : std_logic := '0';
+signal CF_available_S : std_logic := '0';
+
+signal data_delayed_S : std_logic_vector(ADCBITS downto 0) := (others => '0');
+signal data_delayedx4_S : std_logic_vector(ADCBITS+2 downto 0) := (others => '0');
+signal cf_signal_S : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
+signal prev_cf_signal_S : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
+signal cf_negorzero_S : std_logic;
+signal prev_cf_negorzero_S : std_logic;
+signal enable_CF_S : std_logic;
+
+begin
+
+pulse_write <= pulse_write_S;
+pulse_superburst <= pulse_superburst_S;
+pulse_timestamp <= pulse_timestamp_S;
+pulse_skipped <= pulse_skipped_S;
+pulse_energy <= integral;
+pulse_CF1 <= pulse_CF1_S;
+pulse_CF2 <= pulse_CF2_S;
+
+pulse_write_S <= pulse_detected when CF_available_S='1' else '0';
+
+check_skipped: process(clock)
+variable holdcounter_V : integer range 0 to 3 := 3; -- keep value at the output for 4 clock cycles
+begin
+ if rising_edge(clock) then
+ if (pulse_detected='1') and (CF_available_S='0') then
+ pulse_skipped_S <= '1';
+ elsif pulse_detected='1' then
+ holdcounter_V := 0;
+ elsif holdcounter_V<3 then
+ holdcounter_V := holdcounter_V+1;
+ if holdcounter_V=2 then
+ pulse_skipped_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+get_maxima: process(clock)
+begin
+ if rising_edge(clock) then
+ prev_setmax_S <= '0';
+ if (pulse_valid='0') then
+ pulse_max_S <= data_in;
+ else
+ if conv_integer(signed(data_in))>=conv_integer(signed(pulse_max_S)) then
+ pulse_max_S <= data_in;
+ prev_setmax_S <= '1';
+ end if;
+ end if;
+ prev_pulse_valid_S <= pulse_valid;
+ end if;
+end process;
+
+after_max: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ enable_CF_S <= '0';
+ else
+ if (pulse_valid='0') then
+ enable_CF_S <= '0';
+ else
+ if prev_pulse_valid_S='0' then
+ enable_CF_S <= '1';
+ else
+ if prev_setmax_S='1' then
+ after_max_counter_S <= (others => '0');
+ else
+ if after_max_counter_S(CF_DELAYBITS-1 downto 0) = cf_delay then
+ enable_CF_S <= '0';
+ end if;
+ if after_max_counter_S(CF_DELAYBITS)='0' then
+ after_max_counter_S <= after_max_counter_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+shiftregister1: shift_register
+ generic map(
+ width => ADCBITS+1, -- signed signal
+ depthbits => CF_DELAYBITS
+ )
+ port map(
+ clock => clock,
+ reset => reset,
+ hold => '0',
+ data_in => data_in,
+ depth => cf_delay,
+ data_out => data_delayed_S);
+
+
+data_delayedx4_S <= data_delayed_S & "00";
+cf_signal_S <= conv_std_logic_vector(conv_integer(signed(data_delayedx4_S))-conv_integer(signed(data_in)),ADCBITS+4);
+
+cf_negorzero_S <= '1' when (conv_integer(signed(cf_signal_S))<=0) else '0';
+
+count_samples: process(clock)
+variable pulse_CF1_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
+variable pulse_CF2_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ CF_available_S <= '0';
+ else
+ if (pulse_valid='0') and (pulse_detected='0') then
+ CF_available_S <= '0';
+ else
+ if prev_cf_negorzero_S='1' then
+ if cf_negorzero_S='0' then
+ if enable_CF_S='1' then
+ pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));
+ if pulse_CF1_V>65535 then
+ pulse_CF1_S <= x"ffff";
+ else
+ pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);
+ end if;
+ pulse_CF2_V := conv_integer(signed(cf_signal_S));
+ if pulse_CF2_V>65535 then
+ pulse_CF2_S <= x"ffff";
+ else
+ pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);
+ end if;
+ pulse_superburst_S <= superburstnumber(15 downto 0);
+ pulse_timestamp_S <= timestamp;
+ CF_available_S <= '1';
+ end if;
+ else
+ end if;
+ end if;
+ end if;
+ end if;
+ prev_cf_negorzero_S <= cf_negorzero_S;
+ prev_cf_signal_S <= cf_signal_S;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd b/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd
new file mode 100644
index 0000000..ea4cbb8
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd
@@ -0,0 +1,195 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 19-11-2014
+-- Module Name: FEE_fifo32to8_SODA
+-- Description: FIFO with 32 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_fifo32to8_SODA
+-- FIFO with 32 bits to 8 bits conversion and additional K-character
+-- Data is written in asynchronous 32-bits fifo
+-- After reading the data is splitted in bytes.
+-- If no data is available an Idle is put on the output (BC and the K-character signal).
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+--
+-- Inputs:
+-- write_clock : clock for the 32-bits input data
+-- read_clock : clock for the 16-bits output data
+-- reset : reset
+-- data_in : 32-bits input data
+-- data_write : write signal for 32-bits input data
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+--
+-- Outputs:
+-- data_out : 16-bits output data
+-- char_is_k : corresponding byte in 16-bits output data is K-character
+--
+-- Components:
+-- async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity FEE_fifo32to8_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ data_write : in std_logic;
+ full : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic
+ );
+end FEE_fifo32to8_SODA;
+
+architecture Behavioral of FEE_fifo32to8_SODA is
+
+component async_fifo_512x32
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(31 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(31 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+signal fifo_read_S : std_logic;
+signal fifo_dataout_S : std_logic_vector(31 downto 0);
+signal fifo_databuf_S : std_logic_vector(31 downto 0);
+signal data_out_S : std_logic_vector(7 downto 0);
+signal char_is_k_S : std_logic;
+signal fifo_empty_S : std_logic;
+signal prev_fifo_empty_S : std_logic;
+
+signal fifo_buffilled_S : std_logic := '0';
+signal fifo_read_after1clk_S : std_logic := '0';
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal bytecounter_S : integer range 0 to 3 := 0;
+signal write_data_S : std_logic;
+signal lastbytefilled_S : std_logic;
+signal lastbyte_S : std_logic_vector(7 downto 0);
+
+
+begin
+
+process (read_clock)
+begin
+ if rising_edge(read_clock) then
+ data_out <= data_out_S;
+ char_is_k <= char_is_k_S;
+ end if;
+end process;
+
+
+fifo: async_fifo_512x32 port map(
+ rst => reset,
+ wr_clk => write_clock,
+ rd_clk => read_clock,
+ din => data_in,
+ wr_en => data_write,
+ rd_en => fifo_read_S,
+ dout => fifo_dataout_S,
+ full => full,
+ empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') and (fifo_read_after1clk_S='0') and (lastbytefilled_S='0')
+ and (((bytecounter_S=0) and (fifo_buffilled_S='0')) or ((bytecounter_S=3) and (fifo_buffilled_S='0')))
+ else '0';
+
+data_out_S <=
+ KCHARSODA when TX_DLM='1' else
+ TX_DLM_WORD_S when (TX_DLM_S='1') else
+ KCHAR285 when (write_data_S='0') else
+ lastbyte_S when (lastbytefilled_S='1') else
+ fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
+ fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
+
+char_is_k_S <=
+ '1' when TX_DLM='1' else
+ '0' when (TX_DLM_S='1') else
+ '1' when (write_data_S='0') else
+ '0' when fifo_read_after1clk_S='1' else
+ '0';
+
+write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and
+ ((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
+
+tx_process : process (read_clock)
+begin
+ if rising_edge(read_clock) then
+ if reset='1' then
+ fifo_read_after1clk_S <= '0';
+ TX_DLM_S <= '0';
+ lastbytefilled_S <= '0';
+ bytecounter_S <= 0;
+ else
+ TX_DLM_S <= TX_DLM;
+ if TX_DLM='1' then
+ TX_DLM_WORD_S <= TX_DLM_WORD;
+ end if;
+ fifo_read_after1clk_S <= fifo_read_S;
+ prev_fifo_empty_S <= fifo_empty_S;
+ if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
+ lastbytefilled_S <= '0';
+ end if;
+ if (fifo_read_after1clk_S='1') then
+ if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then
+ lastbytefilled_S <= '1';
+ lastbyte_S <= fifo_databuf_S(7 downto 0);
+ end if;
+ fifo_databuf_S <= fifo_dataout_S;
+ fifo_buffilled_S <= '1';
+ end if;
+ if (TX_DLM='1') or (TX_DLM_S='1') then
+ elsif lastbytefilled_S='1' then
+ bytecounter_S <= 0;
+ else
+ case bytecounter_S is
+ when 0 =>
+ if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
+ fifo_buffilled_S <= '1';
+ bytecounter_S <= 1;
+ end if;
+ when 1 =>
+ fifo_buffilled_S <= '1';
+ bytecounter_S <= 2;
+ when 2 =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 3;
+ when 3 =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 0;
+ when others =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 0;
+ end case;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_fifo8to32_SODA.vhd b/FEE_ADC32board/FEE_modules/FEE_fifo8to32_SODA.vhd
new file mode 100644
index 0000000..859843a
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_fifo8to32_SODA.vhd
@@ -0,0 +1,157 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 19-11-2014
+-- Module Name: FEE_fifo8to32_SODA
+-- Description: FIFO with 8 bits to 32 bits conversion and SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_fifo8to32_SODA
+-- FIFO with 8 bits to 32 bits conversion and SODA
+-- Byte data is converted to 32-bits, alignment is done with check on first word after idles
+-- The resulting 32-bits word is written in an asynchronous 32-bits fifo.
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+--
+-- Inputs:
+-- write_clock : clock for the 32-bits input data
+-- read_clock : clock for the 16-bits output data
+-- reset : reset
+-- data_in : 8-bits input data
+-- char_is_k : corresponding byte in 16-bits data input is K-character
+-- data_read : read signal for 32-bits output data
+--
+-- Outputs:
+-- RX_DLM : SODA character received
+-- RX_DLM_WORD : SODA character
+-- data_out : 32-bits output data (asynchrounous)
+-- data_available : 32-bits output data available (fifo not empty)
+-- overflow : fifo overflow : data has been thrown away
+-- error : error in input data
+--
+-- Components:
+-- async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity FEE_fifo8to32_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ data_read : in std_logic;
+ data_available : out std_logic;
+ overflow : out std_logic;
+ error : out std_logic
+ );
+end FEE_fifo8to32_SODA;
+
+architecture Behavioral of FEE_fifo8to32_SODA is
+
+component async_fifo_512x32
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(31 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(31 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+signal fifo_write_S : std_logic;
+signal fifo_datain_S : std_logic_vector(31 downto 0);
+signal fifo_full_S : std_logic;
+signal fifo_empty_S : std_logic;
+signal error_S : std_logic := '0';
+signal RX_DLM0_S : std_logic := '0';
+signal RX_DLM_S : std_logic := '0';
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0) := (others => '0');
+signal bytecounter_S : integer range 0 to 3 := 0;
+
+begin
+
+error <= error_S;
+RX_DLM_WORD <= RX_DLM_WORD_S;
+RX_DLM <= RX_DLM_S;
+
+fifo: async_fifo_512x32 port map(
+ rst => reset,
+ wr_clk => write_clock,
+ rd_clk => read_clock,
+ din => fifo_datain_S,
+ wr_en => fifo_write_S,
+ rd_en => data_read,
+ dout => data_out,
+ full => fifo_full_S,
+ empty => fifo_empty_S);
+data_available <= '1' when fifo_empty_S='0' else '0';
+
+overflow <= '1' when (fifo_write_S='1') and (fifo_full_S='1') else '0';
+
+rx_process : process(write_clock)
+variable idlecounter_V : integer range 0 to 4;
+begin
+ if rising_edge(write_clock) then
+ RX_DLM_S <= '0';
+ error_S <= '0';
+ fifo_write_S <= '0';
+ if reset='1' then
+ RX_DLM0_S <= '0';
+ bytecounter_S <= 0;
+ idlecounter_V := 0;
+ else
+ if (char_is_k='1') and (data_in=KCHARSODA) then
+ RX_DLM0_S <= '1';
+ error_S <= RX_DLM0_S; -- not 2 DLM after each other
+ elsif RX_DLM0_S='1' then
+ RX_DLM0_S <= '0';
+ RX_DLM_S <= '1';
+ RX_DLM_WORD_S <= data_in;
+ elsif (char_is_k='1') then -- idle: ignore a few
+ if idlecounter_V<4 then
+ idlecounter_V := idlecounter_V+1;
+ else
+ bytecounter_S <= 0;
+ end if;
+ error_S <= RX_DLM0_S; -- not an idle after DLM
+ else -- data
+ idlecounter_V := 0;
+ fifo_datain_S(31 downto 24) <= fifo_datain_S(23 downto 16);
+ fifo_datain_S(23 downto 16) <= fifo_datain_S(15 downto 8);
+ fifo_datain_S(15 downto 8) <= fifo_datain_S(7 downto 0);
+ fifo_datain_S(7 downto 0) <= data_in;
+ if bytecounter_S=3 then
+ bytecounter_S <= 0;
+ fifo_write_S <= '1';
+ else
+ bytecounter_S <= bytecounter_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_gtxModule.vhd b/FEE_ADC32board/FEE_modules/FEE_gtxModule.vhd
new file mode 100644
index 0000000..705e1a9
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_gtxModule.vhd
@@ -0,0 +1,390 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-08-2013
+-- Module Name: FEE_gtxModule
+-- Description: GTP/GTX/serdes tranceiver for PANDA Front End Electronics with clock synchronization
+-- Modifications:
+-- 19-11-2014 Name changed from gtpBufLayerFee to FEE_gtxModule
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxModule
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization:
+--
+-- Receiver generates synchronous clock on incomming serial data (SODA) and detects synchronous
+-- data packages (SODA-commands) with fixed delay.
+-- Receives also asynchronous data from fibre and outputs it as 32 bits.
+-- SODA packages use the DLM i/o. Data is send along with K27.7 character (0xFB)
+-- Idle's consists of K28.1 & K28.5 characters (0x3c,0xBC)
+-- All other valid (non K) characters is treated as data and combined to 32-bits
+--
+-- Transmitter sends data (asynchronous to SODA). The data is organised as 32-bits words.
+-- If no data is available then idle's are sent (0x3CBC)
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- gtpClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency (finally probably 155.52 MHz)
+-- asyncclk : clock for asynchronous resetting of GTP/GTX
+-- reset : reset GTP/GTX
+-- disable_GTX_reset : disable reset of GTX (during clock switching)
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+-- rxAsyncClk : Clock for the asynchronous (32-bits) data (used for slow-control in FEE)
+-- txAsyncData : asynchronous 32-bits data to be transmitted
+-- txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+-- txAsyncLastData : Last asynchronous 32-bits word of the data packet to be transmitted, used for separating packets on the fiber
+-- txAsyncClk : clock for the asynchronous 32-bits data to be transmitted
+-- rxAsyncDataRead : read signal for the asynchronous data fifo
+-- gtpRxP0,gtpRxN0 : differential GTP/GTX inputs
+--
+-- Outputs:
+-- RX_DLM : SODA character received
+-- RX_DLM_WORD : SODA character
+-- txAsyncFifoFull : fifo for 32-bits transmit data is full
+-- txLocked : Transmitter PLL locked
+-- rxAsyncData : asynchronous 32 bits data from the receiver fifo
+-- rxNotInTable : invalid character or other receiver error
+-- rxAsyncDataOverflow : overflow bit of the receiver asynchronous data fifo
+-- rxAsyncDataPresent : Indicates if asynchronous data is available in the receiver fifo
+-- rxSodaClk : Reconstructed clock, synchronous with original SODA clock but different frequency (200MHz)
+-- rxSodaClk40 : Reconstructed SODA clock : 40MHz
+-- rxLocked : Receiver locked
+-- gtpTxP0,gtpTxN0 : differential transmit outputs of the GTP/GTX (not used at the moment)
+--
+-- Components:
+-- FEE_gtxWrapper_Virtex6 : module with the GTP/GTX interface
+-- FEE_SODAfrequencydiv5 : make divide by 5 clock from recovered clock
+-- FEE_fifo32to8_SODA : fifo for data to be transmitted, converts data from 32-bits to 16-bits
+-- FEE_fifo8to32_SODA : fifo for received asynchronous data, converts data from 16-bits to 32-bits
+-- sync_to_different_phase : synchronize to clock with same frequency but different phase
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxModule is
+ Port (
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncDataRead : in std_logic;
+ rxNotInTable : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_gtxModule;
+
+
+architecture Behavioral of FEE_gtxModule is
+
+component FEE_gtxWrapper_Virtex6 is
+ port (
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxLocked : out std_logic;
+
+ resetDone : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_SODAfrequencydiv5 is
+ port (
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component FEE_fifo32to8_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ data_write : in std_logic;
+ full : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic
+ );
+end component;
+
+component FEE_fifo8to32_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ data_read : in std_logic;
+ data_available : out std_logic;
+ overflow : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component sync_to_different_phase is
+ generic (
+ WIDTH : natural := 18
+ );
+ port (
+ clock1 : in std_logic;
+ clock2 : in std_logic;
+ data_in : in std_logic_vector(WIDTH-1 downto 0);
+ data_out : out std_logic_vector(WIDTH-1 downto 0)
+ );
+end component;
+
+component async_fifo_16x9
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(8 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(8 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+component asyncfifo is
+ generic (
+ DATA_WIDTH : natural := 9;
+ ADDR_WIDTH : natural := 2
+ );
+ port (
+ reset : in std_logic;
+ read_clock : in std_logic;
+ read_request : in std_logic;
+ data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+ write_clock : in std_logic;
+ write_request : in std_logic;
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ valid : out std_logic
+ );
+end component;
+
+signal rxSodaClk40_S : std_logic := '0';
+signal rxNotInTable_S : std_logic := '0';
+signal rxLocked_S : std_logic := '0';
+signal txLocked_S : std_logic := '0';
+signal txreset_S : std_logic := '0';
+signal txCharIsK_S : std_logic := '0';
+signal txUsrClk_S : std_logic;
+signal txData_S : std_logic_vector(7 downto 0);
+signal rxCharIsK_S : std_logic;
+
+signal rxUsrClk_S : std_logic;
+signal rxData_S : std_logic_vector(7 downto 0);
+signal rxerror_s : std_logic;
+
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+
+signal fifo_dout_S : std_logic_vector(8 downto 0) := (others => '0');
+signal fifosync_write_S : std_logic :='0';
+signal fifosync_read_S : std_logic :='0';
+signal fifosync_empty_S : std_logic :='0';
+signal fifosync_full_S : std_logic :='0';
+signal fifosync_valid_S : std_logic :='0';
+attribute keep : string;
+attribute keep of txUsrClk_S : signal is "TRUE";
+
+
+
+signal testword0_S : std_logic_vector (35 downto 0):= (others => '0');
+
+begin
+
+txUsrClk <= txUsrClk_S;
+rxSodaClk <= rxUsrClk_S;
+rxSodaClk40 <= rxSodaClk40_S;
+
+FEE_gtxWrapper_Virtex6_1 : FEE_gtxWrapper_Virtex6
+ port map (
+ gtpClk => gtpClk,
+ asyncclk => asyncclk,
+ gtpReset => reset,
+ disable_GTX_reset => disable_GTX_reset,
+ txData => txData_S,
+ txCharIsK => txCharIsK_S,
+ txP => gtpTxP0,
+ txN => gtpTxN0,
+ txUsrClk => txUsrClk_S,
+ txLocked => txLocked_S,
+ rxData => rxData_S,
+ rxCharIsK => rxCharIsK_S,
+ rxNotInTable => rxNotInTable_S,
+ rxP => gtpRxP0,
+ rxN => gtpRxN0,
+ rxUsrClk => rxUsrClk_S,
+ rxLocked => rxLocked_S,
+ resetDone => open,
+ testword0 => testword0
+ );
+
+FEE_SODAfrequencydiv51: FEE_SODAfrequencydiv5 port map(
+ clock => rxUsrClk_S,
+ data => rxData_S,
+ kchar => rxCharIsK_S,
+ clockdiv5 => rxSodaClk40_S,
+ error => open
+ );
+
+-- synchronise SODA signals to txUsrClk_S. same frequency, differe4nt phase -----------------
+txreset_S <= '1' when (txLocked_S='0') or (reset='1') else '0';
+fifosync: async_fifo_16x9 port map(
+ rst => txreset_S,
+ wr_clk => rxUsrClk_S,
+ rd_clk => txUsrClk_S,
+ din(7 downto 0) => TX_DLM_WORD,
+ din(8) => TX_DLM,
+ wr_en => fifosync_write_S,
+ rd_en => fifosync_read_S,
+ dout => fifo_dout_S,
+ full => fifosync_full_S,
+ empty => fifosync_empty_S);
+--fifosync: asyncfifo
+-- generic map(
+-- DATA_WIDTH => 9,
+-- ADDR_WIDTH => 2
+-- )
+-- port map(
+-- reset => txreset_S,
+-- read_clock => txUsrClk_S,
+-- read_request => fifosync_read_S,
+-- data_in(7 downto 0) => TX_DLM_WORD,
+-- data_in(8) => TX_DLM,
+-- write_clock => rxUsrClk_S,
+-- write_request => fifosync_write_S,
+-- data_out => fifo_dout_S,
+-- empty => fifosync_empty_S,
+-- full => fifosync_full_S,
+-- valid => fifosync_valid_S);
+fifosync_read_S <= '1' when fifosync_empty_S='0' else '0';
+fifosync_write_S <= '1' when fifosync_full_S='0' else '0';
+
+TX_DLM_WORD_S <= fifo_dout_S(7 downto 0);
+TX_DLM_S <= fifo_dout_S(8);-- when fifosync_valid_S='1' else '0';
+
+FEE_fifo32to8_SODA1: FEE_fifo32to8_SODA port map(
+ write_clock => txAsyncClk,
+ read_clock => txUsrClk_S,
+ reset => reset,
+ data_in => txAsyncData,
+ data_write => txAsyncDataWrite,
+ full => txAsyncFifoFull,
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ data_out => txData_S,
+ char_is_k => txCharIsK_S
+ );
+
+
+
+
+FEE_fifo8to32_SODA1: FEE_fifo8to32_SODA port map(
+ write_clock => rxUsrClk_S,
+ read_clock => rxAsyncClk,
+ reset => reset,
+ data_in => rxData_S,
+ char_is_k => rxCharIsK_S,
+ RX_DLM => RX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+ data_out => rxAsyncData,
+ data_read => rxAsyncDataRead,
+ data_available => rxAsyncDataPresent,
+ overflow => rxAsyncDataOverflow,
+ error => rxerror_S);
+
+txLocked <= txLocked_S; -- 1 => OK
+rxLocked <= rxLocked_S; -- 1 => OK
+rxNotInTable <= rxNotInTable_S or rxerror_S; -- '1' => error
+
+--sync_to_different_phase1: sync_to_different_phase port map(
+-- clock1 => rxUsrClk_S,
+-- clock2 => txUsrClk_S,
+-- data_in(15 downto 0) => txData_rxclk_S,
+-- data_in(17 downto 16) => txCharisK_rxclk_S,
+-- data_out(15 downto 0) => txData_S,
+-- data_out(17 downto 16) => txCharIsK_S);
+
+
+--testword0 <= testword0_S;
+
+
+--testword0(15 downto 0) <= rxData_S;
+--testword0(17 downto 16) <= rxCharIsK_S;
+--testword0(33 downto 18) <= txData_rxclk_S;
+--testword0(34) <= '1' when txCharisK_rxclk_S="11" else '0';
+
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd b/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd
new file mode 100644
index 0000000..a9883ef
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd
@@ -0,0 +1,531 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Michel Hevinga / Peter Schakel
+-- Create Date: 2010
+-- Module Name: FEE_gtxWrapper_Virtex6
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Virtex6 with clock synchronization
+-- Modifications:
+-- 19-11-2014 Name changed from gtxWrapperVirtex6Fee to FEE_gtxWrapper_Virtex6
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+library work;
+use work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxWrapper_Virtex6
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.
+--
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA).
+-- Data is 16-bits, synchronous to recovered clock.
+-- Transmitter sends 16-bits data.
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- gtpClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency
+-- asyncclk : clock for synchronous resetting
+-- gtpReset : reset GTP/GTX
+-- disable_GTX_reset : disable ressetting temporarely
+-- txData : 16-bits input data to transmit
+-- txCharIsK : data to transmit are K-characters
+-- rxP,rxN : differential transmit inputs from the GTP/GTX
+--
+-- Outputs:
+-- txP,txN : differential transmit outputs of the GTP/GTX
+-- txUsrClk : clock for transmit data
+-- txLocked : transmitter locked
+-- rxData : 16-bits received data
+-- rxCharIsK : received 16-bits data (2 bytes) are K-characters
+-- rxNotInTable : receiver data not valid
+-- rxUsrClk : Recovered synchronous clock
+-- rxLocked : receiver locked to incomming data
+-- resetDone : resetting ready
+--
+-- Components:
+-- GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments
+-- FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase
+-- Clock_62M5_doubler : Clock doubler with PLL
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxWrapper_Virtex6 is
+ port (
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxLocked : out std_logic;
+
+ resetDone : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_gtxWrapper_Virtex6;
+
+architecture Behavioral of FEE_gtxWrapper_Virtex6 is
+
+component gtxVirtex6FEE80 is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset
+);
+port
+(
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GTX0 (X0Y12)
+
+ GTX0_DOUBLE_RESET_CLK_IN : in std_logic;
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+
+
+);
+
+
+end component;
+
+
+component FEE_rxBitLock is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0));
+end component;
+
+component gtxVirtex6FEE80_tx_sync
+generic
+(
+ -- Simulation attributes
+ SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset
+);
+port
+(
+ TXENPMAPHASEALIGN : out std_logic;
+ TXPMASETPHASE : out std_logic;
+ TXDLYALIGNDISABLE : out std_logic;
+ TXDLYALIGNRESET : out std_logic;
+ SYNC_DONE : out std_logic;
+ USER_CLK : in std_logic;
+ RESET : in std_logic
+);
+end component;
+
+component MGT_USRCLK_SOURCE_MMCM
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+(
+ CLKFBOUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ CLK_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic;
+ MMCM_RESET_IN : in std_logic
+);
+end component;
+
+signal rxCharIsK_S : std_logic;
+signal rxData_S : std_logic_vector(7 downto 0);
+signal rxReset_S : std_logic :='0';
+signal rxRecClk_S : std_logic :='0';
+signal rxRecClk_buf_S : std_logic :='0';
+signal rxRecClk_double_S : std_logic :='0';
+
+signal rxLocked_S : std_logic;
+signal txLocked_S : std_logic;
+signal txReset_S : std_logic;
+signal txResetdone_S : std_logic;
+
+signal rxLossOfSync_S : std_logic_vector(1 downto 0);
+signal rxLossOfSync1_S : std_logic;
+signal rxNotInTable_S : std_logic;
+signal rxDispError_S : std_logic;
+
+signal rxResetBitLock_S : std_logic :='0';
+signal pllLkDet_S : std_logic :='0';
+signal resetDone_S : std_logic :='0';
+signal txOutClk_S : std_logic :='0';
+
+--signal txUsrClk0_S : std_logic :='0';
+signal txUsrClk_buf_S : std_logic :='0';
+
+signal fsmStatus_S : std_logic_vector(1 downto 0);
+signal gtx0_double_reset_clk_i : std_logic;
+
+signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
+
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal disable_GTX_reset_S : std_logic :='0';
+
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ signal gtx0_txdlyaligndisable_i : std_logic;
+ signal gtx0_txdlyalignmonenb_i : std_logic;
+ signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_txdlyalignreset_i : std_logic;
+ signal gtx0_txenpmaphasealign_i : std_logic;
+ signal gtx0_txpmasetphase_i : std_logic;
+ signal gtx0_txresetdone_r : std_logic;
+ signal gtx0_txresetdone_r2 : std_logic;
+ signal gtx0_reset_txsync_c : std_logic;
+ signal gtx0_tx_sync_done_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+
+
+signal testword0_S : std_logic_vector(35 downto 0);
+
+begin
+ rxUsrClk <= rxRecClk_buf_S;
+ rxData <= rxData_S;
+ txUsrClk <= txUsrClk_buf_S;
+ resetDone <= resetDone_S;
+ rxLocked <= rxLocked_S;
+ txLocked <= txLocked_S;
+ rxCharIsK <= rxCharIsK_S;
+
+--rxRecClk0_BUFG: BUFG port map (
+-- I => rxRecClk_S,
+-- O => rxRecClk_buf_S);
+
+rxrecclk_bufr1_i : BUFR
+ generic map ( BUFR_DIVIDE => "BYPASS" )
+ port map (
+ CE => '1',
+ CLR => '0',
+ I => rxRecClk_S,
+ O => rxRecClk_buf_S);
+
+-----------------------Dedicated GTX Reference Clock Inputs ---------------
+-- The dedicated reference clock inputs you selected in the GUI are implemented using
+-- IBUFDS_GTXE1 instances.
+--
+-- In the UCF file for this example design, you will see that each of
+-- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these
+-- locations, we tell the tools to use the dedicated input buffers to the GTX reference
+-- clock network, rather than general purpose IOs. To select other pins, consult the
+-- Implementation chapter of UG___, or rerun the wizard.
+--
+-- This network is the highest performace (lowest jitter) option for providing clocks
+-- to the GTX transceivers.
+q3_clk0_refclk_bufg_i : BUFG port map (
+ I => gtpClk,
+ O => gtx0_double_reset_clk_i);
+
+
+
+gtx_i : gtxVirtex6FEE80 port map(
+ GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT => rxCharIsK_S,
+ GTX0_RXDISPERR_OUT => rxDispError_S,
+ GTX0_RXNOTINTABLE_OUT => rxNotInTable_S,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN => '0', -- disable byte boundery alignment
+ GTX0_RXENPCOMMAALIGN_IN => '0', -- disable byte boundery alignment
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT => rxData_S,
+ GTX0_RXRECCLK_OUT => rxRecClk_S,
+ GTX0_RXRESET_IN => rxReset_S,
+ GTX0_RXUSRCLK2_IN => rxRecClk_buf_S,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN => rxReset_S,
+--? GTX0_RXELECIDLE_OUT => open,
+ GTX0_RXN_IN => rxN,
+ GTX0_RXP_IN => rxP,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN => '0', --- ??????????????????
+ GTX0_RXDLYALIGNMONENB_IN => '0', --- ??????????????????
+ GTX0_RXDLYALIGNMONITOR_OUT => open, --- ??????????????????
+ GTX0_RXDLYALIGNOVERRIDE_IN => '1', --- ??????????????????
+ GTX0_RXDLYALIGNRESET_IN => '0', --- ??????????????????
+ GTX0_RXENPMAPHASEALIGN_IN => '0',
+ GTX0_RXPMASETPHASE_IN => '0',
+ GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT => rxLossOfSync_S,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN => gtpReset,
+ GTX0_MGTREFCLKRX_IN => gtpClk,
+ GTX0_PLLRXRESET_IN => '0', -- gtpReset, --- ??????????????????????
+ GTX0_RXPLLLKDET_OUT => pllLkDet_S,
+ GTX0_RXRESETDONE_OUT => resetDone_S,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT => open, --?
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN => txCharIsK,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN => txData,
+ GTX0_TXOUTCLK_OUT => txOutClk_S,
+ GTX0_TXRESET_IN => txReset_S,
+ GTX0_TXUSRCLK2_IN => txUsrClk_buf_S,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT => txN,
+ GTX0_TXP_OUT => txP,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
+ GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
+ GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
+ GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
+ GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
+ GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN => gtpReset, --- ??????????????????????
+ GTX0_TXRESETDONE_OUT => txResetdone_S
+ );
+
+
+rxLossOfSync1_S <= '0' when (rxNotInTable_S='0') or (disable_GTX_reset_S='1') else '1';
+FEE_rxBitLock1 : FEE_rxBitLock port map (
+ clk => rxRecClk_buf_S,
+ reset => gtpReset,
+ resetDone => resetDone_S,
+ lossOfSync => rxLossOfSync1_S,
+ rxPllLocked => PllLkDet_S,
+ rxReset => rxResetBitLock_S,
+ fsmStatus => fsmStatus_S
+ );
+
+---- rxReset_S <= gtpReset;
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset='1')) and (disable_GTX_reset_S='0') else '0';
+rxLocked_S <= '1' when (fsmStatus_S = "10") else '0';
+rxNotInTable <= rxNotInTable_S;
+-- peter: gepulste reset (op refclk) voor zowel GTP als PLL
+-- lengte van de reset-pulse varieert om te voorkomen dat de reset synchroon is met de GTP
+----rxPLLwrapper_reset_S <= '1' when (notPllLkDet_S='1') or (rxResetBitLock_pulse_S='1') else '0';
+rxPLLwrapper_reset_S <= '1' when (rxResetBitLock_pulse_S='1') else '0';
+
+
+--ADCclkbuf : BUFG port map (
+-- O => txUsrClk_buf_S,
+-- I => txOutClk_S);
+txLocked_S <= '1' when (txResetdone_S='1') and (gtx0_tx_sync_done_i='1') else '0';
+
+rxRecClk_double_S <= '0';
+
+process(rxRecClk_buf_S)
+begin
+ if rising_edge(rxRecClk_buf_S) then
+ disable_GTX_reset_S <= disable_GTX_reset;
+ end if;
+end process;
+
+
+process(asyncclk)
+variable resetcounter_V : integer range 0 to 63 := 0;
+variable lastresetcounter_V : integer range 0 to 63 := 10;
+begin
+ if rising_edge(asyncclk) then
+ if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+ rxResetBitLock_pulse_S <= '1';
+ resetcounter_V := 0;
+ if lastresetcounter_V<63 then
+ lastresetcounter_V := lastresetcounter_V+1;
+ else
+ lastresetcounter_V := 10;
+ end if;
+ elsif resetcounter_V 0
+ )
+ port map
+ (
+ TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,
+ TXPMASETPHASE => gtx0_txpmasetphase_i,
+ TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,
+ TXDLYALIGNRESET => gtx0_txdlyalignreset_i,
+ SYNC_DONE => gtx0_tx_sync_done_i,
+ USER_CLK => txUsrClk_buf_S,
+ RESET => gtx0_reset_txsync_c
+ );
+ -- The clock resources in this section were added based on userclk source selections on
+ -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:
+ -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to
+ -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits
+ -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency
+ -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when
+ -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all
+ -- the channels using the clock are receiving data from TX channels that share a reference clock
+ -- source with each other.
+
+ txoutclk_mmcm0_reset_i <= not pllLkDet_S;
+ txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
+ generic map
+ (
+ MULT => 15.0,
+ DIVIDE => 1,
+ CLK_PERIOD => 12.5,
+ OUT0_DIVIDE => 6.0,
+ OUT1_DIVIDE => 1,
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLKFBOUT => open,
+ CLK0_OUT => txUsrClk_buf_S,
+ CLK1_OUT => open,
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => txOutClk_S,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+ process( txUsrClk_buf_S,txResetdone_S)
+ begin
+ if(txResetdone_S = '0') then
+ gtx0_txresetdone_r <= '0';
+ gtx0_txresetdone_r2 <= '0';
+ elsif(txUsrClk_buf_S'event and txUsrClk_buf_S = '1') then
+ gtx0_txresetdone_r <= txResetdone_S;
+ gtx0_txresetdone_r2 <= gtx0_txresetdone_r;
+ end if;
+ end process;
+ txReset_S <= not txoutclk_mmcm0_locked_i;
+
+
+testword0(7 downto 0) <= rxData_S;
+testword0(8) <= rxCharIsK_S;
+testword0(10 downto 9) <= fsmStatus_S;
+testword0(12 downto 11) <= rxLossOfSync_S;
+testword0(13) <= rxNotInTable_S;
+
+testword0(14) <= rxReset_S;
+testword0(15) <= resetDone_S;
+testword0(16) <= rxPLLwrapper_reset_S;
+
+testword0(17) <= disable_GTX_reset_S;
+testword0(18) <= rxResetBitLock_S;
+testword0(19) <= rxResetBitLock_pulse_S;
+--testword0(20) <= rxLocked_S;
+--
+--testword0(21) <= gtpReset;
+--testword0(22) <= PllLkDet_S;
+--testword0(23) <= rxDispError_S;
+--testword0(24) <= rxLossOfSync1_S;
+--testword0(27 downto 25) <= gtx0_rxstatus_i;
+--testword0(28) <= sync_rxResetBitLock_S;
+testword0(29) <= prev_rxResetBitLock_S;
+testword0(30) <= txLocked_S;
+testword0(31) <= txResetdone_S;
+
+testword0(27 downto 20) <= txData;
+testword0(28) <= txCharIsK;
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd b/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd
new file mode 100644
index 0000000..c024f53
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 16-09-2014
+-- Module Name: FEE_measure_frequency
+-- Description: Measures the frequency of pulses
+-- Modifications:
+-- 02-10-2014 onesecondpulse outside module
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_measure_frequency
+-- Measures the number of pulses in one second
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+-- CLOCKFREQUENCY : frequency of the clock
+--
+-- Inputs:
+-- clock : clock
+-- pulse : pulse to count
+--
+-- Outputs:
+-- frequency : number of pulses measured in one second
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_measure_frequency is
+ generic (
+ CLOCKFREQUENCY : natural := 80000000
+ );
+ port (
+ clock : in std_logic;
+ pulse : in std_logic;
+ onesecondpulse : in std_logic;
+ frequency : out std_logic_vector(31 downto 0)
+ );
+end FEE_measure_frequency;
+
+architecture Behavioral of FEE_measure_frequency is
+
+signal counter_S : std_logic_vector(31 downto 0) := (others => '0');
+
+begin
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if onesecondpulse='1' then
+ frequency <= counter_S;
+ if pulse='1' then
+ counter_S <= x"00000001";
+ else
+ counter_S <= x"00000000";
+ end if;
+ else
+ if pulse='1' then
+ counter_S <= counter_S+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd b/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd
new file mode 100644
index 0000000..5b7c216
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd
@@ -0,0 +1,345 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_mux2to1
+-- Description: compare timestamp of 36bits data pass on first
+-- Modifications:
+-- 16-10-2014: 3*36bits words; bits 35 and 34 as indenticication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_mux2to1
+-- Compare timestamp of 36bits data and pass on first
+-- If data from only one is available then this is passed on directly
+-- The 36-bits data contains packets with 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data1_in : data from first 36-bits input, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data1_in_write : write signal for data1_in
+-- data1_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data2_in : data from second 36-bits input, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data2_in_write : write signal for data2_in
+-- data2_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data_out_allowed : writing of resulting data allowed
+--
+-- outputs
+-- data1_in_allowed : signal to allow data input 1
+-- data2_in_allowed : signal to allow data input 2
+-- data_out : 36-bits data with valid pulse waveform, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_write : write signal for 36-bits output data
+-- data_out_available : data available: in this module or at the input
+-- error : error in data bits 35..32
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_mux2to1 is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_mux2to1;
+
+
+architecture Behavioral of FEE_mux2to1 is
+
+constant TIMEOUTBITS : integer := 6;
+signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+
+signal error_S : std_logic := '0';
+signal read_pulse1_S : std_logic := '0';
+signal read_pulse2_S : std_logic := '0';
+signal data1_in_allowed_S : std_logic := '0';
+signal data2_in_allowed_S : std_logic := '0';
+signal data1_in_write_S : std_logic := '0';
+signal data2_in_write_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_available_S : std_logic := '0';
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data1_timestamp_valid_S : std_logic := '0';
+signal data2_timestamp_valid_S : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+data_out_available <= data_out_available_S;
+data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1')
+ or (data_out_trywrite_S='1')
+ or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
+ else '0';
+
+data_out <= data_out_S;
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data1_in_allowed <= data1_in_allowed_S;
+data1_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse1_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
+ else '0';
+
+data2_in_allowed <= data2_in_allowed_S;
+data2_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse2_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+ else '0';
+
+--data2_in_allowed_S <= '1' when (data_out_allowed='1')
+-- and ((read_pulse2_S='1')
+-- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
+-- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+-- else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
+
+readprocess: process(clock)
+variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data1_timestamp_valid_V : std_logic;
+variable data2_timestamp_valid_V : std_logic;
+variable data1_lowchannel_V : std_logic;
+variable data2_lowchannel_V : std_logic;
+variable data1_pulseskipped_V : std_logic;
+variable data2_pulseskipped_V : std_logic;
+
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_trywrite_S <= '0';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data1_timestamp_valid_S <= '0';
+ data2_timestamp_valid_S <= '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+ data_out_trywrite_S <= '1'; -- try again
+ timeout_counter_S <= (others => '0');
+ else
+ if read_pulse1_S='1' then
+ data1_timestamp_valid_V := '0';
+ if data1_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data1_in(35 downto 34)="01") then -- next data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';
+ elsif (data1_in(35 downto 34)="10") then -- last data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ read_pulse1_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ elsif read_pulse2_S='1' then
+ data2_timestamp_valid_V := '0';
+ if data2_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data2_in(35 downto 34)="01") then -- next data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';
+ elsif (data2_in(35 downto 34)="10") then -- last data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ read_pulse2_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ else
+ timeout_counter_S <= (others => '0');
+ if data1_in_write_S='1' then
+ if (data1_in(35 downto 34)="00") then
+ data1_timestamp_V := data1_in(31 downto 0);
+ data1_lowchannel_V := data1_in(33);
+ data1_pulseskipped_V := data1_in(32);
+ data1_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data2_in_write_S='1' then
+ if (data2_in(35 downto 34)="00") then
+ data2_timestamp_V := data2_in(31 downto 0);
+ data2_lowchannel_V := data1_in(33);
+ data2_pulseskipped_V := data1_in(32);
+ data2_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data1_timestamp_valid_V='1' then
+ if data2_timestamp_valid_V='1' then
+ if (data1_timestamp_V(31 downto 0) '0');
+
+testword0(0) <= data1_in_write;
+testword0(1) <= data1_in_available;
+testword0(2) <= data1_in_allowed_S;
+testword0(3) <= read_pulse1_S;
+testword0(4) <= data1_in_write_S;
+testword0(5) <= data1_timestamp_valid_S;
+testword0(9 downto 6) <= data1_in(35 downto 32);
+
+testword0(10) <= data2_in_write;
+testword0(11) <= data2_in_available;
+testword0(12) <= data2_in_allowed_S;
+testword0(13) <= read_pulse2_S;
+testword0(14) <= data2_in_write_S;
+testword0(15) <= data2_timestamp_valid_S;
+testword0(19 downto 16) <= data2_in(35 downto 32);
+
+
+testword0(20) <= data_out_trywrite_S;
+testword0(21) <= data_out_write_S;
+testword0(22) <= data_out_available_S;
+testword0(23) <= data_out_allowed;
+testword0(27 downto 24) <= data_out_S(35 downto 32);
+testword0(28) <= error_S;
+
+
+
+testword0(35 downto 29) <= (others => '0');
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd b/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd
new file mode 100644
index 0000000..df92b80
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd
@@ -0,0 +1,119 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_mux_readfifo
+-- Description: Read 36-bits data from fifo and write to next module
+-- Modifications:
+-- 16-10-2014 new name for output : data_out_inpipe
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- MUX_mux_readfifo
+-- Read 36-bits data from fifo and write to next module.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : 36-bits input data from fifo
+-- data_in_available : input fifo not empty
+-- data_out_allowed : allowed to write output data data
+--
+-- Outputs:
+-- data_in_read : read signal to input fifo
+-- data_out : 36-bits output data
+-- data_out_write : write signal for output data
+-- data_out_inpipe : data available, in this module or in input fifo
+--
+-- Components:
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_mux_readfifo is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);
+end FEE_mux_readfifo;
+
+
+architecture Behavioral of FEE_mux_readfifo is
+
+signal data_in_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_write_S : std_logic := '0';
+signal data_in_saved_S : std_logic := '0';
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+
+
+begin
+
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or
+ (data_in_saved_S='1') else '0';
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data_out <= data_out_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ data_in_read_after1clk_S <= '0';
+ data_out_trywrite_S <= '0';
+ data_in_saved_S <= '0';
+ else
+ if (data_out_write_S='0') and (data_out_trywrite_S='1') then -- unsuccesfull try again
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ end if;
+ elsif data_in_saved_S='1' then -- write saved data
+ data_out_S <= data_in_S;
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then -- save next data
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ else
+ data_in_saved_S <= '0';
+ end if;
+ elsif data_in_read_after1clk_S='1' then -- next read
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ else
+ data_out_trywrite_S <= '0';
+ end if;
+ data_in_read_after1clk_S <= data_in_read_S;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd b/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd
new file mode 100644
index 0000000..6c3876f
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd
@@ -0,0 +1,526 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 16-03-2012
+-- Module Name: FEE_pileup_check
+-- Description: Checks and compares two pulselength's
+-- Modifications:
+-- 02-09-2014 timestamp output indicates now the time of pulse or pileup valid signal
+-- 16-09-2014 name changed from pileup_check to FEE_pileup_check
+-- 24-09-2014 enable_highgain and enable_lowgain inputs added
+-- 10-10-2014 Integral output added, as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pileup_check
+-- Determines if pulses should be regarded as pileup, as single pulse, or rejected.
+-- If the pulse-time is below an adjustable number of samples then the pulse is rejected.
+-- If the pulse-time is longer than an adjustable number of samples then the pulse is regarded as pileup.
+-- The other pulses are tested for Integral/Maximum ratio:
+-- Pulse is valid until the signal dropps below Triggerlevel_endofpulse
+-- The pulse is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
+-- The pulse is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
+-- At the end of the pulse 1-clockcycle signals are generated for : valid pulse, pileup or cleanup
+--
+--
+--
+-- generics
+-- ADCBITS : number of ADC-bits
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- superburstnumber : actual superburstnumber
+-- timestampcounter : timestampcounter within superburst
+-- ADC_highgain : signed ADC value, corrected for baseline
+-- enable_highgain : enable high gain input
+-- max_data_highgain : maximum of the waveform, calculated by the eventdetector (unsigned)
+-- pulse_active_highgain : high gain pulse active (signal above threshold)
+-- pulse_rising_highgain : high gain pulse has not yet reached maximum
+-- ADC_lowgain : signed ADC value, corrected for baseline
+-- enable_lowgain : enable low gain input
+-- max_data_lowgain : maximum of the waveform, calculated by the eventdetector (unsigned)
+-- pulse_active_lowgain : low gain pulse active (signal above threshold)
+-- pulse_rising_lowgain : low gain pulse has not yet reached maximum
+-- minpulselength : number of samples below which the pulse is ignored
+-- pileuplength : number of samples above which the pulse is treated as pileup
+-- maxwavelength : maximum number of samples that can be saved in one waveform
+-- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
+-- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
+-- fullsize_wave_highgain : take waveforms with maximum size for highgain input
+-- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
+--
+-- outputs
+-- pulse_valid_highgain : high gain pulse data valid, and pulse not too long
+-- singlepulse_highgain : high gain pulse detected
+-- pileuppulse_highgain : high gain pileup signal detected
+-- clearpulse_highgain : high gain pulse too short: clear saved samples
+-- integral_highgain : high gain scaled integral output as value for the energy
+-- pulse_valid_lowgain : low gain pulse data valid, and pulse not too long
+-- singlepulse_lowgain : low gain pulse detected
+-- pileuppulse_lowgain : low gain pileup signal detected
+-- clearpulse_lowgain : low gain pulse too short: clear saved samples
+-- integral_lowgain : low gain scaled integral output as value for the energy
+-- superburst : superburst of the detected pulse or pileup signal (start of valid)
+-- timestamp : timestamp within the superburst of the detected pulse or pileup signal (start of valid)
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pileup_check is
+ generic (
+ ADCBITS : natural := 14;
+ IDIVMAXBITS : natural := 5;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_highgain : in std_logic;
+ max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_highgain : in std_logic;
+ pulse_rising_highgain : in std_logic;
+ clipping_highgain : in std_logic;
+ ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_lowgain : in std_logic;
+ max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_lowgain : in std_logic;
+ pulse_rising_lowgain : in std_logic;
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ pulse_valid_highgain : out std_logic;
+ singlepulse_highgain : out std_logic;
+ pileuppulse_highgain : out std_logic;
+ clearpulse_highgain : out std_logic;
+ integral_highgain : out std_logic_vector(15 downto 0);
+ pulse_valid_lowgain : out std_logic;
+ singlepulse_lowgain : out std_logic;
+ pileuppulse_lowgain : out std_logic;
+ clearpulse_lowgain : out std_logic;
+ integral_lowgain : out std_logic_vector(15 downto 0);
+ superburst : out std_logic_vector(15 downto 0);
+ timestamp : out std_logic_vector(15 downto 0);
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_pileup_check;
+
+architecture Behavioral of FEE_pileup_check is
+
+constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');
+signal pulse_highgain_tooshort_S : std_logic := '0';
+signal pulse_highgain_toolong_S : std_logic := '0';
+signal pulse_highgain_pileup_S : std_logic := '0';
+signal prev_pulse_highgain_toolong_S : std_logic := '0';
+signal prev_pulseactive_highgain_S : std_logic := '0';
+signal singlepulse_highgain_S : std_logic := '0';
+signal pileuppulse_highgain_S : std_logic := '0';
+signal clearpulse_highgain_S : std_logic := '0';
+signal pulse_active_highgain_prev1_S : std_logic := '0';
+signal pulse_active_highgain_prev2_S : std_logic := '0';
+signal counter_highgain_S : std_logic_vector(7 downto 0);
+
+signal singlepulse_lowgain_occured_S : std_logic := '0';
+signal pileuppulse_lowgain_occured_S : std_logic := '0';
+signal pulse_lowgain_tooshort_S : std_logic := '0';
+signal pulse_lowgain_toolong_S : std_logic := '0';
+signal pulse_lowgain_pileup_S : std_logic := '0';
+signal prev_pulse_lowgain_toolong_S : std_logic := '0';
+signal prev_pulseactive_lowgain_S : std_logic := '0';
+signal singlepulse_lowgain_S : std_logic := '0';
+signal pileuppulse_lowgain_S : std_logic := '0';
+signal clearpulse_lowgain_S : std_logic := '0';
+signal pulse_active_lowgain_prev1_S : std_logic := '0';
+signal pulse_active_lowgain_prev2_S : std_logic := '0';
+
+signal clipping_highgain_S : std_logic := '0';
+signal counter_lowgain_S : std_logic_vector(7 downto 0) := (others => '0');
+
+signal superburst_highgain_S : std_logic_vector(15 downto 0) := (others => '0');
+signal timestamp_highgain_S : std_logic_vector(15 downto 0) := (others => '0');
+signal superburst_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');
+signal timestamp_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');
+
+
+signal integral_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal maxXconstant1_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal maxXconstant2_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal integral_highgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);
+signal pulse_highgain_toonarrow_s : std_logic := '0';
+signal pulse_highgain_toowide_S : std_logic := '0';
+
+
+signal integral_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal maxXconstant1_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal maxXconstant2_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
+signal integral_lowgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);
+signal pulse_lowgain_toonarrow_s : std_logic := '0';
+signal pulse_lowgain_toowide_S : std_logic := '0';
+
+signal fullsize_wave_highgain_S : std_logic := '0';
+signal fullsize_wave_lowgain_S : std_logic := '0';
+
+signal pulse_active_highgain_S : std_logic := '0';
+signal prev_pulseactive_highgainS_S : std_logic := '0';
+signal pulse_busy_highgain_S : std_logic := '0';
+signal pulse_active_lowgain_S : std_logic := '0';
+signal prev_pulse_active_lowgains_s : std_logic := '0';
+signal pulse_busy_lowgain_S : std_logic := '0';
+
+--integer range 0 to 2**(ADCBITS+IDIVMAXBITS-1)-1;
+begin
+
+integral_highgain_stdl_S <= conv_std_logic_vector(integral_highgain_S,ADCBITS+10);
+integral_highgain <=
+ x"0000" when (integral_highgain_stdl_S(ADCBITS+9)='1') else -- negative
+ x"ffff" when (integral_highgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip
+ else integral_highgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
+
+integral_lowgain_stdl_S <= conv_std_logic_vector(integral_lowgain_S,ADCBITS+10);
+integral_lowgain <=
+ x"0000" when (integral_lowgain_stdl_S(ADCBITS+9)='1') else -- negative
+ x"ffff" when (integral_lowgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip
+ else integral_lowgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if (enable_highgain='1') then
+ fullsize_wave_highgain_S <= fullsize_wave_highgain;
+ else
+ fullsize_wave_highgain_S <= '0';
+ end if;
+ if (enable_lowgain='1') then
+ fullsize_wave_lowgain_S <= fullsize_wave_lowgain;
+ else
+ fullsize_wave_lowgain_S <= '0';
+ end if;
+ end if;
+end process;
+
+clipping_highgain_S <= clipping_highgain;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if (reset='1') then
+ integral_highgain_S <= conv_integer(signed(ADC_highgain));
+ else
+ if ((pulse_active_highgain='0') and (pulse_active_highgain_prev1_S='0')) or
+ ((pulse_active_highgain='1') and (pulse_active_highgain_prev1_S='0') and (pulse_active_highgain_prev2_S='1'))then
+ integral_highgain_S <= conv_integer(signed(ADC_highgain));
+ else
+ integral_highgain_S <= integral_highgain_S+conv_integer(signed(ADC_highgain));
+ end if;
+ end if;
+ pulse_active_highgain_prev2_S <= pulse_active_highgain_prev1_S;
+ pulse_active_highgain_prev1_S <= pulse_active_highgain;
+ end if;
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ maxXconstant1_highgain_S <= conv_integer(unsigned(max_data_highgain)) * conv_integer(unsigned(IdivMAX_discard));
+ maxXconstant2_highgain_S <= conv_integer(unsigned(max_data_highgain)) * conv_integer(unsigned(IdivMAX_pileup));
+ end if;
+end process;
+pulse_highgain_toonarrow_S <= '1' when maxXconstant1_highgain_S>integral_highgain_S else '0';
+pulse_highgain_toowide_S <= '1' when maxXconstant2_highgain_Sintegral_lowgain_S else '0';
+pulse_lowgain_toowide_S <= '1' when maxXconstant2_lowgain_S '0');
+ pulse_highgain_toolong_S <= '0';
+ pulse_highgain_pileup_S <= '0';
+ pulse_busy_highgain_S <= '0';
+ else
+ if (pulse_active_highgain_S='1') or (pulse_active_highgain='1') then
+ pulse_busy_highgain_S <= enable_highgain;
+ if counter_highgain_S '0');
+ pulse_highgain_pileup_S <= '0';
+ end if;
+ end if;
+ prev_pulse_highgain_toolong_S <= pulse_highgain_toolong_S;
+ prev_pulseactive_highgain_S <= pulse_active_highgain;
+ prev_pulseactive_highgainS_S <= pulse_active_highgain_S;
+ end if;
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ singlepulse_lowgain_occured_S <= '0';
+ pileuppulse_lowgain_occured_S <= '0';
+ else
+ if (pulse_active_highgain='0') then
+ singlepulse_lowgain_occured_S <= '0'; -- clear indicator for low-gain pulse happened
+ elsif singlepulse_lowgain_S='1' then
+ singlepulse_lowgain_occured_S <= enable_lowgain;
+ end if;
+ if (pulse_active_highgain='0') then
+ pileuppulse_lowgain_occured_S <= '0'; -- clear indicator for low-gain pileup-pulse happened
+ elsif pileuppulse_lowgain_S='1' then
+ pileuppulse_lowgain_occured_S <= enable_lowgain;
+ end if;
+ end if;
+ end if;
+end process;
+
+pulse_lowgain_tooshort_S <= '1' when (counter_lowgain_S '0');
+ pulse_lowgain_toolong_S <= '0';
+ pulse_lowgain_pileup_S <= '0';
+ pulse_busy_lowgain_S <= '0';
+ else
+ if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') then
+ pulse_busy_lowgain_S <= enable_lowgain;
+ if counter_lowgain_S '0');
+ pulse_lowgain_pileup_S <= '0';
+ end if;
+ end if;
+ prev_pulse_lowgain_toolong_S <= pulse_lowgain_toolong_S;
+ prev_pulseactive_lowgain_S <= pulse_active_lowgain;
+ prev_pulse_active_lowgainS_S <= pulse_active_lowgain_S;
+ end if;
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ superburst <= (others => '0');
+ timestamp <= (others => '0');
+ else
+ if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then
+ superburst <= superburst_lowgain_S;
+ timestamp <= timestamp_lowgain_S;
+ elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then
+ superburst <= superburst_highgain_S;
+ timestamp <= timestamp_highgain_S;
+ end if;
+ end if;
+ end if;
+end process;
+
+--testword0(0) <= pulse_active_highgain;
+--testword0(1) <= pulse_rising_highgain;
+--
+--testword0(2) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;
+--testword0(3) <= pulse_highgain_toolong_S;
+--testword0(4) <= prev_pulse_highgain_toolong_S;
+--testword0(5) <= prev_pulseactive_highgain_S;
+--testword0(6) <= singlepulse_highgain_S;
+--testword0(7) <= pileuppulse_highgain_S;
+--testword0(8) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;
+--testword0(9) <= pulse_highgain_toowide_S;
+--
+--testword0(15 downto 10) <= counter_highgain_S(5 downto 0);
+--testword0(16) <= pulse_active_lowgain;
+--testword0(17) <= pulse_rising_lowgain;
+--testword0(18) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;
+--testword0(19) <= pulse_lowgain_toolong_S;
+--testword0(20) <= prev_pulse_lowgain_toolong_S;
+--testword0(21) <= prev_pulseactive_lowgain_S;
+--testword0(22) <= singlepulse_lowgain_S;
+--testword0(23) <= pileuppulse_lowgain_S;
+--testword0(24) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;
+--testword0(25) <= pulse_lowgain_toowide_S;
+--
+--testword0(31 downto 26) <= counter_lowgain_S(5 downto 0);
+--
+--testword0(32) <= singlepulse_lowgain_occured_S;
+--testword0(33) <= pileuppulse_lowgain_occured_S;
+--testword0(34) <= clearpulse_highgain_S;
+--testword0(35) <= clearpulse_lowgain_S;
+
+
+testword0(22) <= pulse_active_highgain;
+testword0(23) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;
+testword0(24) <= singlepulse_highgain_S;
+testword0(25) <= pileuppulse_highgain_S;
+testword0(26) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;
+testword0(27) <= pulse_active_lowgain;
+testword0(28) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;
+testword0(29) <= singlepulse_lowgain_S;
+testword0(30) <= pileuppulse_lowgain_S;
+testword0(31) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;
+testword0(32) <= singlepulse_lowgain_occured_S;
+testword0(33) <= pileuppulse_lowgain_occured_S;
+testword0(34) <= clearpulse_highgain_S;
+testword0(35) <= clearpulse_lowgain_S;
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd b/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd
new file mode 100644
index 0000000..b38a36a
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd
@@ -0,0 +1,192 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-09-2014
+-- Module Name: FEE_pulse2to1_pulse
+-- Description: Get hit-members from high and low gain input and put in a 36-bits wide stream
+-- Modifications:
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulse2to1_pulse
+-- Get hit-members from high and low gain input and put in a 36-bits wide stream.
+-- The members are:
+-- superburstnumber, timestamp,
+-- CF_signal before and after zero-crossing,
+-- two samples at the maximum of the pulse,
+-- status that indicates if a previous pulse was skipped
+--
+-- The output data consist of packets with three 36-bits each containing the members of one hit:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- channel : adc index
+-- pulse1_write : write signal for the input signal from first input
+-- pulse1_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse1_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse1_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse1_energy : energy of the pulse : scaled integral
+-- pulse1_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse1_CF2 : CF_signal value of the value after the zero-crossing (absolute value)
+-- pulse2_write : write signal for the input signal from second input
+-- pulse2_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse2_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse2_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse2_energy : energy of the pulse : scaled integral
+-- pulse2_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse2_CF2 : CF_signal value of the value after the zero-crossing (absolute value)
+-- data_out_almostfull : target fifo is almost full : discard data-packet and report skipped pulse at next hit-result packet
+-- data_out_allowed : writing of resulting data allowed
+--
+-- outputs
+-- pulse_skipped : indicates that a hit is skipped (buffer overrun or faulty constant fraction)
+-- data2_in_allowed : signal to allow data input 2
+-- data_out : 36-bits data with valid pulse waveform:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_write : write signal for 36-bits output data
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulse2to1_pulse is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ channel : in std_logic_vector(7 downto 0);
+ pulse1_write : in std_logic;
+ pulse1_superburst : in std_logic_vector(15 downto 0);
+ pulse1_timestamp : in std_logic_vector(15 downto 0);
+ pulse1_skipped : in std_logic;
+ pulse1_energy : in std_logic_vector(15 downto 0);
+ pulse1_CF1 : in std_logic_vector(15 downto 0);
+ pulse1_CF2 : in std_logic_vector(15 downto 0);
+ pulse2_write : in std_logic;
+ pulse2_superburst : in std_logic_vector(15 downto 0);
+ pulse2_timestamp : in std_logic_vector(15 downto 0);
+ pulse2_skipped : in std_logic;
+ pulse2_energy : in std_logic_vector(15 downto 0);
+ pulse2_CF1 : in std_logic_vector(15 downto 0);
+ pulse2_CF2 : in std_logic_vector(15 downto 0);
+ pulse_skipped : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_almostfull : in std_logic;
+ data_out_allowed : in std_logic
+ );
+end FEE_pulse2to1_pulse;
+
+
+architecture Behavioral of FEE_pulse2to1_pulse is
+constant zeros : std_logic_vector(35 downto 0) := (others => '0');
+signal select2_S : std_logic;
+signal select2b_S : std_logic := '0';
+signal writeindex_S : integer range 0 to 2 := 0;
+signal pulse1_skipped_S : std_logic := '0';
+signal pulse2_skipped_S : std_logic := '0';
+signal pulse1_skipbit_S : std_logic;
+signal pulse2_skipbit_S : std_logic;
+
+begin
+
+pulse_skipped <= '1' when (pulse1_skipped_S='1') or (pulse2_skipped_S='1') else '0';
+
+select2_S <=
+ '0' when ((writeindex_S=0) and (pulse1_write='1')) else
+ '1' when ((writeindex_S=0) and (pulse2_write='1')) else
+ select2b_S;
+data_out <=
+ "00" & '0' & pulse1_skipbit_S & pulse1_superburst & pulse1_timestamp when (select2_S='0') and (writeindex_S=0) else
+ "00" & '1' & pulse2_skipbit_S & pulse2_superburst & pulse2_timestamp when (select2_S='1') and (writeindex_S=0) else
+ "01" & "00" & x"00" & channel(7 downto 1) & '0' & pulse1_energy when (select2_S='0') and (writeindex_S=1) else
+ "01" & "00" & x"00" & channel(7 downto 1) & '1' & pulse2_energy when (select2_S='1') and (writeindex_S=1) else
+ "10" & "00" & pulse1_CF1 & pulse1_CF2 when (select2_S='0') and (writeindex_S=2) else
+ "10" & "00" & pulse2_CF1 & pulse2_CF2; -- when (select2_S='1') and (writeindex_S=2) else
+pulse1_skipbit_S <= '1' when (pulse1_skipped_S='1') or (pulse1_skipped='1') else '0';
+pulse2_skipbit_S <= '1' when (pulse2_skipped_S='1') or (pulse2_skipped='1') else '0';
+
+data_out_write <= '1' when
+ ((writeindex_S=0) and (data_out_almostfull='0') and (data_out_allowed='1') and ((pulse1_write='1') or (pulse2_write='1'))) or
+ ((writeindex_S=1) or (writeindex_S=2))
+ else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ select2b_S <= '0';
+ writeindex_S <= 0;
+ else
+ if (writeindex_S=0) then
+ if (data_out_almostfull='0') and (data_out_allowed='1') then
+ if pulse1_write='1' then
+ select2b_S <= '0';
+ writeindex_S <= 1;
+ elsif pulse2_write='1' then
+ select2b_S <= '1';
+ writeindex_S <= 1;
+ end if;
+ end if;
+ elsif writeindex_S=1 then
+ writeindex_S <= 2;
+ else
+ writeindex_S <= 0;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ pulse1_skipped_S <= '0';
+ else
+ if (pulse1_write='1') and
+ ((data_out_almostfull='1') or (data_out_allowed='0') or (writeindex_S/=0)) then
+ pulse1_skipped_S <= '1';
+ elsif writeindex_S=2 then
+ pulse1_skipped_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ pulse2_skipped_S <= '0';
+ else
+ if (pulse2_write='1') and
+ ((data_out_almostfull='1') or (data_out_allowed='0') or (writeindex_S/=0)) then
+ pulse2_skipped_S <= '1';
+ elsif writeindex_S=2 then
+ pulse2_skipped_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd b/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd
new file mode 100644
index 0000000..5cc71af
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd
@@ -0,0 +1,561 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_pulse_and_pileup_waveforms
+-- Description: Multiple adc inputs with output stream for pulse-waveforms and pileup-waveforms, dual gain version
+-- Modifications:
+-- 08-09-2014 Part of Constant Fraction calculation moved to input module (before mux)
+-- 22-09-2014 single clock
+-- 23-09-2014 sort pileup waveforms
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+library work;
+USE work.panda_package.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulse_and_pileup_waveforms
+-- Multiple adc inputs with output stream for pulse-waveforms and pileup-waveforms.
+-- on each input pulses are detected and the waveform is put in a buffer.
+-- A timestamp is added, based on maximum signal in waveform.
+-- From each high-gain and low-gain input pair only one waveform at the same time is choosen and passed on.
+-- The waveform are distinguish for single pulse and pileup waveforms.
+-- The single pulse waveforms are sorted, based on timestamp, and multiplexed to one stream.
+-- The pileup waveforms multiplexed to one stream (unsorted).
+-- The parameters are organised in registers A,B,C,D :
+-- board_register A: write
+-- register_A(7..0) = threshold High
+-- register_A(15..8) = threshold Low
+-- register_A(16) = disable High
+-- register_A(17) = disable Low
+-- register_A(23..18) = I/Max discard
+-- register_A(29..24) = I/Max pileup
+-- board_register B: write
+-- register_B(7..0) = minimum pulselength
+-- register_B(15..8) = pileup length
+-- register_B(23..16) = maximum wavelength
+-- register_B(24) = fullsize High
+-- register_B(25) = fullsize Low
+-- register_B(29..26) = CF delay
+--
+--
+-- generics
+-- NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
+-- ADCBITS : number of ADC-bits
+-- BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+--
+-- inputs
+-- clock : clock
+-- reset : synchrounous reset
+-- superburstnumber : actual superburstnumber
+-- timestampcounter : timestampcounter within superburst
+-- ADCdata : array with ADC data for each input
+-- enable_data : enable adc data
+-- slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
+-- slowcontrol_byte_write : write signal for the slowcontrol commands
+-- slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
+-- pulsedata_read : read signal for data with resulting single pulse waveforms
+-- pileupdata_read : read signal for data with resulting pileup waveforms
+--
+-- outputs
+-- pulsedata_out : 36 bits output data with resulting single pulse waveforms:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- pulsedata_available : output single pulse data is available
+-- pulsedata_inpipe : more single pulse data on its way
+-- pileupdata_out : 36-bits output data with resulting pileup waveforms:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..16) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- pileupdata_available : output pileup data is available
+-- pileupdata_inpipe : more pileup data on its way
+-- pulsedetect : pulse detected for each of the ADC channels
+-- overflow : overflow in data from one of the channels: data is lost
+--
+-- components
+-- FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair
+-- FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp
+-- FEE_sorting_wavemux : sorted multiplexer for waveform data
+-- FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulse_and_pileup_waveforms is
+ generic (
+ NROFADCS : natural := 16;
+ ADCBITS : natural := 14;
+ BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADCdata : in array_adc_type;
+ enable_data : in std_logic;
+ slowcontrol_byte_data : in std_logic_vector (7 downto 0);
+ slowcontrol_byte_write : in std_logic;
+ slowcontrol_byte_request: in std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_read : in std_logic;
+ pulsedata_available : out std_logic;
+ pulsedata_inpipe : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_read : in std_logic;
+ pileupdata_available : out std_logic;
+ pileupdata_inpipe : out std_logic;
+ pulsedetect : out std_logic_vector(0 to NROFADCS-1);
+ overflow : out std_logic;
+ testindex : in integer range 0 to NROFADCS/2-1;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end FEE_pulse_and_pileup_waveforms;
+
+architecture Behavioral of FEE_pulse_and_pileup_waveforms is
+
+component FEE_dual_pulse_waveform is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ enable_highgain : in std_logic;
+ enable_lowgain : in std_logic;
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
+ ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
+ pulsedata_allowed : in std_logic;
+ pulsedata_almostfull : in std_logic;
+ pulsedata_write : out std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ pileupdata_write : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pulsedetect : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_sorting_mux is
+ generic(
+ NROFMUXINPUTS : natural := NROFADCS/2
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+
+component FEE_sorting_wavemux is
+ generic(
+ NROFMUXINPUTS : natural := NROFADCS/2
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_slowcontrol_receive_from_cpu is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(7 downto 0);
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ register_A : out std_logic_vector (31 downto 0);
+ register_B : out std_logic_vector (31 downto 0)
+ );
+end component;
+
+constant zeros : std_logic_vector(0 to NROFADCS/2-1) := (others => '0');
+signal ADCdata_S : array_adc_type;
+signal enable_high_S : std_logic_vector(0 to NROFADCS/2-1);
+signal enable_low_S : std_logic_vector(0 to NROFADCS/2-1);
+signal adcnumber_S : array_halfadc8bits_type;
+signal pulsedata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_write_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_out_S : array_halfadc36bits_type;
+signal pulsedata_inpipe_S : std_logic;
+signal pileupdata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pileupdata_write_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pileupdata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pileupdata_out_S : array_halfadc36bits_type;
+signal overflow_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_available_S : std_logic;
+signal pileupdata_available_S : std_logic;
+signal pileupdata_inpipe_S : std_logic;
+
+signal pulsedetect_S : std_logic_vector(0 to NROFADCS-1);
+signal pileupdata_output_S : std_logic_vector(35 downto 0);
+
+signal register_A_S : array_halfadc32bits_type := (others => (others => '0'));
+signal register_B_S : array_halfadc32bits_type := (others => (others => '0'));
+
+signal dataerrors_S : std_logic_vector(0 to NROFADCS/2-1);
+
+signal testword0_S : array_halfadc36bits_type;
+signal testword1_S : array_halfadc36bits_type;
+signal testword2_S : array_halfadc36bits_type;
+
+
+begin
+
+
+ waves : for index in 0 to NROFADCS/2-1 generate
+
+ FEE_slowcontrol_receive_from_cpu_all: FEE_slowcontrol_receive_from_cpu port map(
+ clock => clock,
+ reset => reset,
+ address => conv_std_logic_vector(index*2,8),
+ byte_data => slowcontrol_byte_data,
+ byte_write => slowcontrol_byte_write,
+ byte_request => slowcontrol_byte_request,
+ register_A => register_A_S(index),
+ register_B => register_B_S(index));
+
+ adcnumber_S(index) <= conv_std_logic_vector(index*2,8);
+ process(clock)
+ begin
+ if (rising_edge(clock)) then
+ enable_high_S(index) <= not register_A_S(index)(16);
+ enable_low_S(index) <= not register_A_S(index)(17);
+ end if;
+ end process;
+ ADCdata_S(index*2) <= ADCdata(index*2);-- when enable_high_S(index)='1' else (others => '0');
+ ADCdata_S(index*2+1) <= ADCdata(index*2+1);-- when enable_low_S(index)='1' else (others => '0');
+
+ FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform port map(
+ clock => clock,
+ reset => reset,
+ enable => enable_data,
+ adcnumber => adcnumber_S(index),
+ cf_delay => register_B_S(index)(29 downto 26),
+ superburstnumber => superburstnumber,
+ timestampcounter => timestampcounter,
+ ADCdata_highgain => ADCdata_S(index*2),
+ ADCdata_lowgain => ADCdata_S(index*2+1),
+ threshold_highgain(7 downto 0) => register_A_S(index)(7 downto 0),
+ threshold_highgain((ADCBITS-1) downto 8) => (others => '0'),
+ threshold_lowgain(7 downto 0) => register_A_S(index)(15 downto 8),
+ threshold_lowgain((ADCBITS-1) downto 8) => (others => '0'),
+ enable_highgain => enable_high_S(index),
+ enable_lowgain => enable_low_S(index),
+ IIRfilterBW => (others => '0'),
+ maxabovebaseline => "1010",
+ minpulselength => register_B_S(index)(7 downto 0),
+ pileuplength => register_B_S(index)(15 downto 8),
+ maxwavelength => register_B_S(index)(23 downto 16),
+ IdivMAX_discard => register_A_S(index)(IDIVMAXBITS+17 downto 18),
+ IdivMAX_pileup => register_A_S(index)(IDIVMAXBITS+23 downto 24),
+ fullsize_wave_highgain => register_B_S(index)(24),
+ fullsize_wave_lowgain => register_B_S(index)(25),
+ ADC_minus_baseline_highgain => open, -- testword0_S(idx)(14 downto 0),
+ ADC_minus_baseline_lowgain => open, -- testword0_S(idx)(30 downto 16),
+ pulsedata_allowed => pulsedata_allowed_S(index),
+ pulsedata_almostfull => pulsedata_almostfull_S(index),
+ pulsedata_write => pulsedata_write_S(index),
+ pulsedata_out => pulsedata_out_S(index),
+ pileupdata_allowed => pileupdata_allowed_S(index),
+ pileupdata_almostfull => pileupdata_almostfull_S(index),
+ pileupdata_write => pileupdata_write_S(index),
+ pileupdata_out => pileupdata_out_S(index),
+ pulsedetect => pulsedetect_S(index),
+ overflow => overflow_S(index),
+ testword0 => testword0_S(index),
+ testword1 => testword1_S(index),
+ testword2 => testword2_S(index));
+
+process(clock)
+type array_halfadc4bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(3 downto 0);
+variable prev_data_V : array_halfadc4bits_type;
+begin
+ if rising_edge(clock) then
+ dataerrors_S(index) <= '0';
+ if pileupdata_write_S(index)='1' then
+ case pileupdata_out_S(index)(35 downto 32) is
+ when "0000" =>
+ if (prev_data_V(index)/="0100") and (prev_data_V(index)/="0101") then
+ dataerrors_S(index) <= '1';
+ end if;
+ when "0001" =>
+ if (prev_data_V(index)/="0000") then
+ dataerrors_S(index) <= '1';
+ end if;
+ when "0010" =>
+ if (prev_data_V(index)/="0001") and (prev_data_V(index)/="0010") then
+ dataerrors_S(index) <= '1';
+ end if;
+ when "0100" =>
+ if (prev_data_V(index)/="0010") then
+ dataerrors_S(index) <= '1';
+ end if;
+ when "0101" =>
+ if (prev_data_V(index)/="0010") then
+ dataerrors_S(index) <= '1';
+ end if;
+ when others =>
+ dataerrors_S(index) <= '1';
+ end case;
+ prev_data_V(index) := pileupdata_out_S(index)(35 downto 32);
+ end if;
+ end if;
+end process;
+
+ end generate;
+overflow <= '1' when overflow_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';
+pulsedetect_S(NROFADCS/2 to NROFADCS-1) <= (others => '0');
+pulsedetect <= pulsedetect_S;
+
+FEE_sorting_mux1: FEE_sorting_mux port map(
+ clock => clock,
+ reset => reset,
+ data_in => pulsedata_out_S,
+ data_in_write => pulsedata_write_S,
+ data_in_allowed => pulsedata_allowed_S,
+ data_in_almostfull => pulsedata_almostfull_S,
+ data_out => pulsedata_out,
+ data_out_read => pulsedata_read,
+ data_out_available => pulsedata_available_S,
+ data_out_inpipe => pulsedata_inpipe_S,
+ error => open,
+ testword0 => open,
+ testword1 => open);
+pulsedata_available <= pulsedata_available_S;
+pulsedata_inpipe <= pulsedata_inpipe_S;
+
+-- FEE_sorting_wavemux_pileup: FEE_sorting_wavemux port map(
+FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
+ clock => clock,
+ reset => reset,
+ data_in => pileupdata_out_S,
+ data_in_write => pileupdata_write_S,
+ data_in_allowed => pileupdata_allowed_S,
+ data_in_almostfull => pileupdata_almostfull_S,
+ data_out => pileupdata_output_S,
+ data_out_read => pileupdata_read,
+ data_out_available => pileupdata_available_S,
+ data_out_inpipe => pileupdata_inpipe_S,
+ error => open,
+ testword0 => open,
+ testword1 => open);
+pileupdata_available <= pileupdata_available_S;
+pileupdata_out <= pileupdata_output_S;
+pileupdata_inpipe <= pileupdata_inpipe_S;
+
+
+
+--process(clock)
+--type array_16_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
+--type array_8_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
+--variable l1 : line;
+--variable l2 : line;
+--variable c : std_logic_vector(63 downto 0) := x"0000000000000000";
+--variable pulse_time_V : array_16_type;
+--variable pulse_sb_V : array_16_type;
+--variable pulse_energy_V : array_16_type;
+--variable pulse_chan_V : array_8_type;
+--variable wave_time_V : array_16_type;
+--variable wave_sb_V : array_16_type;
+--variable wave_chan_V : array_8_type;
+--file file0: text;
+--file file1: text;
+--begin
+-- if rising_edge(clock) then
+-- if c=x"0000000000000000" then
+-- file_open(file0,"D:\data\Panda\pulses.txt",WRITE_MODE);
+-- file_open(file1,"D:\data\Panda\waves.txt",WRITE_MODE);
+-- end if;
+-- c := c+1;
+-- for i in 0 to NROFADCS/2-1 loop
+-- if pulsedata_write_S(i)='1' then
+-- if pulsedata_out_S(i)(35 downto 34)="00" then
+-- pulse_sb_V(i) := pulsedata_out_S(i)(31 downto 16);
+-- pulse_time_V(i) := pulsedata_out_S(i)(15 downto 0);
+-- elsif pulsedata_out_S(i)(35 downto 34)="01" then
+-- pulse_chan_V(i) := pulsedata_out_S(i)(23 downto 16);
+-- pulse_energy_V(i) := pulsedata_out_S(i)(15 downto 0);
+-- hwrite(l1,c,right,16);
+-- write(l1," ");
+-- hwrite(l1,pulse_sb_V(i),right,4);
+-- write(l1," ");
+-- hwrite(l1,pulse_time_V(i),right,4);
+-- write(l1," ");
+-- hwrite(l1,pulse_chan_V(i),right,2);
+-- write(l1," ");
+-- hwrite(l1,pulse_energy_V(i),right,4);
+-- writeline(file0,l1);
+-- end if;
+-- end if;
+-- if pileupdata_write_S(i)='1' then
+-- if pileupdata_out_S(i)(35 downto 32) ="0000" then
+-- wave_sb_V(i) := pileupdata_out_S(i)(31 downto 16);
+-- wave_time_V(i) := pileupdata_out_S(i)(15 downto 0);
+-- elsif pileupdata_out_S(i)(35 downto 32) ="0001" then
+-- wave_chan_V(i) := pileupdata_out_S(i)(7 downto 0);
+-- hwrite(l2,c,right,16);
+-- write(l2," ");
+-- hwrite(l2,wave_sb_V(i),right,4);
+-- write(l2," ");
+-- hwrite(l2,wave_time_V(i),right,4);
+-- write(l2," ");
+-- hwrite(l2,wave_chan_V(i),right,2);
+-- writeline(file1,l2);
+-- end if;
+-- end if;
+-- end loop;
+-- end if;
+--end process;
+
+
+
+testword0(33 downto 0) <= testword0_S(testindex)(33 downto 0);
+testword0(35) <= testword0_S(testindex)(35);
+testword0(34) <= '1' when
+ (testword0_S(0)(35)='1') or
+ (testword0_S(1)(35)='1') or
+ (testword0_S(2)(35)='1') or
+ (testword0_S(3)(35)='1') or
+ (testword0_S(4)(35)='1') or
+ (testword0_S(5)(35)='1') or
+ (testword0_S(6)(35)='1') or
+ (testword0_S(7)(35)='1') or
+ (testword0_S(8)(35)='1') or
+ (testword0_S(9)(35)='1') or
+ (testword0_S(10)(35)='1') or
+ (testword0_S(11)(35)='1') or
+ (testword0_S(12)(35)='1') or
+ (testword0_S(13)(35)='1') or
+ (testword0_S(14)(35)='1') or
+ (testword0_S(15)(35)='1') else '0';
+
+
+
+
+testword1(15 downto 0) <= testword1_S(0)(15 downto 0);
+testword1(31 downto 16) <= dataerrors_S;
+testword1(32) <= '1' when dataerrors_S/=x"0000";
+testword1(35) <= testword0_S(testindex)(28);
+testword1(34) <= '1' when
+ (testword0_S(0)(35)='1') or
+ (testword0_S(1)(35)='1') or
+ (testword0_S(2)(35)='1') or
+ (testword0_S(3)(35)='1') or
+ (testword0_S(4)(35)='1') or
+ (testword0_S(5)(35)='1') or
+ (testword0_S(6)(35)='1') or
+ (testword0_S(7)(35)='1') or
+ (testword0_S(8)(35)='1') or
+ (testword0_S(9)(35)='1') or
+ (testword0_S(10)(35)='1') or
+ (testword0_S(11)(35)='1') or
+ (testword0_S(12)(35)='1') or
+ (testword0_S(13)(35)='1') or
+ (testword0_S(14)(35)='1') or
+ (testword0_S(15)(35)='1') else '0';
+
+testword2(33 downto 0) <= testword2_S(testindex)(33 downto 0);
+testword2(35) <= testword0_S(testindex)(35);
+testword2(34) <= testword0_S(testindex)(28);
+--testword2(34) <= '1' when
+-- (testword0_S(0)(35)='1') or
+-- (testword0_S(1)(35)='1') or
+-- (testword0_S(2)(35)='1') or
+-- (testword0_S(3)(35)='1') or
+-- (testword0_S(4)(35)='1') or
+-- (testword0_S(5)(35)='1') or
+-- (testword0_S(6)(35)='1') or
+-- (testword0_S(7)(35)='1') or
+-- (testword0_S(8)(35)='1') or
+-- (testword0_S(9)(35)='1') or
+-- (testword0_S(10)(35)='1') or
+-- (testword0_S(11)(35)='1') or
+-- (testword0_S(12)(35)='1') or
+-- (testword0_S(13)(35)='1') or
+-- (testword0_S(14)(35)='1') or
+-- (testword0_S(15)(35)='1') else '0';
+
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd b/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd
new file mode 100644
index 0000000..e4d51f9
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd
@@ -0,0 +1,302 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 31-01-2012
+-- Module Name: FEE_pulsewaveform_buffer
+-- Description: Buffers pulse waveforms
+-- Modifications:
+-- 08-09-2014 Removed waveform output in case of pulse detection
+-- 16-09-2014 name changed from pulsewaveform_buffer to FEE_pulsewaveform_buffer
+-- 10-10-2014 separated input for superburst
+-- 23-10-2014 space enough signal more accurate
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulsewaveform_buffer
+-- Buffers adc waveforms.
+-- Memory is configured as ring buffer: samples are written into this buffer when a pulse is being detected.
+-- Also, a timestamp is written into the memory.
+-- Data can be read when at least one waveform is written.
+--
+--
+-- generics
+-- ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- pulse_valid : input data is valid pulse data
+-- pulse_rising : the pulse has not yet reached its maximum
+-- pulse_detected : previous samples are regarded as valid pulse data
+-- pileup_detected : previous samples are regarded as pileup waveform data
+-- clear_waveform : previous samples do not give valid data, clear this data
+-- data_in : input data: adc values minus baseline: signed data
+-- superburst : superburst at the starting of the waveform
+-- timestamp : timestamp (within the superburst) at the starting of the waveform
+-- data_out_read : read data from the buffer memory
+--
+-- outputs
+-- data_out : data from the buffer memory
+-- bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform (combination superburst and clockcounter)
+-- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
+-- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
+-- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
+-- bits(35..32)="1111" : error, bits(31..0)=don't care
+-- data_out_available : data available from the buffer memory
+-- overflow : buffer overrun
+--
+--
+-- components
+-- blockmem : buffer memory, dual ported ram
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulsewaveform_buffer is
+ generic (
+ ADCBITS : natural := 14;
+ WAVEFORMBUFFERSIZE : natural := 10
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ superburst : in std_logic_vector(15 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_pulsewaveform_buffer;
+
+architecture Behavioral of FEE_pulsewaveform_buffer is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := WAVEFORMBUFFERSIZE;
+ DATA_BITS : natural := 36
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal data_in_S : std_logic_vector(15 downto 0) := (others => '0');
+signal sample0_S : std_logic_vector(15 downto 0) := (others => '0');
+signal write_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := zeros(WAVEFORMBUFFERSIZE-1 downto 2) & "10";
+-- signal write_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := "00000010";
+signal write_enable_S : std_logic := '0';
+signal write_data_S : std_logic_vector(35 downto 0) := (others => '0');
+
+signal wavestart_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal nextstart_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+
+signal read_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal read_data_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_available_S : std_logic := '0';
+signal pileup_detected_S : std_logic := '0';
+signal pulse_rising_S : std_logic := '0';
+signal prev_pulse_valid_S : std_logic := '0';
+
+signal lastsample_even_S : std_logic := '0';
+signal space_enough_S : std_logic := '0';
+
+
+type writemode_type is (ACQUIRE_EVEN,ACQUIRE_ODD,TIMESTAMP0,SKIPPULSE);
+signal writemode_S : writemode_type := ACQUIRE_EVEN;
+
+
+begin
+
+overflow <= '1' when writemode_S=SKIPPULSE else '0';
+
+space_enough_S <= '1' when
+ (((conv_integer(unsigned(nextstart_address_S)))<(conv_integer(unsigned(read_address_S))))
+ and ((conv_integer(unsigned(nextstart_address_S))+130)<(conv_integer(unsigned(read_address_S))))) or
+ (((conv_integer(unsigned(nextstart_address_S)))>(conv_integer(unsigned(read_address_S))))
+ and ((conv_integer(unsigned(nextstart_address_S))+130)<(conv_integer(unsigned(read_address_S))+2**WAVEFORMBUFFERSIZE))) or
+ ((conv_integer(unsigned(nextstart_address_S)))=(conv_integer(unsigned(read_address_S))))
+ else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ data_in_S(ADCBITS downto 0) <= data_in;
+ -- data_in_S(15 downto ADCBITS+1) <= (others => '0');
+ data_in_S(15) <= data_in_S(14);
+ pulse_rising_S <= pulse_rising;
+ end if;
+end process;
+
+blockmem1: blockmem port map(
+ clock => clock,
+ write_enable => write_enable_S,
+ write_address => write_address_S,
+ data_in => write_data_S,
+ read_address => read_address_S,
+ data_out => read_data_S);
+data_out <= read_data_S;
+
+write_data_S <=
+ "1000" & superburst & timestamp when ((writemode_S=TIMESTAMP0) and (pileup_detected_S='1')) else
+ "0100" & data_in_S & x"0000" when ((pileup_detected='1') and (writemode_S=ACQUIRE_EVEN)) else
+ "0101" & sample0_S & data_in_S when ((pileup_detected='1') and (writemode_S=ACQUIRE_ODD)) else
+ "0010" & sample0_S & data_in_S when ((pulse_valid='1') and (writemode_S=ACQUIRE_ODD)) else
+ (others => '1');
+
+
+write_enable_S <= '1'
+ when ((pulse_valid='1') and (writemode_S=ACQUIRE_ODD))
+ or ((writemode_S=ACQUIRE_EVEN) and (pileup_detected='1'))
+ or ((writemode_S=ACQUIRE_ODD) and (pileup_detected='1'))
+ or (writemode_S=TIMESTAMP0)
+ else '0';
+
+writeprocess: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ write_address_S <= conv_std_logic_vector(2,WAVEFORMBUFFERSIZE);
+ wavestart_address_S <= (others => '0');
+ nextstart_address_S <= (others => '0');
+ pileup_detected_S <= '0';
+ lastsample_even_S <= '0';
+ writemode_S <= ACQUIRE_EVEN;
+ else
+ prev_pulse_valid_S <= pulse_valid;
+ case writemode_S is
+ when ACQUIRE_EVEN =>
+ if (pileup_detected='1') then
+ pileup_detected_S <= '1';
+ write_address_S <= wavestart_address_S; -- for timestamp
+ nextstart_address_S <= write_address_S+1;
+ lastsample_even_S <= '1';
+ writemode_S <= TIMESTAMP0;
+ elsif (clear_waveform='1') or (pulse_detected='1') then
+ write_address_S <= wavestart_address_S+1;
+ pileup_detected_S <= '0';
+ else
+ if pulse_valid='1' then
+ if (space_enough_S='1') or (prev_pulse_valid_S='1') then
+ sample0_S <= data_in_S;
+ writemode_S <= ACQUIRE_ODD;
+ else
+ writemode_S <= SKIPPULSE;
+ end if;
+ else
+ write_address_S <= wavestart_address_S+1; -- restart
+ end if;
+ pileup_detected_S <= '0';
+ end if;
+ when ACQUIRE_ODD =>
+ if (pileup_detected='1') then
+ pileup_detected_S <= '1';
+ write_address_S <= wavestart_address_S; -- for timestamp
+ nextstart_address_S <= write_address_S+1;
+ lastsample_even_S <= '0';
+ writemode_S <= TIMESTAMP0;
+ elsif (clear_waveform='1') or (pulse_detected='1') then
+ write_address_S <= wavestart_address_S+1;
+ pileup_detected_S <= '0';
+ else
+ if pulse_valid='1' then
+ writemode_S <= ACQUIRE_EVEN;
+ write_address_S <= write_address_S+1;
+ else
+ write_address_S <= wavestart_address_S+1; -- restart
+ writemode_S <= ACQUIRE_EVEN;
+ end if;
+ pileup_detected_S <= '0';
+ end if;
+ when TIMESTAMP0 =>
+ write_address_S <= nextstart_address_S+1;
+ wavestart_address_S <= nextstart_address_S;
+ if pulse_valid='1' then
+ if space_enough_S='1' then
+ sample0_S <= data_in_S;
+ writemode_S <= ACQUIRE_ODD;
+ else
+ writemode_S <= SKIPPULSE;
+ end if;
+ else
+ writemode_S <= ACQUIRE_EVEN;
+ end if;
+ when SKIPPULSE =>
+ if pulse_valid='0' then
+ writemode_S <= ACQUIRE_EVEN;
+ end if;
+ when others =>
+ writemode_S <= ACQUIRE_EVEN;
+ end case;
+ end if;
+ end if;
+end process;
+
+data_out_available_S <= '1'
+ when wavestart_address_S/=read_address_S
+ else '0';
+data_out_available <= data_out_available_S;
+
+readprocess: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ read_address_S <= (others => '0');
+ else
+ if (data_out_read='1') and (data_out_available_S='1') then
+ read_address_S <= read_address_S+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+testword0(1 downto 0) <=
+ "00" when (writemode_S=ACQUIRE_EVEN) else
+ "01" when (writemode_S=ACQUIRE_ODD) else
+ "10" when (writemode_S=TIMESTAMP0) else
+ "11" when (writemode_S=SKIPPULSE) else
+ "11";
+
+testword0(2) <= space_enough_S;
+testword0(3) <= pulse_valid;
+testword0(4) <= pulse_detected;
+testword0(5) <= pileup_detected;
+testword0(6) <= clear_waveform;
+testword0(7) <= write_enable_S;
+testword0(15 downto 8) <= write_address_S(7 downto 0);
+testword0(19 downto 16) <= write_data_S(35 downto 32);
+
+
+testword0(27 downto 20) <= read_address_S(7 downto 0);
+testword0(31 downto 28) <= read_data_S(35 downto 32);
+testword0(32) <= data_out_read;
+testword0(33) <= data_out_available_S;
+testword0(34) <= '0';
+
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_rxBitLock.vhd b/FEE_ADC32board/FEE_modules/FEE_rxBitLock.vhd
new file mode 100644
index 0000000..42e1f59
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_rxBitLock.vhd
@@ -0,0 +1,174 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Michel Hevinga / Peter Schakel
+-- Create Date: 2010
+-- Module Name: FEE_rxBitLock
+-- Description: Module to lock receiving clock of GTP/GTX at the right phase
+-- Modifications:
+-- 18-11-2014 8 bits data instead of 16 bits
+-- 19-11-2014 name changed from rxBitLock to FEE_rxBitLock
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+--use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_rxBitLock
+-- Module to lock receiving clock of GTP/GTX at the right phase.
+-- First is checked if the resetDone input is high, (resetting is done)
+-- then if lossOfSync is low ('0'), (GTP/GTX loss of sync signal)
+-- If all these checks are allright the fmstatus will show that the GTP/GTX is locked on th incomming data.
+-- If one of these checks are not reached within a certain time (TIME_OUT_SYNC_MAX constant)
+-- the rxReset output is activated and checking is started again.
+-- Also, the lossOfSync is always checked during operation.
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clk : recovered clock from the GTP/GTX
+-- reset : reset
+-- resetDone : Reset is done, ready to check lock & synchronisation
+-- lossOfSync : Loss of Sync: "00" means synchronised
+-- rxPllLocked : Receiver PLL locked, not used at the moment
+--
+-- Outputs:
+-- rxReset : Reset GTP/GTX to try another lock
+-- fsmStatus : Status of the state machine:
+-- 00 : WAIT_RESET_DONE : waiting until ResetDone
+-- 01 : WAIT_TIME_OUT_SYNC : waiting for word aligned
+-- 10 : CHECK_LOSS_SYNC : running state : keep on checking for Loss of sync and bytes swapped
+-- 11 : RX_RESET : resetting for a new lock attempt
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+entity FEE_rxBitLock is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0));
+end FEE_rxBitLock;
+
+architecture Behavioral of FEE_rxBitLock is
+
+constant TIME_OUT_SYNC_MAX : integer range 0 to 500 := 500;
+
+signal rxReset_S : std_logic :='0';
+signal fsmStatus_S : std_logic_vector (1 downto 0) :="00";
+signal timeOutSynFlag_S : std_logic :='0';
+signal timeOutSyncCounter_I : integer range 0 to TIME_OUT_SYNC_MAX :=0;
+
+signal resettimeFlag_S : std_logic :='0'; -- counter & flag for reset extender
+signal resettimeCounter_I : integer range 0 to 15 :=0; -- counter & flag for reset extender
+
+
+type state_T is (WAIT_RESET_DONE, WAIT_TIME_OUT_SYNC, CHECK_LOSS_SYNC, RX_RESET);
+signal currentState_S,nextState_S : state_T := WAIT_RESET_DONE;
+
+begin
+
+rxReset <= rxReset_S;
+fsmStatus <= fsmStatus_S;
+
+fsmClk: process(clk, reset)
+begin
+ if (reset = '1')then
+ currentState_S <= RX_RESET;
+ else
+ if rising_edge(clk) then
+ currentState_S <= nextState_S;
+ end if;
+ end if;
+end process;
+
+fsmInput: process (currentState_S,resetDone, timeOutSynFlag_S,
+ lossOfSync, rxPllLocked, timeOutSynFlag_S, resettimeFlag_S)
+begin
+ case currentState_S is
+ when WAIT_RESET_DONE => if(resetDone = '1') then
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ else
+ nextState_S <= WAIT_RESET_DONE;
+ end if;
+ when WAIT_TIME_OUT_SYNC => if (timeOutSynFlag_S = '1') then
+ nextState_S <= RX_RESET;
+ else
+ if (lossOfSync = '0') then
+ nextState_S <= CHECK_LOSS_SYNC;
+ else
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ end if;
+ end if;
+ when CHECK_LOSS_SYNC => if (lossOfSync /= '0') then
+ nextState_S <= RX_RESET;
+ else
+ nextState_S <= CHECK_LOSS_SYNC;
+ end if;
+ when RX_RESET => if (resettimeFlag_S = '1') then -- reset long to prevent that resetDone signal is missed
+ nextState_S <= WAIT_RESET_DONE;
+ else
+ nextState_S <= RX_RESET;
+ end if;
+ when others => nextState_S <= RX_RESET;
+ end case;
+end process;
+
+fsmOutput: process (clk)
+begin
+if rising_edge(clk) then
+ case currentState_S is
+ when WAIT_RESET_DONE => fsmStatus_S <= "00";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ when WAIT_TIME_OUT_SYNC => fsmStatus_S <= "01";
+ rxReset_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ if (timeOutSyncCounter_I < TIME_OUT_SYNC_MAX) then
+ timeOutSyncCounter_I <= timeOutSyncCounter_I+1;
+ timeOutSynFlag_S <= '0';
+ else
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '1';
+ end if;
+ when CHECK_LOSS_SYNC => fsmStatus_S <= "10";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+
+ when RX_RESET => fsmStatus_S <= "11";
+ rxReset_S <= '1';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ if resettimeCounter_I<8 then -- peter : reset langer gemaakt om te voorkomen dat resetDone signaal wordt gemist
+ resettimeCounter_I <= resettimeCounter_I+1;
+ resettimeFlag_S <= '0';
+ else
+ resettimeCounter_I <= 0;
+ resettimeFlag_S <= '1';
+ end if;
+
+ when others =>
+ end case;
+end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd
new file mode 100644
index 0000000..3584b1f
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd
@@ -0,0 +1,309 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 09-03-2011
+-- Module Name: FEE_slowcontrol_packet_receiver
+-- Description: Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board to Front End Electronics
+-- Modifications:
+-- 12-09-2014 New dataformat, name changed to FEE_slowcontrol_packet_receiver
+-- 22-09-2014 single clock
+-- 10-10-2014 bug with high rate of slow-control commands solved
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- FEE_slowcontrol_packet_receiver
+-- Gets packet data from the fiber receive module and analyses them.
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+-- The slow-control commands are written as byte-wise:
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- enable : enable receiving
+-- packet_data_in : 32 bits data input from fiber module
+-- packet_data_present : data available from fiber module
+-- slowcontrol_fifofull : connected fifo is full
+-- clear_hamming_corrections : clear the counter for the hamming-code corrections
+--
+-- Outputs:
+-- packet_data_read : read signal to fiber module to read next data
+-- byte_data : 8-bits slowcontrol data:
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+-- byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read
+-- byte_request : request signal for reading data
+-- data_error : error in packet-data : CRC-error, hamming-code error, error in data bits
+-- overflow : buffer overflow: slowcontrol data loss
+--
+-- Components:
+-- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words (only check here)
+-- sync_fifo_512x41 : fifo for slowcontrol commands
+--
+----------------------------------------------------------------------------------
+
+entity FEE_slowcontrol_packet_receiver is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ packet_data_in : in std_logic_vector (31 downto 0);
+ packet_data_present : in std_logic;
+ packet_data_read : out std_logic;
+ byte_data : out std_logic_vector(7 downto 0);
+ byte_write : out std_logic;
+ byte_request : out std_logic;
+ data_error : out std_logic;
+ overflow : out std_logic);
+end FEE_slowcontrol_packet_receiver;
+
+architecture Behavioral of FEE_slowcontrol_packet_receiver is
+
+component crc8_add_check32 is
+ PORT(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;
+ crc_error : out std_logic
+ );
+end component;
+
+component sync_fifo_512x41
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(40 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(40 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+
+type rec_state_type is (init,expect_first,slow1);
+signal rec_state_S : rec_state_type := init;
+
+signal error_S : std_logic;
+signal enable_S : std_logic;
+
+signal packet_data_read_S : std_logic;
+signal packet_data_valid_S : std_logic;
+
+signal crc8_data_in_S : std_logic_vector (31 downto 0);
+signal crc8_data_in_valid_S : std_logic := '0';
+signal crc8_data_in_last_S : std_logic := '0';
+signal crc8_data_out_S : std_logic_vector (31 downto 0);
+signal crc8_data_out_valid_S : std_logic := '0';
+signal crc8_data_out_last_S : std_logic := '0';
+signal crc8_error_S : std_logic := '0';
+signal crc8_slowerror_S : std_logic := '0';
+signal crc8_reset_S : std_logic := '0';
+signal crc8_clear_S : std_logic := '0';
+
+signal slowpacketvalid_S : std_logic := '0';
+signal slowcontrol_data_S : std_logic_vector (31 downto 0);
+signal slowcontrol_address_S : std_logic_vector (7 downto 0);
+signal slowcontrol_request_S : std_logic := '0';
+signal slowcontrol_write_S : std_logic := '0';
+
+signal slowcontrol_read_S : std_logic := '0';
+signal slowcontrol_read_after1clk_S : std_logic := '0';
+signal slowcontrol_fifoempty_S : std_logic := '0';
+
+signal byte_index_S : integer range 0 to 4 := 0;
+
+signal slowcontrol_dataout_S : std_logic_vector (31 downto 0);
+signal sfifo_in_S : std_logic_vector (40 downto 0);
+signal sfifo_out_S : std_logic_vector (40 downto 0);
+signal sfifo_full_S : std_logic := '0';
+
+begin
+
+data_error <= '1' when (crc8_slowerror_S='1') or (error_S='1') else '0';
+overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1')) else '0';
+
+packet_data_read <= packet_data_read_S;
+packet_data_read_S <= '1' when
+ (packet_data_present='1') and (reset='0') and (enable_S='1') and (rec_state_S/=init) else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ enable_S <= enable;
+ end if;
+end process;
+
+crc8_data_in_S <= packet_data_in;
+crc8_data_in_valid_S <= '1' when (packet_data_valid_S='1') or (rec_state_S=init) else '0';
+crc8_data_in_last_S <= '1' when (rec_state_S=slow1) or (rec_state_S=init) else '0';
+crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
+crc8check: crc8_add_check32 port map(
+ clock => clock,
+ reset => crc8_reset_S,
+ data_in => crc8_data_in_S,
+ data_in_valid => crc8_data_in_valid_S,
+ data_in_last => crc8_data_in_last_S,
+ data_out => crc8_data_out_S,
+ data_out_valid => crc8_data_out_valid_S,
+ data_out_last => crc8_data_out_last_S,
+ crc_error => crc8_error_S);
+
+inputdatahandling: process(clock)
+variable timeoutcounter_V : integer range 0 to 15 := 0;
+begin
+
+ if rising_edge(clock) then
+ crc8_clear_S <= '0';
+ if reset='1' then
+ error_S <= '0';
+ crc8_clear_S <= '1';
+ timeoutcounter_V := 0;
+ rec_state_S <= init;
+ else
+ case rec_state_S is
+ when init =>
+ timeoutcounter_V := 0;
+ rec_state_S <= expect_first;
+ when expect_first =>
+ timeoutcounter_V := 0;
+ if enable_S='0' then
+ rec_state_S <= expect_first;
+ else
+ if packet_data_valid_S='1' then
+ if packet_data_in(31 downto 24)=x"5C" then -- slowcontrol
+ slowcontrol_address_S <= packet_data_in(23 downto 16);
+ slowcontrol_request_S <= packet_data_in(15);
+ slowcontrol_data_S(31 downto 24) <= packet_data_in(7 downto 0);
+ error_S <= '0';
+ rec_state_S <= slow1;
+ else -- error
+ error_S <= enable_S;
+ crc8_clear_S <= '1';
+ end if;
+ end if;
+ end if;
+ when slow1 =>
+ if packet_data_valid_S='1' then
+ timeoutcounter_V := 0;
+ slowcontrol_data_S(23 downto 0) <= packet_data_in(31 downto 8);
+ rec_state_S <= expect_first;
+ else
+ if timeoutcounter_V=15 then
+ error_S <= enable_S;
+ rec_state_S <= expect_first;
+ else
+ timeoutcounter_V := timeoutcounter_V+1;
+ rec_state_S <= slow1;
+ end if;
+ end if;
+ end case;
+ end if;
+ packet_data_valid_S <= packet_data_read_S;
+ end if;
+
+end process inputdatahandling;
+
+slowcontrolpackethandling: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ slowcontrol_write_S <= '0';
+ slowpacketvalid_S <= '0';
+ crc8_slowerror_S <= '0';
+ else
+ if slowpacketvalid_S='0' then
+ slowcontrol_write_S <= '0';
+ crc8_slowerror_S <= '0';
+ if (rec_state_S=slow1) and (packet_data_valid_S='1') and (enable_S='1') then
+ slowpacketvalid_S <= '1';
+ end if;
+ else
+ slowpacketvalid_S <= '0';
+ if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
+ slowcontrol_write_S <= enable_S;
+ crc8_slowerror_S <= '0';
+ else
+ slowcontrol_write_S <= '0';
+ crc8_slowerror_S <= enable_S;
+ end if;
+ end if;
+ end if;
+ end if;
+end process slowcontrolpackethandling;
+
+sfifo_in_S(31 downto 0) <= slowcontrol_data_S;
+sfifo_in_S(39 downto 32) <= slowcontrol_address_S;
+sfifo_in_S(40) <= slowcontrol_request_S;
+
+sfifo: sync_fifo_512x41 port map(
+ rst => reset,
+ clk => clock,
+ din => sfifo_in_S,
+ wr_en => slowcontrol_write_S,
+ rd_en => slowcontrol_read_S,
+ dout => sfifo_out_S,
+ full => sfifo_full_S,
+ empty => slowcontrol_fifoempty_S);
+
+slowcontrol_read_S <= '1' when (slowcontrol_fifoempty_S='0') and ((byte_index_S=0) or (byte_index_S=4)) and (slowcontrol_read_after1clk_S='0') else '0';
+
+byteoutputprocess: process(clock)
+begin
+ if rising_edge(clock) then
+ byte_request <= '0';
+ byte_write <= '0';
+ if slowcontrol_read_after1clk_S='1' then
+ byte_data <= sfifo_out_S(39 downto 32); -- address
+ slowcontrol_dataout_S <= sfifo_out_S(31 downto 0); -- data
+ if sfifo_out_S(40)='1' then -- read request
+ byte_request <= '1';
+ byte_index_S <= 0;
+ else
+ byte_write <= '1';
+ byte_index_S <= 1;
+ end if;
+ elsif byte_index_S=1 then
+ byte_data <= slowcontrol_dataout_S(31 downto 24);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=2 then
+ byte_data <= slowcontrol_dataout_S(23 downto 16);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=3 then
+ byte_data <= slowcontrol_dataout_S(15 downto 8);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=4 then
+ byte_data <= slowcontrol_dataout_S(7 downto 0);
+ byte_write <= '1';
+ byte_index_S <= 0;
+ else
+ byte_index_S <= 0;
+ end if;
+ slowcontrol_read_after1clk_S <= slowcontrol_read_S;
+ end if;
+end process;
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd
new file mode 100644
index 0000000..9fb82b4
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd
@@ -0,0 +1,141 @@
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 21-03-2011
+-- Module Name: FEE_slowcontrol_receive_from_cpu
+-- Description: Module to receive slowcontrol data from soft-core cpu
+-- Modifications:
+-- 12-09-2014 Reduce nrof Registers to 2, replaced channel by address
+-- 22-09-2014 single clock
+-- 08-10-2014 error signal removed
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- FEE_slowcontrol_receive_from_cpu
+-- Module to receive byte-wise data from soft-core cpu and translates it into parallel register data.
+-- The byte-wise input data is sent to all connected modules as packets of 5 bytes.
+-- Byte0 : adc index and register index
+-- Byte1,2,3,4 : 32-bits data, MSB first
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock input and output
+-- reset : synchronous reset
+-- address : base-address of channel
+-- byte_data : 8-bits slowcontrol data:
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+-- byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read
+-- byte_request : request signal for reading data, here only used for check and synchronization
+--
+-- Outputs:
+-- register_A : 32-bits output register A
+-- register_B : 32-bits output register B
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_slowcontrol_receive_from_cpu is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(7 downto 0);
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ register_A : out std_logic_vector (31 downto 0);
+ register_B : out std_logic_vector (31 downto 0)
+ );
+end FEE_slowcontrol_receive_from_cpu;
+
+architecture Behavioral of FEE_slowcontrol_receive_from_cpu is
+
+
+signal byte_idx_S : integer range 0 to 4 := 0;
+signal selected_S : std_logic := '0';
+signal register_buf_S : std_logic_vector(31 downto 8);
+signal selected_reg_S : std_logic_vector(0 downto 0);
+
+signal register_A_S : std_logic_vector (31 downto 0) := x"12183264"; -- default FEE
+signal register_B_S : std_logic_vector (31 downto 0) := x"0C643208"; -- default FEE
+
+-- register_A(7..0) = threshold High
+-- register_A(15..8) = threshold Low
+-- register_A(16) = disable High
+-- register_A(17) = disable Low
+-- register_A(23..18) = I/Max discard
+-- register_A(29..24) = I/Max pileup
+-- register_B(7..0) = minimum pulselength
+-- register_B(15..8) = pileup length
+-- register_B(23..16) = maximum wavelength
+-- register_B(24) = fullsize High
+-- register_B(25) = fullsize Low
+-- register_B(29..26) = CF delay
+
+
+begin
+
+register_A <= register_A_S;
+register_B <= register_B_S;
+
+
+rd_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ byte_idx_S <= 0;
+ selected_S <= '0';
+ else
+ if byte_idx_S=0 then
+ if (byte_write='1') then
+ if (byte_data(7 downto 1)=address(7 downto 1)) then
+ selected_S <= '1';
+ selected_reg_S <= byte_data(0 downto 0);
+ else
+ selected_S <= '0';
+ end if;
+ byte_idx_S <= 1;
+ else
+ selected_S <= '0';
+ end if;
+ elsif byte_request='1' then -- unexpected : synchronize
+ selected_S <= '0';
+ byte_idx_S <= 0;
+ else
+ if selected_S='1' then
+ case byte_idx_S is
+ when 1 =>
+ register_buf_S(31 downto 24) <= byte_data;
+ when 2 =>
+ register_buf_S(23 downto 16) <= byte_data;
+ when 3 =>
+ register_buf_S(15 downto 8) <= byte_data;
+ when 4 =>
+ case selected_reg_S is
+ when "0" => register_A_S <= register_buf_S(31 downto 8) & byte_data;
+ when "1" => register_B_S <= register_buf_S(31 downto 8) & byte_data;
+ when others =>
+ end case;
+ when others =>
+ end case;
+ end if;
+ if byte_idx_S<4 then
+ byte_idx_S <= byte_idx_S+1;
+ else
+ byte_idx_S <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd b/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd
new file mode 100644
index 0000000..047a47e
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd
@@ -0,0 +1,398 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_sorting_mux
+-- Description: Multiplexer for FEE data, sorting on timestamp
+-- 11-09-2014: Output FIFO now with First Word Fall Through
+-- 22-09-2014: single clock
+-- 11-10-2014: adc-channel number 8 bits
+-- 16-10-2014: inpipe check
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_sorting_mux
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the 32-bits timestamp.
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+-- NROFMUXINPUTS : number of input-channels
+--
+-- Inputs:
+-- inputclock : clock for input data (write side incomming fifo)
+-- MUXclock : clock for multiplexer part, between the fifos
+-- outputclock : clock for output data (read side outgoing fifo)
+-- reset : reset, must be long enough for all clocks
+-- data_in : array of input data streams, structure of each (three 36-bits words):
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_in_write : write signal for data_in (write into fifo)
+-- data_out_read : read signal for outgoing data (read from fifo)
+--
+-- Outputs:
+-- data_in_allowed : write to input data allowed (not full)
+-- data_in_almostfull : input fifo is too full for maximum length waveform
+-- data_out : output data (three 36-bits words):
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_available : data_out available (output fifo not empty)
+-- data_out_inpipe : more data on its way
+-- error : data error, index in data words incorrect
+--
+-- Components:
+-- FEE_mux_readfifo : read data from fifo and writes to next level
+-- FEE_mux2to1 : compares the data and passes the first in time on
+-- sync_fifo_progfull504_progempty128_512x36 : synchronous fifo with programmable full and empty
+-- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_sorting_mux is
+ generic(
+ NROFMUXINPUTS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );
+end FEE_sorting_mux;
+
+
+architecture Behavioral of FEE_sorting_mux is
+
+component FEE_mux2to1 is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_mux_readfifo is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);
+end component;
+
+component sync_fifo_progfull504_progempty128_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_full : out std_logic;
+ prog_empty : out std_logic);
+end component;
+
+component sync_fifo_FWFT_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
+constant INPIPE_DELAY : integer := 63;
+constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+
+--type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;
+--constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);
+
+type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);
+type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;
+
+signal error_S : std_logic := '0';
+
+signal data_S : data_type;
+signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
+signal data_write_S : singlebit_type := (others => (others => '0'));
+signal data_allowed_S : singlebit_type := (others => (others => '0'));
+signal error_array_S : singlebit_type := (others => (others => '0'));
+
+signal reset_MUXclock_S : std_logic := '0';
+
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
+signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S : std_logic_vector (35 downto 0);
+signal tfifo_rd_S : std_logic := '0';
+signal tfifo_full_S : std_logic := '0';
+signal tfifo_empty_S : std_logic := '0';
+
+type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);
+signal testword0_S : testword_type;
+
+begin
+
+
+data_out_inpipe <= '1'
+ when dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')
+ else '0';
+
+
+MUX_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
+
+process(clock)
+type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
+variable inpipe_counter_V : inpipe_counter_type := (others => 0);
+variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ inpipe_counter_V(index) := 0;
+ delay_inpipe_S(index) <= '0';
+ else
+ index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
+ if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
+ ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
+ then
+ inpipe_counter_V(index) := INPIPE_DELAY;
+ delay_inpipe_S(index) <= '1';
+ else
+ if inpipe_counter_V(index)/=0 then
+ inpipe_counter_V(index) := inpipe_counter_V(index)-1;
+ delay_inpipe_S(index) <= '1';
+ else
+ delay_inpipe_S(index) <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+dfifo: sync_fifo_progfull504_progempty128_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => data_in(index),
+ wr_en => dfifo_wr_S(index),
+ rd_en => dfifo_rd_S(index),
+ dout => dfifo_out_S(index),
+ full => dfifo_full_S(index),
+ empty => dfifo_empty_S(index),
+ prog_full => data_in_almostfull(index),
+ prog_empty => dfifo_prog_empty_S(index));
+
+dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+
+data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';
+
+FEE_mux_readfifo1: FEE_mux_readfifo port map(
+ clock => clock,
+ reset => reset,
+ data_in => dfifo_out_S(index),
+ data_in_available => data_in_available_S(index),
+ data_in_read => dfifo_rd_S(index),
+ data_out => data_S(0,index),
+ data_out_write => data_write_S(0,index),
+ data_out_inpipe => read36_inpipe_S(index),
+ data_out_allowed => data_allowed_S(0,index));
+
+process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
+--variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+-- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
+-- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
+-- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
+ if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
+ (dfifo_wr_S(index)='1') then
+ data_out_inpipe_S(0,index) <= '1';
+ else
+ data_out_inpipe_S(0,index) <= '0';
+ end if;
+end process;
+
+end generate;
+
+
+MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate
+
+ MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+
+ FEE_mux2to1_1: FEE_mux2to1 port map(
+ clock => clock,
+ reset => reset,
+ data1_in => data_S(i1,i2*2),
+ data1_in_write => data_write_S(i1,i2*2),
+ data1_in_available => data_out_inpipe_S(i1,i2*2),
+ data1_in_allowed => data_allowed_S(i1,i2*2),
+ data2_in => data_S(i1,i2*2+1),
+ data2_in_write => data_write_S(i1,i2*2+1),
+ data2_in_available => data_out_inpipe_S(i1,i2*2+1),
+ data2_in_allowed => data_allowed_S(i1,i2*2+1),
+ data_out => data_S(i1+1,i2),
+ data_out_write => data_write_S(i1+1,i2),
+ data_out_available => data_out_inpipe_S(i1+1,i2),
+ data_out_allowed => data_allowed_S(i1+1,i2),
+ error => error_array_S(i1,i2),
+ testword0 => testword0_S(i1,i2));
+
+ end generate;
+end generate;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ error_S <= '0';
+ for i1 in 0 to mux2to1_gen_max-1 loop
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
+ if error_array_S(i1,i2)='1' then
+ error_S <= '1';
+ end if;
+ end loop;
+ end loop;
+ end if;
+end process;
+error <= error_S;
+
+data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';
+tfifo_in_S <= data_S(mux2to1_gen_max,0);
+tfifo: sync_fifo_FWFT_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => tfifo_in_S,
+ wr_en => data_write_S(mux2to1_gen_max,0),
+ rd_en => tfifo_rd_S,
+ dout => data_out,
+ full => tfifo_full_S,
+ empty => tfifo_empty_S);
+
+
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+
+
+
+
+--testword0(33 downto 0) <= data_in(0)(33 downto 0);
+--testword0(34) <= time_error_S;
+--testword0(35) <= idx_error_S;
+testword1(33 downto 0) <= data_in(1)(33 downto 0);
+testword1(34) <= '0';
+testword1(35) <= '0';
+
+
+
+
+gentest: for i in 0 to 7 generate
+testword0(i) <= dfifo_full_S(i);
+end generate;
+
+testword0(8) <= dfifo_rd_S(7);
+testword0(9) <= data_in_available_S(7);
+
+testword0(10) <= data_write_S(0,7);
+testword0(11) <= data_out_inpipe_S(0,7);
+testword0(12) <= data_allowed_S(0,7);
+
+testword0(13) <= data_write_S(1,3);
+testword0(14) <= data_out_inpipe_S(1,3);
+testword0(15) <= data_allowed_S(1,3);
+
+testword0(16) <= data_write_S(2,1);
+testword0(17) <= data_out_inpipe_S(2,1);
+testword0(18) <= data_allowed_S(2,1);
+
+testword0(19) <= data_write_S(3,0);
+testword0(20) <= data_out_inpipe_S(3,0);
+testword0(21) <= data_allowed_S(3,0);
+
+
+testword0(22) <= data_write_S(0,0);
+testword0(23) <= data_out_inpipe_S(0,0);
+testword0(24) <= data_allowed_S(0,0);
+
+testword0(25) <= data_write_S(1,0);
+testword0(26) <= data_out_inpipe_S(1,0);
+testword0(27) <= data_allowed_S(1,0);
+
+testword0(28) <= data_write_S(2,0);
+testword0(29) <= data_out_inpipe_S(2,0);
+testword0(30) <= data_allowed_S(2,0);
+
+
+testword0(31) <= data_write_S(mux2to1_gen_max,0);
+testword0(32) <= tfifo_full_S;
+testword0(33) <= tfifo_rd_S;
+testword0(34) <= error_S;
+testword0(35) <= '0';
+--
+--
+--
+--testword1 <= testword0_S(2,0);
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd b/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd
new file mode 100644
index 0000000..6fa1ff9
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd
@@ -0,0 +1,347 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_sorting_wavemux
+-- Description: Multiplexer for FEE data, sorting on timestamp
+-- Modifications:
+-- 23-09-2014 single clock, remove fullness fifo,
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_sorting_wavemux
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the 32-bits timestamp.
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+-- NROFMUXINPUTS : number of input-channels
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset, must be long enough for all clocks
+-- data_in : array of input data streams, structure of each:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data_in_write : write signal for data_in (write into fifo)
+-- data_out_read : read signal for outgoing data (read from fifo)
+--
+-- Outputs:
+-- data_in_allowed : write to input data allowed (not full)
+-- data_in_almostfull : input fifo is too full for maximum length waveform
+-- data_out : output data
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identification)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data_out_available : data_out available (output fifo not empty)
+-- data_out_inpipe : more data on its way
+-- error : data error, index in data words incorrect
+--
+-- Components:
+-- FEE_wavemux_readfifo : read data from fifo and writes to next level
+-- FEE_wavemux2to1 : compares the data and passes the first in time on
+-- sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty
+-- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_sorting_wavemux is
+ generic(
+ NROFMUXINPUTS : natural := 16
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+);
+end FEE_sorting_wavemux;
+
+
+architecture Behavioral of FEE_sorting_wavemux is
+
+component FEE_wavemux2to1 is
+ generic(
+ TIMEOUTBITS : natural := 6
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_wavemux_readfifo is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);
+end component;
+
+component sync_fifo_progfull364_progempty128_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_full : out std_logic;
+ prog_empty : out std_logic);
+end component;
+
+component sync_fifo_FWFT_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
+constant INPIPE_DELAY : integer := 63;
+constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+
+--type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;
+--constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);
+
+type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);
+type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;
+
+signal error_S : std_logic := '0';
+
+signal data_S : data_type;
+signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
+signal data_write_S : singlebit_type := (others => (others => '0'));
+signal data_allowed_S : singlebit_type := (others => (others => '0'));
+signal error_array_S : singlebit_type := (others => (others => '0'));
+
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
+signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S : std_logic_vector (35 downto 0);
+signal tfifo_rd_S : std_logic := '0';
+signal tfifo_full_S : std_logic := '0';
+signal tfifo_empty_S : std_logic := '0';
+
+type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);
+signal testword0_S : testword_type;
+
+begin
+
+data_out_inpipe <= '1'
+ when (dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1)) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')
+ else '0';
+
+FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
+
+process(clock)
+type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
+variable inpipe_counter_V : inpipe_counter_type := (others => 0);
+variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ inpipe_counter_V(index) := 0;
+ delay_inpipe_S(index) <= '0';
+ else
+ index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
+ if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
+ ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
+ then
+ inpipe_counter_V(index) := INPIPE_DELAY;
+ delay_inpipe_S(index) <= '1';
+ else
+ if inpipe_counter_V(index)/=0 then
+ inpipe_counter_V(index) := inpipe_counter_V(index)-1;
+ delay_inpipe_S(index) <= '1';
+ else
+ delay_inpipe_S(index) <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+dfifo: sync_fifo_progfull364_progempty128_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => data_in(index),
+ wr_en => dfifo_wr_S(index),
+ rd_en => dfifo_rd_S(index),
+ dout => dfifo_out_S(index),
+ full => dfifo_full_S(index),
+ empty => dfifo_empty_S(index),
+ prog_full => data_in_almostfull(index),
+ prog_empty => dfifo_prog_empty_S(index));
+
+ dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+
+data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';
+
+FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(
+ clock => clock,
+ reset => reset,
+ data_in => dfifo_out_S(index),
+ data_in_available => data_in_available_S(index),
+ data_in_read => dfifo_rd_S(index),
+ data_out => data_S(0,index),
+ data_out_write => data_write_S(0,index),
+ data_out_inpipe => read36_inpipe_S(index),
+ data_out_allowed => data_allowed_S(0,index));
+
+process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
+--variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+-- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
+-- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
+-- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
+ if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
+ (dfifo_wr_S(index)='1') then
+ data_out_inpipe_S(0,index) <= '1';
+ else
+ data_out_inpipe_S(0,index) <= '0';
+ end if;
+end process;
+
+end generate;
+
+
+FEE_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate
+
+ FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+
+ FEE_wavemux2to1_1: FEE_wavemux2to1 port map(
+ clock => clock,
+ reset => reset,
+ data1_in => data_S(i1,i2*2),
+ data1_in_write => data_write_S(i1,i2*2),
+ data1_in_available => data_out_inpipe_S(i1,i2*2),
+ data1_in_allowed => data_allowed_S(i1,i2*2),
+ data2_in => data_S(i1,i2*2+1),
+ data2_in_write => data_write_S(i1,i2*2+1),
+ data2_in_available => data_out_inpipe_S(i1,i2*2+1),
+ data2_in_allowed => data_allowed_S(i1,i2*2+1),
+ data_out => data_S(i1+1,i2),
+ data_out_write => data_write_S(i1+1,i2),
+ data_out_available => data_out_inpipe_S(i1+1,i2),
+ data_out_allowed => data_allowed_S(i1+1,i2),
+ error => error_array_S(i1,i2),
+ testword0 => testword0_S(i1,i2));
+
+ end generate;
+end generate;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ error_S <= '0';
+ for i1 in 0 to mux2to1_gen_max-1 loop
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
+ if error_array_S(i1,i2)='1' then
+ error_S <= '1';
+ end if;
+ end loop;
+ end loop;
+ end if;
+end process;
+error <= error_S;
+
+data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';
+tfifo_in_S <= data_S(mux2to1_gen_max,0);
+tfifo: sync_fifo_FWFT_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => tfifo_in_S,
+ wr_en => data_write_S(mux2to1_gen_max,0),
+ rd_en => tfifo_rd_S,
+ dout => data_out,
+ full => tfifo_full_S,
+ empty => tfifo_empty_S);
+
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+
+
+testword0 <= (others => '0');
+testword1 <= (others => '0');
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd b/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd
new file mode 100644
index 0000000..1c77815
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd
@@ -0,0 +1,225 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-02-2012
+-- Module Name: FEE_waveform_to_36bits
+-- Description: put waveform data in 36-bits wide data stream
+-- Modifications:
+-- 14-08-2014: bug in read signal, output 'overflow_out' added
+-- 16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits
+-- 11-10-2014: adc-channel number 8 bits
+-- 23-10-2014: finish actual waveform in case of almost full signal
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+use work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_waveform_to_36bits
+-- Put waveform data in 36-bits wide data stream
+-- Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.
+-- Output data is 36 bits wide with the four highest bits for identification
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- adcnumber : 8 bits indification of the adc channel
+-- data_in : data from adc waveform buffer:
+-- bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform
+-- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
+-- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
+-- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
+-- bits(35..32)="1111" : error, bits(31..0)=don't care
+-- overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte
+-- pileupdata_allowed : writing of pile-up data allowed
+-- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--
+-- outputs
+-- data_in_read : read signal to adc waveform buffer
+-- pileupdata_out : 36-bits data with pile-up waveform:
+-- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- pileupdata_write : write signal for pile-up data output
+-- overflow_out : buffer overflow: data skipped
+-- error : error in incoming data
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_waveform_to_36bits is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ overflow_in : in std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_write : out std_logic;
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ overflow_out : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_waveform_to_36bits;
+
+architecture Behavioral of FEE_waveform_to_36bits is
+
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal pileupdata_write_S : std_logic := '0';
+signal pileupdata_trywrite_S : std_logic := '0';
+
+signal lastdata_S : std_logic := '0';
+signal lastdata0_S : std_logic := '0';
+signal lastdata1_S : std_logic := '0';
+
+signal writingadcnumber_S : std_logic := '0';
+signal writeadcnumber_S : std_logic := '0';
+signal overflow_occurred_S : std_logic := '0';
+signal clear_overflow_occurred_S : std_logic := '0';
+signal overflow_in_S : std_logic := '0';
+signal error1_S : std_logic := '0';
+signal pileupdata_out_S : std_logic_vector(35 downto 0) := (others => '0');
+
+begin
+
+overflow_out <= overflow_occurred_S;
+error <= error1_S;
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1'
+ when (data_in_available='1') and (writingadcnumber_S='0') and (pileupdata_allowed='1') and
+ ((pileupdata_almostfull='0') or (lastdata_S='0'))--and (prevent_reading_S='0')
+ else '0';
+
+lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 32)="010") else '0';
+lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ lastdata1_S <= '0';
+ else
+ if data_in_read_after1clk_S='1' then
+ lastdata1_S <= lastdata0_S;
+ end if;
+ end if;
+ end if;
+end process;
+
+writingadcnumber_S <= '1' when
+ (writeadcnumber_S='1')
+ or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000"))
+ else '0';
+
+pileupdata_out <= pileupdata_out_S;
+
+pileupdata_write <= pileupdata_write_S;
+pileupdata_write_S <= '1' when (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') else '0';
+
+readprocess: process(clock)
+variable statusbyte_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+ if rising_edge(clock) then
+ error1_S <= '0';
+ clear_overflow_occurred_S <= '0';
+ if reset='1' then
+ pileupdata_trywrite_S <= '0';
+ writeadcnumber_S <= '0';
+ statusbyte_V := (others => '0');
+ overflow_occurred_S <= '0';
+ data_in_read_after1clk_S <= '0';
+ overflow_in_S <= overflow_in;
+ else
+ if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then
+ overflow_occurred_S <= '1';
+ elsif clear_overflow_occurred_S='1' then
+ overflow_occurred_S <= '0';
+ end if;
+ overflow_in_S <= overflow_in;
+ data_in_read_after1clk_S <= data_in_read_S;
+ if data_in_read_after1clk_S='1' then
+ case data_in(35 downto 32) is
+ when "1000" =>
+ pileupdata_out_S <= "0000" & data_in(31 downto 0);
+ pileupdata_trywrite_S <= '1';
+ writeadcnumber_S <= '1';
+ when "0010" => -- samples
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when "0100" => -- last sample
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when "0101" => -- last samples
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when others =>
+ error1_S <= '1';
+ pileupdata_trywrite_S <= '0';
+ end case;
+ else -- not data_in_read_after1clk_S
+ if (writeadcnumber_S='1') and (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') then
+ if overflow_occurred_S='1' then
+ statusbyte_V := STATBYTE_FEEPULSESKIPPED;
+ clear_overflow_occurred_S <= '1';
+ else
+ statusbyte_V := (others => '0');
+ end if;
+ pileupdata_out_S <= "0001" & statusbyte_V & x"0000" & adcnumber;
+ pileupdata_trywrite_S <= '1';
+ writeadcnumber_S <= '0';
+ elsif (pileupdata_trywrite_S='1') and (pileupdata_allowed='0') then -- keep trying
+ pileupdata_trywrite_S <= '1';
+ elsif (writeadcnumber_S='1') then
+ writeadcnumber_S <= '0';
+ else
+ pileupdata_trywrite_S <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+testword0(3 downto 0) <= data_in(35 downto 32);
+testword0(4) <= data_in_read_S;
+testword0(5) <= data_in_available;
+testword0(6) <= data_in_read_after1clk_S;
+testword0(7) <= data_in_read_S;
+testword0(11 downto 8) <= pileupdata_out_S(35 downto 32);
+testword0(12) <= pileupdata_write_S;
+testword0(13) <= pileupdata_trywrite_S;
+testword0(14) <= writingadcnumber_S;
+testword0(15) <= writeadcnumber_S;
+testword0(16) <= overflow_occurred_S;
+testword0(17) <= clear_overflow_occurred_S;
+testword0(18) <= overflow_in_S;
+testword0(19) <= error1_S;
+testword0(20) <= pileupdata_allowed;
+testword0(21) <= pileupdata_almostfull;
+testword0(22) <= writeadcnumber_S;
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd b/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd
new file mode 100644
index 0000000..c1cc47d
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd
@@ -0,0 +1,375 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_wavemux2to1
+-- Description: compare timestamp of 36bits data pass on first
+-- Modifications:
+-- 11-10-2014: adc-channel number 8 bits
+-- 23-10-2014: proper end of packet in case of timeout
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_wavemux2to1
+-- Compare timestamp of 36bits data and pass on first
+-- Timestamp is a combination of the superburst and a clockcounter
+-- If data from only one is available then this is passed on directly
+-- The 36-bits data contains waveforms in packets, starting with timestamp, ending with last sample:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data1_in : data from first 36-bits input
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data1_in_write : write signal for data1_in
+-- data1_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data2_in : data from second 36-bits input
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data2_in_write : write signal for data2_in
+-- data2_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data_out_allowed : writing of resulting data allowed
+--
+-- outputs
+-- data1_in_allowed : signal to allow data input 1
+-- data2_in_allowed : signal to allow data input 2
+-- data_out : 36-bits data with valid pulse waveform:
+-- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data_out_write : write signal for 36-bits output data
+-- data_out_available : data available: in this module or at the input
+-- error : error in data bits 35..32
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_wavemux2to1 is
+ generic(
+ TIMEOUTBITS : natural := 6
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_wavemux2to1;
+
+
+architecture Behavioral of FEE_wavemux2to1 is
+
+signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+
+signal error_S : std_logic := '0';
+signal read_pulse1_S : std_logic := '0';
+signal read_pulse2_S : std_logic := '0';
+signal data1_in_allowed_S : std_logic := '0';
+signal data2_in_allowed_S : std_logic := '0';
+signal data1_in_write_S : std_logic := '0';
+signal data2_in_write_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_available_S : std_logic := '0';
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data1_timestamp_valid_S : std_logic := '0';
+signal data2_timestamp_valid_S : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+data_out_available <= data_out_available_S;
+data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1')
+ or (data_out_trywrite_S='1')
+ or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
+ else '0';
+
+data_out <= data_out_S;
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data1_in_allowed <= data1_in_allowed_S;
+data1_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse1_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
+ else '0';
+
+data2_in_allowed <= data2_in_allowed_S;
+data2_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse2_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+ else '0';
+
+--data2_in_allowed_S <= '1' when (data_out_allowed='1')
+-- and ((read_pulse2_S='1')
+-- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
+-- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+-- else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
+
+readprocess: process(clock)
+variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data1_timestamp_valid_V : std_logic := '0';
+variable data2_timestamp_valid_V : std_logic := '0';
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_trywrite_S <= '0';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data1_timestamp_valid_S <= '0';
+ data2_timestamp_valid_S <= '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+ data_out_trywrite_S <= '1'; -- try again
+ timeout_counter_S <= (others => '0');
+ else
+ if read_pulse1_S='1' then
+ data1_timestamp_valid_V := '0';
+ if data1_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data1_in(35 downto 32)="0001") or (data1_in(35 downto 32)="0010") then -- next data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';
+ elsif (data1_in(35 downto 33)="010") then -- last data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ read_pulse1_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data_out_S <= "0100" & x"00000000"; -- force last data
+ data_out_trywrite_S <= '1';
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if data_out_allowed='1' then
+ if data_out_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ else
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ elsif read_pulse2_S='1' then
+ data2_timestamp_valid_V := '0';
+ if data2_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data2_in(35 downto 32)="0001") or (data2_in(35 downto 32)="0010") then -- next data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';
+ elsif (data2_in(35 downto 33)="010") then -- last data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ read_pulse2_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data_out_S <= "0100" & x"00000000"; -- force last data
+ data_out_trywrite_S <= '1';
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if data_out_allowed='1' then
+ if data_out_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ else
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ else
+ timeout_counter_S <= (others => '0');
+ if data1_in_write_S='1' then
+ if (data1_in(35 downto 32)="0000") then
+ data1_timestamp_V := data1_in(31 downto 0);
+ data1_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data2_in_write_S='1' then
+ if (data2_in(35 downto 32)="0000") then
+ data2_timestamp_V := data2_in(31 downto 0);
+ data2_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data1_timestamp_valid_V='1' then
+ if data2_timestamp_valid_V='1' then
+ if (data1_timestamp_V(31 downto 0) '0');
+
+testword0(0) <= data1_in_write;
+testword0(1) <= data1_in_available;
+testword0(2) <= data1_in_allowed_S;
+testword0(3) <= read_pulse1_S;
+testword0(4) <= data1_in_write_S;
+testword0(5) <= data1_timestamp_valid_S;
+testword0(9 downto 6) <= data1_in(35 downto 32);
+
+testword0(10) <= data2_in_write;
+testword0(11) <= data2_in_available;
+testword0(12) <= data2_in_allowed_S;
+testword0(13) <= read_pulse2_S;
+testword0(14) <= data2_in_write_S;
+testword0(15) <= data2_timestamp_valid_S;
+testword0(19 downto 16) <= data2_in(35 downto 32);
+
+
+testword0(20) <= data_out_trywrite_S;
+testword0(21) <= data_out_write_S;
+testword0(22) <= data_out_available_S;
+testword0(23) <= data_out_allowed;
+testword0(27 downto 24) <= data_out_S(35 downto 32);
+testword0(28) <= error_S;
+
+
+
+testword0(33 downto 29) <= timeout_counter_S(TIMEOUTBITS-1 downto TIMEOUTBITS-5);
+testword0(35 downto 34) <= (others => '0');
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd b/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd
new file mode 100644
index 0000000..7066dff
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd
@@ -0,0 +1,118 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_wavemux_readfifo
+-- Description: Read 36-bits data from fifo and write to next module
+-- Modifications:
+-- 16-10-2014: inpipe signal
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_wavemux_readfifo
+-- Read 36-bits data from fifo and write to next module.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : 36-bits input data from fifo
+-- data_in_available : input fifo not empty
+-- data_out_allowed : allowed to write output data data
+--
+-- Outputs:
+-- data_in_read : read signal to input fifo
+-- data_out : 36-bits output data
+-- data_out_write : write signal for output data
+-- data_out_inpipe : data available, in this module or in input fifo
+--
+-- Components:
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_wavemux_readfifo is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);
+end FEE_wavemux_readfifo;
+
+
+architecture Behavioral of FEE_wavemux_readfifo is
+
+signal data_in_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_write_S : std_logic := '0';
+signal data_in_saved_S : std_logic := '0';
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+
+
+begin
+
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data_out <= data_out_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ data_in_read_after1clk_S <= '0';
+ data_out_trywrite_S <= '0';
+ data_in_saved_S <= '0';
+ else
+ if (data_out_write_S='0') and (data_out_trywrite_S='1') then -- unsuccesfull try again
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ end if;
+ elsif data_in_saved_S='1' then -- write saved data
+ data_out_S <= data_in_S;
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then -- save next data
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ else
+ data_in_saved_S <= '0';
+ end if;
+ elsif data_in_read_after1clk_S='1' then -- next read
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ else
+ data_out_trywrite_S <= '0';
+ end if;
+ data_in_read_after1clk_S <= data_in_read_S;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/Panda_package.vhd b/FEE_ADC32board/FEE_modules/Panda_package.vhd
new file mode 100644
index 0000000..0de958a
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/Panda_package.vhd
@@ -0,0 +1,424 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 04-03-2011
+-- Module Name: panda_package
+-- Description: Package with constants and function for Panda
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+package panda_package is
+
+ constant NROFADCS : natural := 32;
+ constant NROFFIBERS : natural := 4;
+ constant ADCINDEXSHIFT : natural := 1;
+ constant NROFMUXREGS : natural := 14;
+ constant ADCBITS : natural := 14;
+ constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;
+ constant FEESLOWCONTROLADRESSES : natural := 2*NROFADCS/(ADCINDEXSHIFT+1)+4;
+ constant FEESLOWCONTROLBOARDADDRESS : natural := 2*NROFADCS/(ADCINDEXSHIFT+1);
+
+-- statusbyte in data stream :
+ constant STATBYTE_DCPULSESKIPPED : std_logic_vector(7 downto 0) := "00000100";
+ constant STATBYTE_DCWAVESKIPPED : std_logic_vector(7 downto 0) := "00000100";
+ constant STATBYTE_DCCOMBINEDHITS : std_logic_vector(7 downto 0) := "00000001";
+ constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";
+ constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";
+
+ constant STATBYTE_FEEPULSESKIPPED : std_logic_vector(7 downto 0) := "01000000";
+ constant STATBYTE_FEECFNOZEROCROSS : std_logic_vector(7 downto 0) := "00100000";
+ constant STATBYTE_FEECFERROR : std_logic_vector(7 downto 0) := "00010000";
+
+-- fiber constants
+constant KCHAR280 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
+constant KCHAR281 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
+constant KCHAR285 : std_logic_vector(7 downto 0) := "10111100"; -- BC
+-- constant KCHAR277 : std_logic_vector(7 downto 0) := "11111011"; -- FB
+constant KCHAR286 : std_logic_vector(7 downto 0) := x"DC";
+
+constant KCHARIDLE : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285; -- 3CBC peter: bytes different for word sync
+constant KCHARSODASTART : std_logic_vector(15 downto 0) := KCHAR280 & KCHAR280; -- 1C1C
+constant KCHARSODASTOP : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR281; -- 3C3C
+constant KCHARSODA : std_logic_vector(7 downto 0) := KCHAR286; -- DC
+
+-- addresses slowcontrol commands for Multiplexer board
+ constant ADDRESS_MUX_FIBERMODULE_STATUS : std_logic_vector(23 downto 0) := x"800000";
+-- request : request status
+-- command: clear error bits, pulse skipped counter
+-- Reply, or in case of error: Status of the fibermodule:
+-- bit0 : error in slowcontrol to cpu occured
+-- bit1 : error if slowcontrol transmit data
+-- bit2 : error if fiber receive data
+-- bit3 : received character not in table: fiber error
+-- bit4 : pulse data skipped due to full multiplexer fifo
+-- bit5 : receiver locked
+-- bit15..8 : number of pulse data packets skipped due to full buffers
+-- bit31..16 : number of successful hamming code corrections
+ constant ADDRESS_MUX_MAXCFLUTS : std_logic_vector(23 downto 0) := x"800001";
+-- bit15..0 : data for the CF or MAX Look Up Table
+-- bit25..16 :offset for maximum correction LUT
+-- bit26 : write signal for maximum LUT
+-- bit27 : loading maximum correction LUT
+-- bit28 : enable maximum correction
+-- bit29 : write signal for Constant Fraction LUT
+-- bit30 : loading CF correction LUT
+-- bit31 : enable CF correction
+ constant ADDRESS_MUX_MULTIPLEXER_STATUS : std_logic_vector(23 downto 0) := x"800002";
+-- status/fullness of the multiplexer:
+-- bit 15..0 : number of words in input fifo of the multiplexer
+-- bit 15..0 : number of words in output fifo of the multiplexer, only for fiber index 0
+ constant ADDRESS_MUX_SODA_CONTROL : std_logic_vector(23 downto 0) := x"800003";
+-- settings for the SODA :
+-- bit0 : enable SODA packets
+-- bit1 : reset timestamp counters
+-- bit2 : Enable data taking
+-- bit3 : Disable data taking
+-- bit4 : Enable Aurora interface to Computer Node
+ constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004";
+-- settings for the histogram :
+-- bit0 : clear the histogram
+-- bit1 : start reading of the histogram
+-- bit10..8 : Binning of the histogram channels, scaling x-axis :
+-- 000 = no scaling
+-- 001 = div 2
+-- 010 = div 4
+-- 011 = div 8
+-- 100 = div 16
+-- 101 = div 32
+-- 110 = div 64
+-- 111 = div 128
+-- bit31..16 : Selected unique adc-number
+ constant ADDRESS_MUX_TIMESTAMP_ERRORS : std_logic_vector(23 downto 0) := x"800005";
+-- number of errors:
+-- bit 9..0 : number of timestamp mismatches
+-- bit 19..10 : number of skipped pulses
+-- bit 29..20 : number of data errors
+ constant ADDRESS_MUX_TIMESHIFT : std_logic_vector(23 downto 0) := x"800006";
+-- number of clockcycles (incl. constant fraction) to compensate for delay SODA to FEE
+-- bit 10..0 : compensation time, fractional part; number of bits for constant fraction, see CF_FRACTIONBIT
+-- bit 30..16 : compensation time, integer part
+-- bit 31 : load LUT mode, after set to 1 starts with ADC0 on each write, and so on
+ constant ADDRESS_MUX_EXTRACTWAVE : std_logic_vector(23 downto 0) := x"800007";
+-- start extracting waveform of 1 pileup pulse:
+-- bit 15..0 : selected adcnumber
+-- bit 16 : select 1 adc, otherwise take first data arriving
+-- bit 17 : select 1 low/high combination instead of 1 adc channel
+ constant ADDRESS_MUX_EXTRACTDATA : std_logic_vector(23 downto 0) := x"800008";
+-- start extracting data of 1 pulse:
+-- bit 15..0 : selected adcnumber
+-- bit 16 : select 1 adc, otherwise take first data arriving
+-- bit 17 : select 1 low/high combination instead of 1 adc channel
+ constant ADDRESS_MUX_SYSMON : std_logic_vector(23 downto 0) := x"80000c";
+-- write to FPGA system monitor
+-- bit 31 : slect read/write, write='0', read='1'
+-- bit 30 : reset/reconfigure FPGA system monitor
+-- bit 22..16 : 7-bits address of FPGA system monitor
+-- bit 15..0 : 16-bits data for FPGA system monitor
+-- read from FPGA system monitor, effective address is the last address at data bits 30..16 that was written
+-- bit 30..16 : 7-bits effective address of FPGA system monitor
+-- bit 15..0 : data from FPGA system monitor
+ constant ADDRESS_MUX_CROSSSWITCH : std_logic_vector(23 downto 0) := x"80000d";
+-- write to cross switch configuration
+-- bit 7..0 : selected multiplexer input
+-- bit 15..8 : ADC-channel to switch to selected multiplexer input (fibernr*NROFADCS+adcnumber or fibernr*NROFADCS/2+adcnumber/2 if high/low gain ADCs are used)
+-- bit 16 : select if selected multiplexer input will be combined with neighbour (only for even inputs)
+-- bit 31 : write to configuration register (extra check)
+ constant ADDRESS_MUX_ENERGYCORRECTION : std_logic_vector(23 downto 0) := x"80000e";
+-- energy correction Look Up Table
+-- bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)
+-- bit 30..16 : offset for energy
+-- bit 31 : loading LUT mode, after set to 1 starts with ADC0 on each write, and so on
+
+-- addresses slowcontrol commands for Multiplexer
+ constant ADDRESS_BOARDNUMBER : std_logic_vector(23 downto 0) := x"002000";
+-- bit11..0 = sets the unique boardnumber
+-- bit31 = initialize all FEE registers that have been set
+
+-- addresses slowcontrol commands for Front End Electronics board
+ constant ADDRESS_FEE_CONTROL : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS,8);
+-- bit0: reset all
+-- bit2: clear errors
+-- bit3: enable waveforms
+-- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
+-- bit 18 = reset/initializes FPGA System monitor
+ constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1,8);
+-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
+-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
+-- bit 15..6 = ADC value from FPGA System monitor
+-- bit23..16 : error occurred bits: in case of error a bit is set. Clearing is done with ADDRESS_FEE_CONTROL
+-- bit16 : error : NotInTable
+-- bit17 : error : receive data error (slowcontrol)
+-- bit18 : error : slowcontrol buffer overrun
+-- bit19 : error : not used
+-- bit20 : error : transmit data error, multipleser error
+-- bit21 : error : receive data buffer overrun
+-- bit22 : error : adc data buffer overrun
+-- bit23 : error : receive fiber not locked
+ constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2,8);
+-- data not important; this slowcontrol command indicates buffer full
+ constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3,8);
+-- bit31..0 : number of hits in one second
+ constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4,8);
+
+ type array_muxregister_type is array(0 to NROFMUXREGS-1) of std_logic_vector(31 downto 0);
+
+ type array_adc_type is array(0 to NROFADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
+ type array_adc64bits_type is array(0 to NROFADCS-1) of std_logic_vector(63 downto 0);
+ type array_adc48bits_type is array(0 to NROFADCS-1) of std_logic_vector(47 downto 0);
+ type array_adc36bits_type is array(0 to NROFADCS-1) of std_logic_vector(35 downto 0);
+ type array_adc32bits_type is array(0 to NROFADCS-1) of std_logic_vector(31 downto 0);
+ type array_adc24bits_type is array(0 to NROFADCS-1) of std_logic_vector(23 downto 0);
+ type array_adc16bits_type is array(0 to NROFADCS-1) of std_logic_vector(15 downto 0);
+ type array_adc9bits_type is array(0 to NROFADCS-1) of std_logic_vector(8 downto 0);
+ type array_adc8bits_type is array(0 to NROFADCS-1) of std_logic_vector(7 downto 0);
+ type array_adc4bits_type is array(0 to NROFADCS-1) of std_logic_vector(3 downto 0);
+
+ type array_halfadc36bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(35 downto 0);
+ type array_halfadc32bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(31 downto 0);
+ type array_halfadc16bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
+ type array_halfadc9bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(8 downto 0);
+ type array_halfadc8bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
+
+ type array_fiber64bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(63 downto 0);
+ type array_fiber48bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(47 downto 0);
+ type array_fiber36bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(35 downto 0);
+ type array_fiber32bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(31 downto 0);
+ type array_fiber31bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(30 downto 0);
+ type array_fiber24bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(23 downto 0);
+ type array_fiber16bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(15 downto 0);
+ type array_fiber12bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(11 downto 0);
+ type array_fiber10bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(9 downto 0);
+ type array_fiber9bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(8 downto 0);
+ type array_fiber8bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(7 downto 0);
+ type array_fiber4bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(3 downto 0);
+
+ type array_DCadc36bits_type is array(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);
+ type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);
+ type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);
+ type twologarray_type is array(0 to 128) of natural;
+ constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);
+ type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);
+
+----------------------------------------------------------------------------------
+-- add_hamming_code_26_32
+-- Fills in Hamming code bits on positions 0,1,3,7,15,31 of a 32-bits word.
+-- The Hamming code is calculated with additional parity to be able to detect
+-- an error in 2 bits.
+--
+-- Inputs:
+-- data_in : 32 bits data input, with 26 bits real data, the others will be filled with Hamming code
+--
+-- Return:
+-- 32 bits data output, 26 bits original data and bits 0,1,3,7,15,31 filled with Hamming code
+--
+----------------------------------------------------------------------------------
+ function add_hamming_code_26_32 (data_in : in std_logic_vector) return std_logic_vector;
+
+
+----------------------------------------------------------------------------------
+-- calc_next_channel
+-- Calculates the next index in a std_logic_vector that has value '0';
+-- Used to determine the next ADC-channel to select in a multiplexer.
+-- If all values are '1' then the same index is returned.
+--
+-- Inputs:
+-- adcreading : starting index in the std_logic_vector
+-- dfifo_empty : std_logic_vector to select the next index with value '0'
+--
+-- Return:
+-- Next index in std_logic_vector with '0'
+--
+----------------------------------------------------------------------------------
+ function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer;
+
+
+----------------------------------------------------------------------------------
+-- calc_next_channel
+-- Calculates the next index in a std_logic_vector that has value '1';
+-- Used to determine the next ADC-channel to select in a multiplexer.
+-- If all values are '0' then the same index is returned.
+--
+-- Inputs:
+-- adcreading : starting index in the std_logic_vector
+-- data_available : std_logic_vector to select the next index with value '1'
+--
+-- Return:
+-- Next index in std_logic_vector with '1'
+--
+----------------------------------------------------------------------------------
+ function calc_next_channel_set(adcreading : integer; data_available : std_logic_vector) return integer;
+
+
+----------------------------------------------------------------------------------
+-- std_logic_vector_valid
+-- Checks if all bits in std_logic_vector are valid (0 or 1) to suppress conv_integer warnings during simulation
+--
+-- Inputs:
+-- data : std_logic_vector to check
+--
+-- Return:
+-- true if the std_logic_vector data is valid (only '0' and '1')
+--
+----------------------------------------------------------------------------------
+ function std_logic_vector_valid(data : in std_logic_vector) return boolean;
+
+
+end panda_package;
+
+
+package body panda_package is
+
+function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer is
+variable i : integer range 0 to dfifo_empty'high+1;
+variable c : integer range 0 to dfifo_empty'high;
+begin
+ i := 0;
+ if adcreading=dfifo_empty'high then
+ c := 0;
+ else
+ c := adcreading+1;
+ end if;
+ while (i/=dfifo_empty'high+1) and (dfifo_empty(c)='1') loop
+ i := i+1;
+ if (c (others => '0'));
+
+begin
+
+ process (clock)
+ begin
+ if (clock'event and clock = '1') then
+ if (write_enable = '1') then
+ mem_S(conv_integer(write_address)) <= data_in;
+ end if;
+ data_out <= mem_S(conv_integer(read_address));
+ end if;
+ end process;
+
+
+end architecture behavioral;
\ No newline at end of file
diff --git a/FEE_ADC32board/FEE_modules/crc8_add_check32.vhd b/FEE_ADC32board/FEE_modules/crc8_add_check32.vhd
new file mode 100644
index 0000000..9784525
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/crc8_add_check32.vhd
@@ -0,0 +1,140 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-02-2011
+-- Module Name: crc8_add_check32
+-- Description: Add and checks a CRC8 code to a stream of 32 bits data words
+----------------------------------------------------------------------------------
+
+LIBRARY IEEE ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- crc8_add_check32
+-- Checks and adds a CRC8 code to a stream of 32 bits data words.
+-- This module can be used to add a CRC8 code and/or checks the CRC8 code.
+--
+-- The last byte (that is LSB of the 32-bits word) filled with the CRC8 code,
+-- overwriting the original data, and this original data is compared with the
+-- CRC8 code. If they are not the same the crc_error output bit is high.
+-- The CRC8 is calculated on all 32-bits data words, with the LSB of the last word
+-- set to "00000000";
+-- The CRC8 code is calculated with initialize code "00000000".
+-- An explanation can be found at www.ElectronicDesignworks.com
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : one clock is used
+-- reset : synchronous reset
+-- data_in : 32 bits data input, LSB last byte is CRC8 or becomes CRC8
+-- data_in_valid : data_in word is valid
+-- data_in_last : last data in the 32-bits stream; contains or will contain CRC8
+--
+-- Outputs:
+-- data_out : 32 bits data output, LSB last byte is CRC8
+-- data_out_valid : data_in word is valid
+-- data_out_last : last data in the 32-bits stream; contains CRC8
+-- crc_error : CRC8 code in original data_in was wrong,
+-- can be ignored if the module is used to add a CRC8
+--
+----------------------------------------------------------------------------------
+entity crc8_add_check32 is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;
+ crc_error : out std_logic
+ );
+end crc8_add_check32;
+
+architecture behaviour OF crc8_add_check32 IS
+ constant CRC_INIT : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal crc_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal crc_aftr1clk_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal crc_feedback_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal start_on_next_S : std_logic := '0';
+ signal din_S : std_logic_vector(31 DOWNTO 0);
+
+begin
+
+crc_feedback_S <= CRC_INIT when ((start_on_next_S='1') and (data_in_valid='1')) else crc_aftr1clk_S;
+
+din_S(31 downto 8) <= data_in(31 downto 8);
+din_S(7 downto 0) <= data_in(7 downto 0) when data_in_last='0' else (others => '0');
+crc_S(0) <= din_S(0) XOR din_S(1) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR
+ crc_feedback_S(3) XOR din_S(10) XOR din_S(19) XOR din_S(28) XOR crc_feedback_S(4);
+crc_S(1) <= din_S(0) XOR din_S(2) XOR din_S(11) XOR din_S(20) XOR din_S(29) XOR crc_feedback_S(5)
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(2) <= din_S(0) XOR din_S(3) XOR din_S(12) XOR din_S(21) XOR din_S(30) XOR crc_feedback_S(6)
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(3) <= din_S(0) XOR din_S(4) XOR din_S(13) XOR din_S(22) XOR din_S(31) XOR crc_feedback_S(7)
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(4) <= din_S(0) XOR din_S(5) XOR din_S(14) XOR din_S(23) XOR din_S(9) XOR din_S(18) XOR din_S(27)
+ XOR crc_feedback_S(3);
+crc_S(5) <= din_S(0) XOR din_S(6) XOR din_S(15) XOR din_S(24) XOR crc_feedback_S(0) XOR din_S(9)
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(6) <= din_S(0) XOR din_S(7) XOR din_S(16) XOR din_S(25) XOR crc_feedback_S(1) XOR din_S(9)
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(7) <= din_S(0) XOR din_S(8) XOR din_S(17) XOR din_S(26) XOR crc_feedback_S(2) XOR din_S(9)
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+
+crc_process : process(clock, reset)
+begin
+ if (rising_edge(clock)) then
+ if (reset = '1') then
+ crc_error <= '0';
+ start_on_next_S <= '1';
+ data_out_valid <= '0';
+ data_out_last <= '0';
+ crc_aftr1clk_S <= "00000000" ;
+ else
+ if (data_in_valid = '1') then
+ crc_aftr1clk_S <= crc_S;
+ data_out_valid <= '1';
+ if (data_in_last = '1') then
+ start_on_next_S <= '1';
+ data_out_last <= '1';
+ data_out(31 downto 8) <= data_in(31 downto 8);
+ data_out(7 downto 0) <= crc_S;
+ if crc_S/=data_in(7 downto 0) then
+ crc_error <= '1';
+ else
+ crc_error <= '0';
+ end if;
+ else
+ data_out(31 downto 0) <= data_in(31 downto 0);
+ start_on_next_S <= '0';
+ crc_error <= '0';
+ data_out_last <= '0';
+ end if;
+ else
+ crc_error <= '0';
+ data_out_valid <= '0';
+ data_out_last <= '0';
+ end if;
+ end if;
+ end if;
+end process crc_process;
+
+
+end behaviour;
+
+
+
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/cond_add.vhd b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/cond_add.vhd
new file mode 100644
index 0000000..9b33ef6
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/cond_add.vhd
@@ -0,0 +1,37 @@
+----------------------------------------
+-- Conditional adder
+-- op_a + op_b or only op_a depending on sel
+--
+----------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity cond_adder is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end cond_adder;
+
+architecture simple_arch of cond_adder is
+
+begin
+ anAdder: process (sel,op_a,op_b)
+ begin
+ if sel = '1' then
+ outp <= op_a + op_b;
+ else
+ outp <= op_a;
+ end if;
+ end process;
+end simple_arch;
+
diff --git a/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/div_r4_pipe.vhd b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/div_r4_pipe.vhd
new file mode 100644
index 0000000..629e4ac
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/div_r4_pipe.vhd
@@ -0,0 +1,149 @@
+-----------------------------------------------------------------------
+---- Pipelined radix 4 Divisor based on Arch2 (half arch)
+---- A, and B naturals (non negative integers) with XBITS and YBITS width
+---- there is no restriction XBITS >= YBITS.
+---- Return quotient Q of XBITS and remainder R of NBITS
+---- GRAIN defines the amount of bits computed at each cycle.
+----
+---- The circuit captures operands at each cycle
+---- The algorithm needs XBITS/GRAIN/DEPTH + 1 cylcles to calculate the quotient
+---- and remainder (Latency). Its posible to obtain the result one cycle before.
+---- GRAIN = 2 for that radix 4 divider
+---- DEPTH (logic depth) every how many basic cell we register.
+---- DEPTH = 1 maximun pipeline
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity div_r4_pipe is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32;
+ GRAIN : natural := 2;
+ DEPTH : natural := 8
+ );
+ port (
+ A: in STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ B: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ clk: in STD_LOGIC;
+ Q: out STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ R: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end div_r4_pipe;
+
+architecture simple_arch of div_r4_pipe is
+
+ component cond_adder is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+ end component;
+
+ component nr_r4_half_cell is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+ end component;
+
+
+ type connectionmatrix is array (0 to GRAIN) of STD_LOGIC_VECTOR (YBITS downto 0);
+ Signal iR, reg_Y_rem: STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ Signal iQ: STD_LOGIC_VECTOR (XBITS-1 downto 0);
+
+ type matrix_rem is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal rem_in, rem_out: matrix_rem := (others => (others => '0'));
+ type matrix_Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal reg_Y: matrix_Y := (others => (others => '0'));
+ type matrix_3Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal reg_3Y: matrix_3Y := (others => (others => '0'));
+ type matrix_X is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_X: matrix_X := (others => (others => '0'));
+ type matrix_Q is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_Q: matrix_Q := (others => (others => '0'));
+
+signal rem_no_adj: STD_LOGIC_VECTOR (YBITS downto 0);
+
+--attribute keep_hierarchy: string;
+--attribute keep_hierarchy of low_level_arch: architecture is "yes";
+--attribute IOB: string;
+--attribute IOB of low_level_arch: architecture is "FALSE";
+
+begin
+
+ FF_0: process (clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ reg_Y(0) <= ('0' & B);
+ reg_3Y(0) <= ('0' & B) + ('0' & B & '0');
+ reg_X(0) <= A;
+ --Q <= not reg_Q(XBITS/GRAIN-1); --ito obtain the result a cycle before
+ Q <= iQ; iQ <= not reg_Q(XBITS/GRAIN-1);
+ rem_no_adj <= rem_out(XBITS/GRAIN-1);
+ reg_Y_rem <= reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0);
+ R <= iR;
+ end if;
+ end process;
+
+
+ rem_in(0) <= (others => '0');
+
+ g1: for i in 0 to XBITS/GRAIN -1 generate
+ cell: nr_r4_half_cell port map( op_r => rem_in(i),
+ op_y => reg_Y(i), op_3y => reg_3Y(i),
+ x_1 => reg_X(i)(XBITS-1-i*2), x_0 => reg_X(i)(XBITS-2-i*2),
+ n_qneg => reg_Q(i)(XBITS-1-i*2 downto XBITS-2-i*2), new_r => rem_out(i) );
+ end generate;
+
+ g2: for i in 0 to XBITS/GRAIN-2 generate
+ g2c: if (i+1) mod DEPTH /= 0 generate
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end generate;
+ g2FF: if (i+1) mod DEPTH = 0 generate
+ FFs: process(clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end if;
+ end process;
+ end generate;
+ end generate;
+
+
+-- use this code to obtain the remainder a cycle before
+-- final_rem_Adjust: cond_adder port map (op_a => rem_out(XBITS/GRAIN-1)(YBITS-1 downto 0),
+-- op_b => reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0),
+-- sel => rem_out(XBITS/GRAIN-1)(YBITS), outp => iR);
+
+
+ final_rem_Adjust: cond_adder port map (op_a => rem_no_adj(YBITS-1 downto 0),
+ op_b => reg_Y_rem(YBITS-1 downto 0),
+ sel => rem_no_adj(YBITS), outp => iR);
+
+
+end simple_arch;
diff --git a/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/implement_32by32.pdf b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/implement_32by32.pdf
new file mode 100644
index 0000000..9c418f2
Binary files /dev/null and b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/implement_32by32.pdf differ
diff --git a/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/mypack.vhd b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/mypack.vhd
new file mode 100644
index 0000000..8d69abd
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/mypack.vhd
@@ -0,0 +1,10 @@
+-------------------------------------
+-- Defines the dataPath width
+--
+-------------------------------------
+package mypackage is
+ constant XBITS :INTEGER := 32;
+ constant YBITS :INTEGER := 32;
+ constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+ constant DEPTH :INTEGER := 1; --Every how much steps register
+end mypackage;
diff --git a/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/nr_r4_cel.vhd b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/nr_r4_cel.vhd
new file mode 100644
index 0000000..f2fdf98
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/div_pipe_r4_arch2/nr_r4_cel.vhd
@@ -0,0 +1,61 @@
+--------------------------------------------------------
+--
+-- Basic cell radix 4 arch 2. divider
+--------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+use work.mypackage.all;
+
+entity nr_r4_half_cell is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ --generic(pos_x: integer:= 0; pos_y: integer := 0; agroup: string:= "cell_r4");
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+end nr_r4_half_cell;
+
+architecture half of nr_r4_half_cell is
+ signal op_4r: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal a2_pm_b, a4_pm_b, a4_pm_3b: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal sr: STD_LOGIC;
+begin
+ sr <= op_r(YBITS);
+ op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0;
+
+ a2_pm_b <= (op_r & x_1) + (op_y) when sr = '1' else (sr & op_y) + not (op_r & x_1);
+ a4_pm_3b <= (op_4r + op_3y) when sr = '1' else (op_4r) - (op_3y);
+ a4_pm_b <= (op_4r + op_y) when sr = '1' else (op_4r) - (sr & op_y);
+
+ mux_outps: process (a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if a2_pm_b(YBITS)= '1' then
+ new_r <= a4_pm_3b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_3b(YBITS);
+ else
+ new_r <= a4_pm_b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_b(YBITS);
+ end if;
+ end process;
+
+ mux_nqb: process (sr,a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if sr = '1' then --11
+ n_qneg(1) <= a2_pm_b(YBITS);
+ else
+ n_qneg(1) <= not a2_pm_b(YBITS);
+ end if;
+
+ end process;
+
+end half;
diff --git a/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd b/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd
new file mode 100644
index 0000000..1ebc47c
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd
@@ -0,0 +1,90 @@
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 20-04-2008
+-- Module Name: iirfilter_1order_selectBW
+-- Description: First order Infinite respons filter
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- iirfilter_1order_selectBW
+-- First order Infinite Impulse Response filter with inhibit
+-- Description can be found at http://www.beis.de/Elektronik/Filter/AnaDigFilt/AnaDigFilt.html
+--
+-- generics
+-- ADCBITS : number of ADC bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : ADC sampling data
+-- BWidx : factor for BW; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- inhibit : freezes filter
+--
+-- outputs
+-- data_out : filtered output, rounded. Same number of bits as input
+--
+------------------------------------------------------------------------------------------------------
+
+
+entity iirfilter_1order_selectBW is
+ generic (
+ ADCBITS : natural := 16;
+ BWBITS : natural := 10
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector ((ADCBITS-1) downto 0);
+ BWidx : in std_logic_vector (2 downto 0);
+ inhibit : in std_logic;
+ data_out : out std_logic_vector ((ADCBITS-1) downto 0));
+end iirfilter_1order_selectBW;
+
+architecture Behavioral of iirfilter_1order_selectBW is
+signal data_x_BW : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_out_multiplied : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal BWidx_i : integer range 0 to 7 := 0;
+
+begin
+
+process(clock)
+variable data_out_unscaled : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
+ data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
+ data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
+ data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ data_x_BW <= (others => '0');
+ data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ data_out <= data_in;
+ else
+ if inhibit='0' then
+ data_out_unscaled := data_x_BW + data_out_unscaled_delayed-data_out_multiplied;
+
+ data_out_multiplied <= (others => '0');
+ data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
+
+ data_x_BW <= (others => '0');
+ data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+
+ data_out_unscaled_delayed <= data_out_unscaled;
+ data_out <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
+ end if;
+ end if;
+ end if;
+end process;
+
+BWidx_i <= conv_integer(unsigned(BWidx));
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/posedge_to_pulse.vhd b/FEE_ADC32board/FEE_modules/posedge_to_pulse.vhd
new file mode 100644
index 0000000..ee1437f
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/posedge_to_pulse.vhd
@@ -0,0 +1,72 @@
+-----------------------------------------------------------------------------------
+-- posedge_to_pulse
+-- Makes pulse with duration 1 clock-cycle from positive edge
+--
+-- inputs
+-- clock_in : clock input for input signal
+-- clock_out : clock input to synchronize to
+-- en_clk : clock enable
+-- signal_in : rising edge of this signal will result in pulse
+--
+-- output
+-- pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end posedge_to_pulse;
+
+architecture behavioral of posedge_to_pulse is
+
+ signal resetff : std_logic := '0';
+ signal last_signal_in : std_logic := '0';
+ signal qff : std_logic := '0';
+ signal qff1 : std_logic := '0';
+ signal qff2 : std_logic := '0';
+ signal qff3 : std_logic := '0';
+begin
+
+process (clock_in)
+begin
+ if rising_edge(clock_in) then
+ if resetff='1' then
+ qff <= '0';
+ elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then
+ qff <= '1';
+ else
+ qff <= qff;
+ end if;
+ last_signal_in <= signal_in;
+ end if;
+end process;
+resetff <= qff2;
+
+process (clock_out)
+begin
+ if rising_edge(clock_out) then
+ if qff3='0' and qff2='1' then
+ pulse <= '1';
+ else
+ pulse <= '0';
+ end if;
+ qff3 <= qff2;
+ qff2 <= qff1;
+ qff1 <= qff;
+ end if;
+end process;
+
+
+end behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/shift_register.vhd b/FEE_ADC32board/FEE_modules/shift_register.vhd
new file mode 100644
index 0000000..8b99229
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/shift_register.vhd
@@ -0,0 +1,88 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-02-2009
+-- Module Name: shift_register
+-- Description: Shifts data for an adjustable number of clock cycles
+----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- shift_register
+-- Shifts data for an adjustable number of clock cycles
+--
+-- generics
+-- width : number of bits for the data to shift
+-- depthbits : number of bits for the number of clock cycles to shift
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- hold : hold all values
+-- data_in : data to shift
+-- depth : number of clock cycles to shift for
+--
+-- outputs
+-- data_out : shifted data
+--
+------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity shift_register is
+ generic (
+ width : natural := 16;
+ depthbits : natural := 9
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ hold : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end shift_register;
+
+architecture behavior of shift_register is
+
+type arrtype is array((2**depthbits-1) downto 0) of std_logic_vector((width-1) downto 0);
+signal mem : arrtype; -- := (others => (others => '0'));
+signal outptr : std_logic_vector((depthbits-1) downto 0) := (others => '0');
+signal mem_out : std_logic_vector((width-1) downto 0) := (others => '0');
+signal lastreset : std_logic := '0';
+
+attribute syn_ramstyle : string;
+attribute syn_ramstyle of mem : signal is "block_ram";
+
+begin
+
+data_out <= mem_out;
+process (clock)
+begin
+ if rising_edge(clock) then
+ if hold='0' then
+ mem(conv_integer(unsigned(outptr + depth))) <= data_in;
+ if reset = '1' then
+ mem_out <= (others => '0');
+ if lastreset='0' then
+ outptr <= (others => '0');
+ else
+ outptr <= outptr+1;
+ end if;
+ else
+ mem_out <= mem(conv_integer(unsigned(outptr)));
+ outptr <= outptr+1;
+ end if;
+ lastreset <= reset;
+ end if;
+ end if;
+end process;
+
+end behavior;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd
new file mode 100644
index 0000000..1a22311
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd
@@ -0,0 +1,523 @@
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2007 - 2009, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version:
+-- \ \ Filename: AdcClock.vhd
+-- / / Date Last Modified: 16 Jun 09
+-- /___/ /\ Date Created: 08/06/06
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: Marc Defossez
+-- Entity Name: AdcClock
+-- Purpose: High-speed local clock control for an interface between a FPGA and a
+-- Texas Instruments ADC.
+-- Tools: ISE - XST
+-- Limitations: none
+--
+-- Revision History:
+-- Rev.
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_arith.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+entity AdcClock is
+ generic (
+ C_BufioLoc : string := "BUFIODQS_X0Y12";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_AdcBits : integer := 16;
+ C_StatTaps : integer := 16
+ );
+ port (
+ BitClk : in std_logic;
+ BitClkRst : in std_logic;
+ BitClkEna : in std_logic;
+ BitClkReSync : in std_logic;
+ BitClkDivReset : in std_logic;
+ BitClk_MonClkOut : out std_logic; -- CLK output
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input
+ BitClkAlignWarn : out std_logic;
+ BitClkInvrtd : out std_logic;
+ BitClkDone : out std_logic
+ );
+end AdcClock;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcClock_struct of AdcClock is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-- Components are instantiated by means / through the use of library references.
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Constants
+constant Low : std_logic := '0';
+constant LowNibble : std_logic_vector(4 downto 0) := "00000";
+constant High : std_logic := '1';
+-- Signals
+signal IntBitClkRst : std_logic;
+---------- ISRDS signals ------------------
+signal IntClkCtrlDlyCe : std_logic;
+signal IntClkCtrlDlyInc : std_logic;
+signal IntClkCtrlDlyRst : std_logic;
+
+signal IntBitClk_Ddly : std_logic;
+signal IntBitClk : std_logic;
+signal IntClkCtrlIsrdsMtoS1 : std_logic;
+signal IntClkCtrlIsrdsMtoS2 : std_logic;
+signal IntClkCtrlOut : std_logic_vector(7 downto 0);
+---------- Controller signals -------------
+signal IntCal : std_logic;
+signal IntVal : std_logic;
+signal IntCalVal : std_logic_vector (1 downto 0);
+signal IntProceedCnt : std_logic_vector (2 downto 0);
+signal IntproceedCntTc : std_logic;
+signal IntproceedCntTc_d : std_logic;
+signal IntProceed : std_logic;
+signal IntProceedDone : std_logic;
+
+type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);
+signal State : StateType;
+signal ReturnState : StateType;
+
+signal PassedSubState : std_logic;
+signal IntNumIncDecIdly : std_logic_vector (3 downto 0);
+signal IntAction : std_logic_vector (1 downto 0);
+signal IntClkCtrlDone : std_logic;
+signal IntClkCtrlAlgnWrn : std_logic;
+signal IntClkCtrlInvrtd : std_logic;
+signal IntTurnAroundBit : std_logic;
+signal IntCalValReg : std_logic_vector (1 downto 0);
+signal IntTimeOutCnt : std_logic_vector (3 downto 0);
+signal IntStepCnt : std_logic_vector (3 downto 0);
+-- Attributes
+attribute LOC : string;
+ attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;
+-- The BUFR is generated through a generate statement and therefore the LOC attribute
+-- must be place into the generate statement.
+-- See the BUFR generation down in the source code.
+-----------------------------------------------------------------------------------------------
+signal reset_clockdiv_S : std_logic;
+
+
+begin
+-----------------------------------------------------------------------------------------------
+-- Bit clock capture ISERDES Master-Slave combination
+-----------------------------------------------------------------------------------------------
+--
+AdcClock_I_Iodly : IODELAYE1
+ generic map (
+ SIGNAL_PATTERN => "CLOCK",
+ REFCLK_FREQUENCY => 200.0,
+ HIGH_PERFORMANCE_MODE => TRUE,
+ DELAY_SRC => "I",
+ CINVCTRL_SEL => FALSE,
+ IDELAY_TYPE => "VARIABLE",
+ IDELAY_VALUE => C_StatTaps,
+ ODELAY_TYPE => "FIXED",
+ ODELAY_VALUE => 0
+ )
+ port map (
+ DATAIN => Low, -- in input from FPGA fabric
+ IDATAIN => BitClk, -- in input from IOB
+ ODATAIN => Low, -- in input from I/O SERDES
+ CLKIN => Low, -- in input from BUFIO. BUFG, or BUFR
+ CE => IntClkCtrlDlyCe, -- in
+ INC => IntClkCtrlDlyInc, -- in
+ C => BitClk_RefClkIn, -- in
+ RST => IntClkCtrlDlyRst, -- in
+ T => Low, -- in
+ DATAOUT => IntBitClk_Ddly, -- out Delayed data
+ CINVCTRL => Low, -- in
+ CNTVALUEIN => LowNibble, -- in [4:0]
+ CNTVALUEOUT => open -- out [4:0]
+ );
+IntClkCtrlDlyRst <= BitClkRst;
+--
+AdcClock_I_Isrds_Master : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING",--
+ IOBDELAY => "IBUF", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => 8, --
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => BitClk, -- in Clock from clock input IBUFDS
+ DDLY => IntBitClk_Ddly, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => Low, -- in !!!!!
+ CE1 => BitClkEna, -- in
+ CE2 => Low, -- in
+ RST => IntBitClkRst, -- in
+ CLK => BitClk_MonClkIn, -- in Clock from BUFIO.O = BitClk
+ CLKB => Low, -- in
+ CLKDIV => BitClk_RefClkIn, -- in Clock from BUFR.O = BitClkDiv
+ OCLK => Low, -- in
+ SHIFTOUT1 => IntClkCtrlIsrdsMtoS1,-- out
+ SHIFTOUT2 => IntClkCtrlIsrdsMtoS2,-- out
+ O => IntBitClk, -- out Clock to BUFIO.I
+ Q1 => IntClkCtrlOut(0), -- out
+ Q2 => IntClkCtrlOut(1), -- out
+ Q3 => IntClkCtrlOut(2), -- out
+ Q4 => IntClkCtrlOut(3), -- out
+ Q5 => IntClkCtrlOut(4), -- out
+ Q6 => IntClkCtrlOut(5), -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+--
+AdcClock_I_Isrds_Slave : ISERDESE1
+ generic map (
+ SERDES_MODE => "SLAVE", --
+ INTERFACE_TYPE => "NETWORKING",--
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => 8, --
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => Low, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => Low, -- in !!!!!
+ CE1 => BitClkEna, -- in
+ CE2 => Low, -- in
+ RST => IntBitClkRst, -- in
+ CLK => BitClk_MonClkIn, -- in
+ CLKB => Low, -- in
+ CLKDIV => BitClk_RefClkIn, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => open, -- out
+ Q2 => open, -- out
+ Q3 => IntClkCtrlOut(6), -- out
+ Q4 => IntClkCtrlOut(7), -- out
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => IntClkCtrlIsrdsMtoS1,-- in
+ SHIFTIN2 => IntClkCtrlIsrdsMtoS2 -- in
+ );
+-- Input from ISERDES.O -- Output and CLK for all ISERDES
+AdcClock_I_Bufio : BUFIO
+ port map (I => IntBitClk, O => BitClk_MonClkOut);
+--
+Gen_Bufr_Div_3 : if (C_AdcBits = 12) generate
+ attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
+begin
+ AdcClock_I_Bufr : BUFR
+ generic map (BUFR_DIVIDE => "3", SIM_DEVICE => "VIRTEX6") -- 12-bit = DIV by 3
+-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
+ port map (I => IntBitClk, O => BitClk_RefClkOut,
+ CE => High, CLR => BitClkDivReset);
+end generate;
+--
+Gen_Bufr_Div_4 : if (C_AdcBits /= 12) generate
+ attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
+begin
+ AdcClock_I_Bufr : BUFR
+ generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "VIRTEX6") -- 14- and 16-bit = DIV by 4
+-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
+ port map (I => IntBitClk, O => BitClk_RefClkOut,
+ CE => High, CLR => BitClkDivReset);
+end generate;
+
+
+-----------------------------------------------------------------------------------------------
+-- Bit clock re-synchronizer
+-----------------------------------------------------------------------------------------------
+IntBitClkRst <= BitClkRst or BitClkReSync;
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment input.
+-----------------------------------------------------------------------------------------------
+-- This input section makes sure 64 bits are captured before action is taken to pass to
+-- the statemachine for evaluation.
+-- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel
+-- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.
+-- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)
+-- into an intermediate register (IntCalVal).
+--
+-- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.
+-- IntVal = '1' when all outputs are '0' or '1'.
+--
+IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and
+ IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and
+ IntClkCtrlOut(1) and IntClkCtrlOut(0);
+IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';
+--
+AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)
+begin
+ if (IntBitClkRst = '1') then
+ IntProceedCnt <= (others => '0');
+ IntProceedCntTc_d <= '0';
+ IntCalVal <= (others => '0');
+ IntProceed <= '0';
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+ IntProceedCnt <= IntProceedCnt + 1;
+ IntProceedCntTc_d <= IntProceedCntTc;
+ if (IntProceedCntTc_d = '1') then
+ IntCalVal <= IntCal & IntVal;
+ end if;
+ if (IntProceedCntTc_d = '1') then
+ IntProceed <= '1';
+ elsif (IntProceedDone = '1') then
+ IntProceed <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment state machine.
+-----------------------------------------------------------------------------------------------
+BitClkAlignWarn <= IntClkCtrlAlgnWrn;
+BitClkInvrtd <= IntClkCtrlInvrtd;
+BitClkDone <= IntClkCtrlDone;
+
+AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)
+subtype ActCalVal is std_logic_vector (4 downto 0);
+begin
+ if (IntBitClkRst = '1') then
+ State <= Idle;
+ ReturnState <= Idle;
+ PassedSubState <= '0';
+ --
+ IntNumIncDecIdly <= "0000"; -- Max. 16
+ IntAction <= "00";
+ IntClkCtrlDlyInc <= '1';
+ IntClkCtrlDlyCe <= '0';
+ IntClkCtrlDone <= '0';
+ IntClkCtrlAlgnWrn <= '0';
+ IntClkCtrlInvrtd <= '0';
+ IntTurnAroundBit <= '0';
+ IntProceedDone <= '0';
+ IntClkCtrlDone <= '0';
+ IntCalValReg <= (others => '0'); -- 2-bit
+ IntTimeOutCnt <= (others => '0'); -- 4-bit
+ IntStepCnt <= (others => '0'); -- 4-bit (16)
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+ case State is
+ when Idle =>
+ IntProceedDone <= '0';
+ PassedSubState <= '0';
+ case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is
+ when "00001" => State <= A;
+ when "01001" => State <= B;
+ when "10001" => State <= B;
+ when "11001" => State <= B;
+ when "01111" => State <= C;
+ when "01101" => State <= D;
+ when "01011" => State <= D;
+ when "00011" => State <= E;
+ when "00101" => State <= E;
+ when "00111" => State <= E;
+ when "10011" => State <= F;
+ when "11011" => State <= F;
+ when "10101" => State <= F;
+ when "11101" => State <= F;
+ when "10111" => State <= F;
+ when "11111" => State <= F;
+ when others => State <= Idle;
+ end case;
+ when A => -- First time and sampling in jitter or cross area.
+ IntAction <= "01"; -- Set the action bits and go to next step.
+ State <= B;
+ when B => -- Input is samples in jitter or clock cross area.
+ if (PassedSubState = '1') then
+ PassedSubState <= '0'; -- Clear the pass through the substate bit.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ State <= Idle; -- Return for a new sample of the input.
+ elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong.
+ IntTimeOutCnt <= "0000"; -- Reset the counter.
+ IntAction <= "00"; -- reset the action bits.
+ IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ State <= Idle; -- Retry, return for new sample of input.
+ else
+ IntTimeOutCnt <= IntTimeOutCnt + 1;
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= State; -- This state is the state to return too.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ end if;
+ when C => -- After first sample, jitter or cross, is now high.
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- This state is the state to return too.
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement.
+ State <= IdlyIncDec;
+ when D => -- Same as C but with indication of 180-deg shift.
+ IntClkCtrlInvrtd <= '1';
+ State <= C;
+ when E => -- First saple with valid data.
+ IntCalValReg <= IntCalVal; -- Register the sampled value
+ IntAction <= "10";
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ ReturnState <= Idle; -- When increment is done return sampling.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ when F => -- Next samples with valid data.
+ if (IntCalVal /= IntCalValReg) then
+ State <= G; -- The new CalVal value is different from the first.
+ else
+ if (IntStepCnt = "1111") then -- Step counter at the end, 15
+ if (IntTurnAroundBit = '0') then
+ State <= H; -- No edge found and first time here.
+ elsif (IntCalValReg = "11") then
+ State <= K; -- A turnaround already happend.
+ else -- No edge is found (large 1/2 period).
+ State <= K1; -- Move the clock edge to near the correct
+ end if; -- edge.
+ else
+ IntStepCnt <= IntStepCnt + 1;
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ ReturnState <= Idle; -- When increment is done return sampling.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ end if;
+ end if;
+ when G =>
+ if (IntCalValReg /= "01") then
+ IntClkCtrlInvrtd <= '1';
+ State <= G1;
+ else
+ State <= G1;
+ end if;
+ when G1 =>
+ if (IntTimeOutCnt = "00") then
+ State <= Done;
+ else
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- After decrement it's finished.
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ end if;
+ when H =>
+ IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0.
+ IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero.
+ IntAction <= "00"; -- Take one step, let the counter flow over
+ IntCalValReg <= "00"; -- The idelay turn over to 0.
+ IntTimeOutCnt <= "0000"; -- Start sampling from scratch.
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ ReturnState <= Idle; -- After increment go sampling for new.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K =>
+ IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do.
+ ReturnState <= K2; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K1 =>
+ IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do.
+ ReturnState <= K2; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K2 =>
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ --
+ when IdlyIncDec => -- Increment or decrement by enable.
+ if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps
+ IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement.
+ IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it.
+ else
+ IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it
+ PassedSubState <= '1'; -- Set a check bit "I've been here and passed".
+ State <= ReturnState; -- Return to origin.
+ end if;
+ when Done => -- Alignment done.
+ IntClkCtrlDone <= '1'; -- Alignment is done.
+ end case;
+ end if;
+ end if;
+end process;
+--
+------------------------------------------------------------------------------------------------
+end AdcClock_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd
new file mode 100644
index 0000000..79072ed
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd
@@ -0,0 +1,775 @@
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version:
+-- \ \ Filename: AdcData.vhd
+-- / / Date Last Modified: 15 Feb 2011
+-- /___/ /\ Date Created: 18 Dec 2007
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: Marc Defossez
+-- Entity Name: AdcData
+-- Purpose: 2-channel ADC data receiver interface.
+-- The output of this module is alwasy fprmatted in 32-bit.
+-- When the interface is for a 12-bit ADC then the output is formatted as:
+-- 32 ---------- 16 , 15 ----------- 0
+-- 0000 & (12-bit) , 0000 & (12-bit)
+-- When the interface is for 14-bit or 16-bit the the ouput is formatted as:
+-- 32 ---------- 16 , 15 ----------- 0
+-- ( 16-bit ) , ( 16-bit )
+-- In 1-wire mode the 32-bit output shows two channels
+-- In 2-wire mode the 32-bit output shows two words of the same channel.
+--
+-- Tools: ISE_11.2.xx
+-- Limitations: none
+--
+-- Revision History:
+-- Rev 21 Jun 09
+-- Adaption to Virtex-6
+-- Rev 20 Oct 09
+-- Removal of the input buffers.
+-- FPGA is placed in a different hierarchical level for easyness of portability.
+-- Rev 28 Oct 09
+-- Removal of two mode options.
+-- C_AdcBytOrBitMode and C_AdcMsbOrLsbFst are now coded as default BYTE MODE and MSB FIRST
+-- This can still be changed by making the generics again available at higher HDL levels.
+-- Rev 09 Dec 2010
+-- Made sure the output of the interface is always FFs with enable.
+-- Therefore instantiated the FFs in staid of using plain VHDL descriptions.
+-- Rev 15 Feb 2011
+-- Review of implementation of the AdcData hierarchical level.
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+entity AdcData is
+ generic (
+ C_AdcBits : integer := 16; -- Can be 12, 14 or 16
+ C_AdcBytOrBitMode : integer := 0; -- 1 = BIT mode, 0 = BYTE mode,
+ C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
+ C_AdcWireInt : integer := 1 -- 1 = 1-wire, 2 = 2-wire.
+ );
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatBitSlip_p : in std_logic;
+ DatBitSlip_n : in std_logic;
+ DatSwapMux : in std_logic;
+ DatMsbRegEna : in std_logic;
+ DatLsbRegEna : in std_logic;
+ DatReSync : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end AdcData;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcData_struct of AdcData is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-- Components are instantiated through library naming.
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Functions
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
+function DatBits (Bits : integer) return integer is
+variable Temp : integer;
+begin
+ if (Bits = 12) then
+ Temp := 12;
+ elsif (Bits = 14) then
+ Temp := 16;
+ elsif (Bits = 16) then
+ Temp := 16;
+ end if;
+return Temp;
+end function DatBits;
+-- Constants
+constant IntIsrdsDataWidth : integer := DatBits(C_AdcBits)/4;
+constant Low : std_logic := '0';
+constant High : std_logic := '1';
+-- Signals
+signal IntDatClk : std_logic;
+signal IntDatClk_n : std_logic;
+--
+-- ADC resolution = 12-bit: IntDatSrds0Out(5 downto 0) and IntDatSrds1Out(5 downto 0)
+-- ADC resolution = 14-bit or 16-bit: IntDatSrds0Out(7 downto 0) and IntDatSrds1Out(7 downto 0)
+signal IntDatSrds0Out : std_logic_vector(7 downto 0);
+signal IntDatSrds1Out : std_logic_vector(7 downto 0);
+signal IntDatSrds0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDatSrds1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDatSwpBus : std_logic_vector(31 downto 0);
+signal IntDatDone : std_logic;
+signal IntDatEna : std_logic;
+-- Attributes
+-----------------------------------------------------------------------------------------------
+begin
+--
+-- DatRst en DatEna are synchronised to DatClkDiv on a higher hierarchical level.
+-- the higher level is "AdcToplevel".
+AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
+begin
+ if (DatRst = High) then
+ IntDatDone <= Low;
+ elsif (DatClkDiv'event and DatClkDiv = '1') then
+ IntDatDone <= DatDone;
+ end if;
+end process;
+-- "IntDatDone" enables the ISERDES.
+-- "IntDatEna" is the enable for the logic behind the ISERDES.
+--
+IntDatEna <= High when (IntDatDone = High and DatEna = High) else Low;
+-----------------------------------------------------------------------------------------------
+IntDatClk <= DatClk; -- CLOCK FOR P-side ISERDES
+IntDatClk_n <= not DatClk; -- CLOCK FOR N_side ISERDES
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ZERO
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D0_p : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD0_p, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_p,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(6), -- out (0)
+ Q2 => IntDatSrds0Out(4), -- out (2)
+ Q3 => IntDatSrds0Out(2), -- out (4)
+ Q4 => IntDatSrds0Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+AdcData_I_Isrds_D0_n : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD0_n, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_n,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(7), -- out (1)
+ Q2 => IntDatSrds0Out(5), -- out (3)
+ Q3 => IntDatSrds0Out(3), -- out (5)
+ Q4 => IntDatSrds0Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ONE
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D1_p : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD1_p, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_p,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(6), -- out (0)
+ Q2 => IntDatSrds1Out(4), -- out (2)
+ Q3 => IntDatSrds1Out(2), -- out (4)
+ Q4 => IntDatSrds1Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+AdcData_I_Isrds_D1_n : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD1_n, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_n,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(7), -- out (1)
+ Q2 => IntDatSrds1Out(5), -- out (3)
+ Q3 => IntDatSrds1Out(3), -- out (5)
+ Q4 => IntDatSrds1Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+-----------------------------------------------------------------------------------------------
+Gen_1_DatBus : if (DatBits(C_AdcBits)/2) = 6 generate
+begin
+ IntDatSrds0 <= not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+ not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+ not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+ IntDatSrds1 <= not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+ not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+ not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+end generate;
+Gen_2_DatBus : if (DatBits(C_AdcBits)/2) = 8 generate
+begin
+ IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
+ not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+ not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+ not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+ IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
+ not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+ not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+ not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+end generate;
+-----------------------------------------------------------------------------------------------
+-- DATA REGISTER
+-----------------------------------------------------------------------------------------------
+Gen_1_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcData_I_Fdce_Reg0 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat0(n));
+ AdcData_I_Fdce_Reg1 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat1(n));
+end generate Gen_1_DatReg;
+-----------------------------------------------------------------------------------------------
+-- BIT SWAP MULTIPLEXER and REGISTER
+-- Swap the bits in correct order when the pattern detected is bit swapped.
+-----------------------------------------------------------------------------------------------
+Gen_2_DatMux : for n in (DatBits(C_AdcBits)/4)-1 downto 0 generate
+begin
+ IntDat0Mux((n*2)+1) <= IntDat0(n*2) when (DatSwapMux = '1') else IntDat0((n*2)+1);
+ IntDat0Mux(n*2) <= IntDat0((n*2)+1) when (DatSwapMux = '1') else IntDat0(n*2);
+ IntDat1Mux((n*2)+1) <= IntDat1(n*2) when (DatSwapMux = '1') else IntDat1((n*2)+1);
+ IntDat1Mux(n*2) <= IntDat1((n*2)+1) when (DatSwapMux = '1') else IntDat1(n*2);
+end generate Gen_2_DatMux;
+Gen_3_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcData_I_Fdce_Reg2 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat0Swp(n));
+ AdcData_I_Fdce_Reg3 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat1Swp(n));
+end generate Gen_3_DatReg;
+-----------------------------------------------------------------------------------------------
+-- 1-WIRE, 12x SERIALIZATION for 12-bit ADCs
+-- The data from one ADC will show up in the output of one interface channel. It is so that the
+-- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel and
+-- bits 15:0 show the lower channel.
+-----------------------------------------------------------------------------------------------
+Gen_1w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 1) generate
+ -- 1-wire mode is only coded for BIT wise operation.
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+-- -- MSB first.
+-- -- Output : 31 16 15 0
+-- -- : "0000" & MSB(5:0) & LSB(5:0) "0000" & MSB(5:0) & LSB(5:0)
+ IntDatSwpBus <= "0000" & IntDat1Swp(5 downto 0) & IntDat1Swp(5 downto 0) &
+ "0000" & IntDat0Swp(5 downto 0) & IntDat0Swp(5 downto 0);
+ Gen_1_H : for n in 6 to 15 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ Gen_1_L : for n in 0 to 5 generate
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_L;
+ end generate;
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- LSB first.
+ -- Output : 31 22 & 21 16 & 15 6 & 5 0
+ -- : "0000" & LSB(0:5) & MSB(0:5) "0000" & LSB(0:5) & MSB(0:5)
+ IntDatSwpBus <= "0000" & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 31-|
+ IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-22
+ IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 21-|
+ IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-16
+ "0000" & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 15-|
+ IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5) & -- |-6
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 5-|
+ IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5); -- |-0
+ Gen_1_H : for n in 6 to 15 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ Gen_1_L : for n in 0 to 5 generate
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_L;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 12x SERIALIZATION for 12-bit ADCs
+-- Only one of these options can be chosen at a time.
+-- 2-wire, Msb-Bit or Msb-Byte
+-- 2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+Gen_2w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 2) generate
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ -- Bit mode, MSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D10, D8, D6, D4, D2, D0
+ -- Channel 1 : D11, D9, D7, D5, D3, D1
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_5, 0_5, 1_4, 0_4, 1_3, 0_3, 1_2, 0_2, 1_1, 0_1, 1_0, 0_0
+ Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & "0000"
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ -- Byte mode, MSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D5, D4, D3, D2, D1, D0
+ -- Channel 1 : D11, D10, D9, D8, D7, D6
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_5, 1_4, 1_3, 1_2, 1_1, 1_0, 0_5, 0_4, 0_3, 0_2, 0_1, 0_0
+ Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
+ & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0)
+ & "0000"
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
+ & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ end generate;
+--
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- Bit mode, LSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D0, D2, D4, D6, D8, D10
+ -- Channel 1 : D1, D3, D5, D7, D9, D11
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_0, 0_0, 1_1, 0_1, 1_2, 0_2, 1_3, 0_3, 1_4, 0_4, 1_5, 0_5
+ Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
+ & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
+ & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5)
+ & "0000"
+ & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
+ & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
+ & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ -- Byte Mode, LSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D0, D1, D2, D3, D4, D5
+ -- Channel 1 : D6, D7, D8, D9, D10, D11
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_0, 1_1, 1_2, 1_3, 1_4, 1_5, 0_0, 0_1, 0_2, 0_3, 0_4, 0_5
+ Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
+ & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5)
+ & "0000"
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
+ & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 1-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- The data from one ADC will show up in the output of one interface channel. It is so that the
+-- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel (CH_1)
+-- and bits 15:0 show the lower (CH_0) channel.
+-----------------------------------------------------------------------------------------------
+Gen_1w_1416b : if (C_AdcBits /= 12 and C_AdcWireInt = 1) generate
+ -- 1-wire is only coded for BIT wise operation
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ IntDatSwpBus <= IntDat1Swp(7 downto 0) & IntDat1Swp(7 downto 0) &
+ IntDat0Swp(7 downto 0) & IntDat0Swp(7 downto 0);
+ Gen_1_HL : for n in 0 to 7 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+24));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+8));
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
+ IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
+ IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
+ IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
+ IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7) &
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
+ IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7);
+ Gen_1_HL : for n in 0 to 7 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+24));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+8));
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- Only one of these options can be chosen at a time.
+-- 2-wire, Msb-Bit or Msb-Byte
+-- 2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+Gen_1416Bit : if (C_AdcBits /= 12 and C_AdcWireInt = 2) generate
+-- Shift in order is assumed MSB first.
+ Gen_2_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ -- Bit mode, MSB First, 14-bits (16-bits)
+ -- Bit : 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : 0/(D14), D12, D10, D8, D6, D4, D2, D0
+ -- Channel 1 : 0/(D15), D13, D11, D9, D7, D5, D3, D1
+ Gen1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ -- Byte Mode, MSB First, 14-bits (16-bits)
+ -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0,
+ -- Channel 0 : D7, D6, D5, D4, D3, D2, D1, D0,
+ -- Channel 1 : 0/(D15), 0/(D14), D13, D12, D11, D10, D9, D8
+ Gen1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
+ IntDatSwpBus <= IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
+ & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2)
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
+ & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ end generate;
+-- Shift in order is assumed LSB first
+ Gen_2_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- Bit mode, LSB First, 14-bits (16-bit)
+ -- Data Bit ; 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : D0, D2, D4, D6, D8, D10, D12, 0/(D14)
+ -- Channel 1 : D1, D3, D5, D7, D9, D11, D13, 0/(D15)
+ Gen_2_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
+ & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
+ & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
+ & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5)
+ & IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
+ & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
+ & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
+ & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ -- Byte Mode, LSB First, 14-bits (16-bit)
+ -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : D0, D1, D2, D3, D4, D5, D6, D7
+ -- Channel 1 : D8, D9, D10, D11, D12, D13, 0/(D14), 0/(D15)
+ Gen_2_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
+ IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
+ & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
+ & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
+ & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
+ & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ end generate;
+end generate;
+--
+-----------------------------------------------------------------------------------------------
+end AdcData_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd
new file mode 100644
index 0000000..0c5a3ff
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd
@@ -0,0 +1,859 @@
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
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+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
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+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
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+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
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+--
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+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version:
+-- \ \ Filename: AdcFrame.vhd
+-- / / Date Last Modified: 29 Mar 11
+-- /___/ /\ Date Created: 05 Oct 07
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: Marc Defossez
+-- Entity Name: AdcFrame
+-- Purpose: This file is part of an FPGA interface for a Texas Instruments ADC.
+-- Tools: ISE_13.1
+-- Limitations: none
+--
+-- Revision History:
+-- Rev. 28 Oct 2009
+-- Corrected the circuit to check for "Bouble Nibble" at the output of the ISEDRES.
+-- Made the reaction of this circuit immediate (asynchrounous).
+-- Then synchronousity steps in after registering the signals.
+-- Rev. 16 feb 2011
+-- Replace HDL synthesized FFs by instantiated FFs for frame data path.
+-- Check implementation results is ISE_12.4 with PlanAhead through a AdcFrame_Toplevel.
+-- Rev 07 Mar 2011
+-- Modified the calculation of some "generate" parameters to be able to work in 1-wire
+-- and 2-wire mode. generate parameters to create sets of FFs.
+-- Rev 09 Mar 2011
+-- Problem solved with 1-wire interface not finding correct frame pattern.
+-- In the past 1-wire and 2-wire was selected with 0 and 1 while for recent interfaces
+-- this is changed to 1 and 2 (To reflect in the selection the interface type).
+-- The function calculating the frame pattern for use with the comparator still used
+-- the old selection style. Result was that 2-wire functioned normally and 1-wire
+-- returned a all zero compare pattern.
+-- Finalized the integration and documentation of the "DoubleNibbleDetect".
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+library AdcFrame_lib;
+ use AdcFrame_lib.all;
+--library AdcMem;
+-- use AdcMem.all;
+
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+entity AdcFrame is
+ generic (
+ C_AdcBits : integer;
+ C_AdcWireInt : integer;
+ C_FrmPattern : string
+ );
+ port (
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT
+ FrmClkRst : in std_logic;
+ FrmClkEna : in std_logic;
+ FrmClk : in std_logic;
+ FrmClkDiv : in std_logic;
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.
+ FrmClkReSync : in std_logic;
+ FrmClkBitSlip_p : out std_logic;
+ FrmClkBitSlip_n : out std_logic;
+ FrmClkSwapMux : out std_logic;
+ FrmClkMsbRegEna : out std_logic;
+ FrmClkLsbRegEna : out std_logic;
+ FrmClkReSyncOut : out std_logic;
+ FrmClkDat : out std_logic_vector(15 downto 0);
+ FrmClkSyncWarn : out std_logic;
+ Frame_out : out std_logic;
+ testOK : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end AdcFrame;
+-----------------------------------------------------------------------------------------------
+-- Architecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcFrame_struct of AdcFrame is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Functions
+-- A std_logic_vector is converted to a string.
+ function stdlvec_to_str(inp: std_logic_vector) return string is
+ variable temp: string(inp'left+1 downto 1) := (others => 'X');
+ begin
+ for i in inp'reverse_range loop
+ if (inp(i) = '1') then
+ temp(i+1) := '1';
+ elsif (inp(i) = '0') then
+ temp(i+1) := '0';
+ end if;
+ end loop;
+ return temp;
+ end function stdlvec_to_str;
+--
+-- A string is converted to a std_logic_vector.
+ function str_to_stdlvec(Inp: string) return std_logic_vector is
+ variable Temp : std_logic_vector(Inp'range) := (others => 'X');
+ begin
+ for i in Inp'range loop
+ if (Inp(i) = '1') then
+ Temp(i) := '1';
+ elsif (Inp(i) = '0') then
+ Temp(i) := '0';
+ end if;
+ end loop;
+ return Temp;
+ end function str_to_stdlvec;
+--
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
+ function FrmBits (Bits : integer) return integer is
+ variable Temp : integer;
+ begin
+ if (Bits = 12) then
+ Temp := 12;
+ elsif (Bits = 14) then
+ Temp := 16;
+ elsif (Bits = 16) then
+ Temp := 16;
+ end if;
+ return Temp;
+ end function FrmBits;
+--
+-- Word symmetry check
+-- A word (16-bit) is checked for bit pair symmetry
+-- Example: In one byte there are 16 possible symmetry positions.
+-- 00000000, 00000011, 00001100, 00001111,
+-- 00110000, 00110011, 00111100, 00111111,
+-- 11000000, 11000011, 11001100, 11001111,
+-- 11110000, 11110011, 11111100, 11111111,
+-- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0
+ function SymChck (Inp: std_logic_vector) return std_logic is
+ variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');
+ variable Sym : std_logic := '0';
+ begin
+ for n in (Inp'left-1)/2 downto 0 loop
+ Temp(n) := Inp((n*2)+1) xor Inp(n*2);
+ Sym := Temp(n) or Sym;
+ end loop;
+ assert false
+ report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR
+ severity note;
+ return Sym;
+ end function SymChck;
+--
+-- When a symmetric byte, bit pattern is found, make the requested pattern rotate
+-- by one bit to become a non-symmetric pattern.
+ function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is
+ variable Temp : std_logic_vector (Inp'range):= (others => '0');
+ begin
+-- Bit shift all bits.
+-- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000
+-- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000
+ if (SymChck(Inp) = '0') then
+ if (Wire = 1 ) then -- 1-wire, shift 15-bits
+ for n in Inp'left downto 0 loop
+ if (n /= 0) then
+ Temp(n) := Inp(n-1);
+ elsif (n = 0) then
+ Temp(Temp'right) := Inp(Inp'left);
+ end if;
+ end loop;
+ else -- (Wire = 2) -- 2-wire, shift 8-bits
+ for n in (Inp'left-8) downto 0 loop
+ if (n /= 0) then
+ Temp(n) := Inp(n-1);
+ elsif (n = 0) then
+ Temp(Temp'right) := Inp(Inp'left-8);
+ end if;
+ end loop;
+ end if;
+ elsif (SymChck(Inp) = '1') then
+ -- Don't do anything, return the word as it came in.
+ Temp := Inp;
+ end if;
+ --
+ assert false
+ report CR &
+ " Pattern Shifted = " & stdlvec_to_str(Temp) & CR &
+ " Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
+ " Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR
+ severity note;
+ return Temp;
+ end function BitShft;
+--
+-- Bit swap operation:
+-- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).
+-- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).
+-- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).
+-- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).
+-- and etcetera....
+-- This: Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.
+-- Results in: Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.
+ function BitSwap(Inp: std_logic_vector) return std_logic_vector is
+ variable Temp : std_logic_vector (Inp'range);
+ begin
+ for n in (Inp'left-1)/2 downto 0 loop
+ Temp((n*2)+1) := Inp(n*2);
+ Temp(n*2) := Inp((n*2)+1);
+ end loop;
+ assert false
+ report CR &
+ " Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &
+ " Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
+ " Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0)) & CR
+ severity note;
+ return Temp;
+ end function BitSwap;
+--
+ function TermOrNot (Term : integer) return boolean is
+ begin
+ if (Term = 0) then
+ return FALSE;
+ else
+ return TRUE;
+ end if;
+ end TermOrNot;
+
+component DoubleNibbleDetect is
+ port (
+ Clock : in std_logic;
+ RstIn : in std_logic;
+ Final : out std_logic;
+ DataIn : in std_logic_vector(3 downto 0);
+ DataOut : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+component GenPulse is
+ port (
+ Clk : in std_logic;
+ Ena : in std_logic;
+ SigIn : in std_logic;
+ SigOut : out std_logic
+ );
+end component;
+
+--
+-- Constants
+-- Transform the pattern STRING into a std_logic_vector.
+constant IntPattern :
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := str_to_stdlvec(C_FrmPattern);
+-- Shift the pattern for one bit.
+constant IntPatternBitShifted :
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitShft(IntPattern, C_AdcWireInt);
+-- Bit swap the by one bit shifted pattern.
+constant IntPatternBitSwapped :
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitSwap(IntPatternBitShifted);
+-- Define the bytes for pattern comparison.
+constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
+ IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
+constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
+ IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);
+constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
+ IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
+constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
+ IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);
+-- Calculate the data width for a ISERDES.
+constant IntIsrdsDataWidth : integer := FrmBits(C_AdcBits)/4;
+constant Low : std_logic := '0';
+constant High : std_logic := '1';
+attribute keep : string;
+-- Signals
+signal IntFrmClk : std_logic;
+signal IntFrmClk_n : std_logic;
+signal IntFrmSrdsOut : std_logic_vector (7 downto 0);
+--
+signal IntFrmSrdsDatEvn : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
+signal IntFrmSrdsDatOdd : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
+signal IntFrmSrdsDatEvn_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
+signal IntFrmSrdsDatOdd_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
+signal IntFrmSrdsDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
+signal IntFrmDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
+signal IntFrmDatMux : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
+signal IntFrmDatSwp : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
+signal IntFrmDatSwpBus : std_logic_vector(15 downto 0);
+signal IntFrmClkDat : std_logic_vector(15 downto 0);
+--
+signal IntFrmDbleNibFnlEvn : std_logic;
+signal IntFrmDbleNibFnlEvn_d : std_logic;
+signal IntFrmDbleNibFnlOdd : std_logic;
+signal IntFrmDbleNibFnlOdd_d : std_logic;
+signal IntFrmDbleNibFnl : std_logic;
+--
+signal IntFrmEna : std_logic;
+signal IntFrmCmp : std_logic_vector(3 downto 0);
+signal IntFrmEquGte : std_logic;
+signal IntFrmEqu_d : std_logic;
+signal IntFrmSwapMux_d : std_logic;
+signal IntFrmSwapMux_d_Ena : std_logic;
+signal IntFrmLsbMsb_d : std_logic;
+signal IntFrmLsbMsb_d_Ena : std_logic;
+signal IntFrmMsbAllZero_d : std_logic;
+signal IntFrmMsbAllZero_d_Ena : std_logic;
+--
+signal IntFrmRegEna_d : std_logic;
+signal IntFrmMsbRegEna_d : std_logic;
+signal IntFrmLsbRegEna_d : std_logic;
+--
+signal IntFrmEvntCnt : std_logic_vector (3 downto 0); -- count event counter
+signal IntFrmEvntCntTc : std_logic;
+signal IntFrmEvntCntTc_d : std_logic;
+signal IntFrmSlipCnt : std_logic_vector (3 downto 0); -- count to 8
+signal IntFrmSlipCntTc : std_logic;
+signal IntFrmSlipCntTc_d : std_logic;
+signal IntFrmSlipCntTc_d1 : std_logic;
+signal IntFrmSlipCntTc_d2Ena : std_logic;
+signal IntFrmSlipCntTc_d2 : std_logic;
+signal IntFrmWarnCnt : std_logic_vector (2 downto 0);
+signal IntFrmWarnCntTc : std_logic;
+signal IntFrmWarnCntTc_d : std_logic;
+signal IntFrmClkReSync : std_logic;
+signal IntFrmReSyncOut : std_logic;
+--
+signal IntFrmBitSlip : std_logic_vector (5 downto 0);
+signal IntFrmEquSet_d : std_Logic;
+
+signal Frame_out_S : std_Logic;
+-- Attributes
+attribute keep of Frame_out_S : signal is "TRUE";
+-----------------------------------------------------------------------------------------------
+begin
+-----------------------------------------------------------------------------------------------
+-- ISERDES FOR FRAME CAPTURE
+-----------------------------------------------------------------------------------------------
+IntFrmClk <= FrmClk;
+IntFrmClk_n <= not FrmClk;
+--
+AdcFrame_I_Isrds_p : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => FrmClk_p, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => IntFrmBitSlip(0),-- in
+ CE1 => IntFrmEna, -- in
+ CE2 => Low, -- in
+ RST => FrmClkRst, -- in
+ CLK => IntFrmClk, -- in
+ CLKB => Low, -- in
+ CLKDIV => FrmClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => Frame_out_S, -- out
+ Q1 => IntFrmSrdsOut(6), -- out (0)
+ Q2 => IntFrmSrdsOut(4), -- out (2)
+ Q3 => IntFrmSrdsOut(2), -- out (4)
+ Q4 => IntFrmSrdsOut(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+Frame_out <= Frame_out_S;
+
+AdcFrame_I_Isrds_n : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- 12-bit = 3 and 14/16 b its = 4
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => FrmClk_n, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => IntFrmBitSlip(1),-- in
+ CE1 => IntFrmEna, -- in
+ CE2 => Low, -- in
+ RST => FrmClkRst, -- in
+ CLK => IntFrmClk_n, -- in
+ CLKB => Low, -- in
+ CLKDIV => FrmClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntFrmSrdsOut(7), -- out (1)
+ Q2 => IntFrmSrdsOut(5), -- out (3)
+ Q3 => IntFrmSrdsOut(3), -- out (5)
+ Q4 => IntFrmSrdsOut(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+-----------------------------------------------------------------------------------------------
+-- INVERT THE NEEDED BITS.
+-----------------------------------------------------------------------------------------------
+Gen_1_FrmBus : if (FrmBits(C_AdcBits)/2) = 6 generate
+ IntFrmSrdsDatEvn <= IntFrmSrdsOut(4) & IntFrmSrdsOut(2) & IntFrmSrdsOut(0);
+ IntFrmSrdsDatOdd <= not IntFrmSrdsOut(5) & not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1);
+end generate Gen_1_FrmBus;
+Gen_2_FrmBus : if (FrmBits(C_AdcBits)/2) = 8 generate
+ IntFrmSrdsDatEvn <= IntFrmSrdsOut(6) & IntFrmSrdsOut(4) &
+ IntFrmSrdsOut(2) & IntFrmSrdsOut(0);
+ IntFrmSrdsDatOdd <= not IntFrmSrdsOut(7) & not IntFrmSrdsOut(5) &
+ not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1);
+end generate Gen_2_FrmBus;
+-----------------------------------------------------------------------------------------------
+-- Double Nibble Detection.
+-- When the ADC is used in 1-wire mode the frame pattern is 12 or 16 bits long.
+-- It is captured in two ISERDES. One running at rising CLK and the orther runnsing at falling
+-- CLK. For some reason, afetr a bitslip a ISERDES can output twice the same nibble of data.
+-- This phenomenon is called ""Double nibble" and as written before happens after a
+-- Bitslip request.
+-- The output of each ISERDES is first checked for these double nibbles and if needed the
+-- ISERDES output is corrected. After that the data is passed into the franme pattern
+-- Recognition part of the design.
+-----------------------------------------------------------------------------------------------
+Gen_1_DbleNibChk : if (C_AdcWireInt = 1) generate
+ AdcFrame_I_DblNbblDtct_Evn : DoubleNibbleDetect
+ port map (
+ Clock => FrmClkDiv, -- in
+ RstIn => FrmClkRst, -- in
+ Final => IntFrmDbleNibFnlEvn, -- out
+ DataIn => IntFrmSrdsDatEvn, -- in [3:0]
+ DataOut => IntFrmSrdsDatEvn_d -- out [3:0]
+ );
+--
+ AdcFrame_I_DblNbblDtct_Odd : DoubleNibbleDetect
+ port map (
+ Clock => FrmClkDiv, -- in
+ RstIn => FrmClkRst, -- in
+ Final => IntFrmDbleNibFnlOdd, -- out
+ DataIn => IntFrmSrdsDatOdd, -- in [3:0]
+ DataOut => IntFrmSrdsDatOdd_d -- out [3:0]
+ );
+--
+ AdcFrame_DblNibFnl_PROCESS : process (FrmClkDiv)
+ begin
+ if (FrmClkRst = '1' ) then
+ IntFrmDbleNibFnlOdd_d <= '0';
+ IntFrmDbleNibFnlEvn_d <= '0';
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ if (IntFrmDbleNibFnlOdd = '1') then
+ IntFrmDbleNibFnlOdd_d <= '1';
+ else --(IntFrmDbleNibFnlOdd = '0')
+ IntFrmDbleNibFnlOdd_d <= '0';
+ end if;
+ if (IntFrmDbleNibFnlEvn = '1') then
+ IntFrmDbleNibFnlEvn_d <= '1';
+ else --(IntFrmDbleNibFnlOdd = '0')
+ IntFrmDbleNibFnlEvn_d <= '0';
+ end if;
+ end if;
+ end process AdcFrame_DblNibFnl_PROCESS;
+--
+ IntFrmDbleNibFnl <= IntFrmDbleNibFnlOdd_d and IntFrmDbleNibFnlEvn_d;
+end generate Gen_1_DbleNibChk;
+--
+Gen_2_DbleNibChk : if (C_AdcWireInt = 2) generate
+ IntFrmSrdsDatEvn_d <= IntFrmSrdsDatEvn;
+ IntFrmSrdsDatOdd_d <= IntFrmSrdsDatOdd;
+ IntFrmDbleNibFnl <= Low;
+end generate Gen_2_DbleNibChk;
+-----------------------------------------------------------------------------------------------
+-- DATA REGISTER
+-----------------------------------------------------------------------------------------------
+Gen_1_DatBus : for n in (FrmBits(C_AdcBits)/4) downto 1 generate
+ IntFrmSrdsDat((n*2)-1) <= IntFrmSrdsDatOdd_d(n-1);
+ IntFrmSrdsDat((n*2)-2) <= IntFrmSrdsDatEvn_d(n-1);
+end generate Gen_1_DatBus;
+--
+Gen_1_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcFrame_I_Fdce_Reg1 : FDCE
+ generic map (INIT => '0') -- bit
+ port map(D => IntFrmSrdsDat(n), CE => IntFrmEna, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmDat(n));
+end generate Gen_1_DatReg;
+-----------------------------------------------------------------------------------------------
+-- BIT SWAP MULTIPLEXER and REGISTER
+-- Swap the bits in correct order when the pattern detected is bit swapped.
+-----------------------------------------------------------------------------------------------
+Gen_2_DatMux : for n in (FrmBits(C_AdcBits)/4)-1 downto 0 generate
+begin
+ IntFrmDatMux((n*2)+1) <= IntFrmDat(n*2) when (IntFrmSwapMux_d = '1') else IntFrmDat((n*2)+1);
+ IntFrmDatMux(n*2) <= IntFrmDat((n*2)+1) when (IntFrmSwapMux_d = '1') else IntFrmDat(n*2);
+end generate Gen_2_DatMux;
+Gen_3_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcFrame_I_Fdce_Reg2 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntFrmDatMux(n), C => FrmClkDiv, CE => IntFrmEna, CLR => IntFrmReSyncOut,
+ Q => IntFrmDatSwp(n));
+end generate Gen_3_DatReg;
+-----------------------------------------------------------------------------------------------
+-- FRAME OUTPUT REGISTERS
+-----------------------------------------------------------------------------------------------
+Gen_4_OutReg12 : if C_AdcBits = 12 generate
+ IntFrmDatSwpBus <= "0000" &
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &
+ IntFrmDatSwp(1) & IntFrmDatSwp(0) &
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &
+ IntFrmDatSwp(1) & IntFrmDatSwp(0);
+ Gen_4_H : for n in 6 to 15 generate
+ AdcFrame_I_Fdce_FrmClkDatMsb : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
+ end generate Gen_4_H;
+ Gen_4_L : for n in 0 to 5 generate
+ AdcFrame_I_Fdce_FrmClkDatLsb : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
+ end generate Gen_4_L;
+end generate Gen_4_OutReg12;
+--
+Gen_5_OutReg12n : if C_AdcBits /= 12 generate
+ IntFrmDatSwpBus <= IntFrmDatSwp(7) & IntFrmDatSwp(6) &
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &
+ IntFrmDatSwp(1) & IntFrmDatSwp(0) &
+ IntFrmDatSwp(7) & IntFrmDatSwp(6) &
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &
+ IntFrmDatSwp(1) & IntFrmDatSwp(0);
+ Gen_5_H : for n in 8 to 15 generate
+ AdcFrame_I_Fdce_FrmClkDatMsb : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
+ end generate Gen_5_H;
+ Gen_5_L : for n in 0 to 7 generate
+ AdcFrame_I_Fdce_FrmClkDatLsb : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
+ end generate Gen_5_L;
+end generate Gen_5_OutReg12n;
+--
+FrmClkDat <= IntFrmClkDat;
+-----------------------------------------------------------------------------------------------
+-- FRAME PATTERN COMPARATOR
+-----------------------------------------------------------------------------------------------
+IntFrmCmp(2 downto 0) <= "101" when (IntFrmSrdsDat = IntPatternA) else -- Equ, , Msb
+ "100" when (IntFrmSrdsDat = IntPatternB) else -- Equ, , Lsb
+ "111" when (IntFrmSrdsDat = IntPatternC) else -- Equ, swpd, Msb
+ "110" when (IntFrmSrdsDat = IntPatternD) else -- Equ, Swpd, Lsb
+ "000";
+IntFrmCmp(3) <= High when (C_AdcWireInt = 2) else Low; -- Msb = all zero
+--
+-- When "Equ" goes high, one of the four patterns has been found.
+-- The other two signals will reflect (Msb or Lsb, bitswapped or not) what pattern has been
+-- found. WHen "Equ" thus goes high, store the status of all signals and make sure it can't
+-- be changed.
+--
+IntFrmEquGte <= (IntFrmCmp(2) or IntFrmEqu_d) and IntFrmEna;
+--
+AdcFrame_I_Fdce_FrmMsbAllZero_d : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmCmp(3), CE => IntFrmMsbAllZero_d_Ena, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmMsbAllZero_d);
+AdcFrame_I_Fdce_FrmEqu_d : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmEquGte, CE => High, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmEqu_d);
+AdcFrame_I_Fdce_FrmSwapMux_d : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmCmp(1), CE => IntFrmSwapMux_d_Ena, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmSwapMux_d);
+AdcFrame_I_Fdce_FrmLsbMsb_d : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmCmp(0), CE => IntFrmLsbMsb_d_Ena, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmLsbMsb_d);
+--
+IntFrmMsbAllZero_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;
+IntFrmSwapMux_d_Ena <= IntFrmCmp(2)and not IntFrmEqu_d;
+IntFrmLsbMsb_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;
+FrmClkSwapMux <= IntFrmSwapMux_d;
+-----------------------------------------------------------------------------------------------
+-- OUTPUT REGISTER ENABLER
+-----------------------------------------------------------------------------------------------
+AdcFrame_EnaSel_PROCESS : process (FrmClkDiv, IntFrmMsbAllZero_d, IntFrmEqu_d)
+subtype IntFrmRegEnaCase is std_logic_vector(4 downto 0);
+begin
+ if (IntFrmMsbAllZero_d = High) then
+ IntFrmRegEna_d <= Low;
+ IntFrmMsbRegEna_d <= High;
+ IntFrmLsbRegEna_d <= High;
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ case IntFrmRegEnaCase'(IntFrmLsbMsb_d, IntFrmEqu_d, IntFrmRegEna_d,
+ IntFrmMsbRegEna_d, IntFrmLsbRegEna_d) is
+ when "00001" => IntFrmRegEna_d <= '0';
+ IntFrmMsbRegEna_d <= '0'; -- A
+ IntFrmLsbRegEna_d <= '1'; --
+ when "01001" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '0'; -- B
+ IntFrmLsbRegEna_d <= '1'; --
+ when "01101" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '1'; -- C
+ IntFrmLsbRegEna_d <= '0'; --
+ when "01110" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '0'; -- D, goto C
+ IntFrmLsbRegEna_d <= '1'; --
+ --
+ when "11001" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '1'; -- E
+ IntFrmLsbRegEna_d <= '0'; --
+ when "11110" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '0'; -- F
+ IntFrmLsbRegEna_d <= '1'; --
+ when "11101" => IntFrmRegEna_d <= '1';
+ IntFrmMsbRegEna_d <= '1'; -- G, goto F
+ IntFrmLsbRegEna_d <= '0'; --
+ --
+ when others => IntFrmRegEna_d <= '0';
+ IntFrmMsbRegEna_d <= '0';
+ IntFrmLsbRegEna_d <= '1';
+ end case;
+ end if;
+end process;
+FrmClkMsbRegEna <= IntFrmMsbRegEna_d;
+FrmClkLsbRegEna <= IntFrmLsbRegEna_d;
+-----------------------------------------------------------------------------------------------
+-- SAMPLE EVENT COUNTER
+-- Take a frame sample every 16 ClkDiv cycles.
+-----------------------------------------------------------------------------------------------
+AdcFrame_EvntCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)
+begin
+ if (IntFrmReSyncOut = High) then
+ IntFrmEvntCnt <= (others => '0');
+ IntFrmEvntCntTc_d <= Low;
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ if (IntFrmEquSet_d = Low and IntFrmEna = High) then
+ IntFrmEvntCnt <= IntFrmEvntCnt + "01";
+ IntFrmEvntCntTc_d <= IntFrmEvntCntTc;
+ end if;
+ end if;
+end process;
+IntFrmEvntCntTc <= High when (IntFrmEvntCnt = "1110") else Low;
+--IntFrmEvntCntTc <= High when (IntFrmEvntCnt = ((2**IntFrmEvntCnt'length)-2)) else Low;
+-----------------------------------------------------------------------------------------------
+-- BITSLIP EVENT COUNTER
+-- Bitslip 8 times for a 8-bit ISERDES and 6 times for a 6-bit ISERDES.
+-----------------------------------------------------------------------------------------------
+AdcFrame_SlipCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)
+begin
+ if (IntFrmReSyncOut = High) then
+ IntFrmSlipCnt <= (others => '0');
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ if (IntFrmEvntCntTc_d = High) then
+ IntFrmSlipCnt <= IntFrmSlipCnt + "01";
+ end if;
+ if (IntFrmEvntCntTc_d = High and IntFrmSlipCntTc = High) then
+ IntFrmSlipCntTc_d <= High;
+ else
+ IntFrmSlipCntTc_d <= Low;
+ end if;
+ end if;
+end process;
+--Terminal count points.
+AdcFrame_SlipCntTc_12 : if (FrmBits(C_AdcBits) = 12) generate
+ IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'
+end generate;
+AdcFrame_SlipCntTc_1_16 : if (FrmBits(C_AdcBits) = 16) generate
+ IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'
+end generate;
+--AdcFrame_SlipCntTc_1_12 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 12) generate
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'
+--end generate;
+--AdcFrame_SlipCntTc_2_12 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 12) generate
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0101") else Low; -- 5
+--end generate;
+--AdcFrame_SlipCntTc_1_16 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 16) generate
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'
+--end generate;
+--AdcFrame_SlipCntTc_2_16 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 16) generate
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0111") else Low; -- 7
+--end generate;
+AdcFrame_I_Fdce_SlipCntTc_1 : FDCE
+ generic map (INIT => '0')
+ port map (D => High, CE => IntFrmSlipCntTc_d, C => FrmClkDiv,
+ CLR => IntFrmSlipCntTc_d2, Q => IntFrmSlipCntTc_d1);
+IntFrmSlipCntTc_d2Ena <= IntFrmSlipCntTc_d and IntFrmSlipCntTc_d1;
+AdcFrame_I_Fdce_SlipCntTc_2 : FDCE
+ generic map (INIT => '0')
+ port map (D => IntFrmSlipCntTc_d2Ena, CE => High, C => FrmClkDiv,
+ CLR => IntFrmReSyncOut, Q => IntFrmSlipCntTc_d2);
+-----------------------------------------------------------------------------------------------
+-- WARNING EVENT COUNTER
+-- When this counter issues terminal count, sunchronisation was impossible for 8 times.
+-----------------------------------------------------------------------------------------------
+AdcFrame_WarnCnt_PROCESS : process (FrmClkDiv, FrmClkRst)
+begin
+ if (FrmClkRst = High) then
+ IntFrmWarnCnt <= (others => '0');
+ IntFrmWarnCntTc_d <= Low;
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ if (IntFrmSlipCntTc_d = High) then
+ IntFrmWarnCnt <= IntFrmWarnCnt + "01";
+ IntFrmWarnCntTc_d <= IntFrmWarnCntTc;
+ end if;
+ end if;
+end process;
+IntFrmWarnCntTc <= High when (IntFrmWarnCnt = "110") else Low;
+FrmClkSyncWarn <= IntFrmWarnCntTc_d;
+-----------------------------------------------------------------------------------------------
+-- Enable, RESYNC or INTERNAL RESET
+-- This is the reset logic for the whole design.
+-- Whenever one of these signals (IntFrmSlipCntTc_d2, IntFrmDbleNibFnl, FrmClkReSync, FrmClkRst)
+-- is high the circuit is pulled int reset (call it a re-sync operation).
+--
+-- The only components not influenced by this are the ISERDES and the Sync Warning Counter.
+-- they only act on the extrenal "FrmClkRst" input.
+--
+-- A circuit enable "IntFrmEna" is generated when the inputs "FrmClkDone" and "FrmClkEna" are
+-- high and when the "IntFrmReSync" reset is released.
+-----------------------------------------------------------------------------------------------
+AdcFrame_I_GenPulse_1 : GenPulse
+ port map (
+ Clk => FrmClkDiv, -- in
+ Ena => High, -- in
+ SigIn => FrmClkReSync, -- in
+ SigOut => IntFrmClkReSync -- out
+ );
+IntFrmReSyncOut <= IntFrmSlipCntTc_d2 or IntFrmDbleNibFnl or IntFrmClkReSync or FrmClkRst;
+FrmClkReSyncOut <= IntFrmReSyncOut;
+--
+AdcFrame_I_Fdce_Done : FDCE
+ generic map (INIT => '0') -- bit
+ port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => IntFrmReSyncOut,
+ Q => IntFrmEna);
+-----------------------------------------------------------------------------------------------
+-- BITSLIP STATE MACHINE.
+-----------------------------------------------------------------------------------------------
+AdcFrame_Bitslip_PROCESS : process (IntFrmReSyncOut, FrmClkDiv)
+subtype IntFrmBitSlipCase is std_logic_vector(5 downto 0);
+begin
+ if (IntFrmReSyncOut = High) then
+ IntFrmBitSlip <= (others => '0');
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then
+ if (IntFrmEna = High and IntFrmEquSet_d = Low) then
+ case IntFrmBitSlipCase'(IntFrmEqu_d, IntFrmEvntCntTc_d, IntFrmBitSlip(5),
+ IntFrmBitSlip(4), IntFrmBitSlip(3), IntFrmBitSlip(2)) is
+ when "000000" => IntFrmBitSlip <= "000000"; -- B
+ when "010000" => IntFrmBitSlip <= "000101"; -- C Slip_p
+ when "000001" => IntFrmBitSlip <= "000100"; -- D
+ when "010001" => IntFrmBitSlip <= "001010"; -- E Slip_n
+ when "000010" => IntFrmBitSlip <= "001000"; -- F
+ when "010010" => IntFrmBitSlip <= "000101"; -- G Slip_p and goto D
+ --
+ when "100000" => IntFrmBitSlip <= "000000"; -- H
+ when "110000" => IntFrmBitSlip <= "100101"; -- K Slip_p
+ when "101001" => IntFrmBitSlip <= "110000"; -- L EquSet
+ when "101100" => IntFrmBitSlip <= "110000"; -- M Halt
+ --
+ when "100001" => IntFrmBitSlip <= "000100"; -- N
+ when "110001" => IntFrmBitSlip <= "101010"; -- P Slip_n
+ when "101010" => IntFrmBitSlip <= "110000"; -- R EquSet goto M
+ --
+ when "100010" => IntFrmBitSlip <= "001000"; -- S
+ when "110010" => IntFrmBitSlip <= "100101"; -- T Slip_p goto L
+ --
+ when others => IntFrmBitSlip <= "110000";
+ end case;
+ end if;
+ end if;
+end process;
+FrmClkBitSlip_p <= IntFrmBitSlip(0);
+FrmClkBitSlip_n <= IntFrmBitSlip(1);
+IntFrmEquSet_d <= IntFrmBitSlip(4);
+
+
+testword0(7 downto 0) <= IntFrmSrdsOut;
+testOK <= '1' when IntFrmSrdsOut=x"A5" else '0';
+
+--
+-----------------------------------------------------------------------------------------------
+end AdcFrame_struct;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd
new file mode 100644
index 0000000..77959dd
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd
@@ -0,0 +1,739 @@
+----------------------------------------------------------------------------------------------
+-- Copyright 2010, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx Inc.
+-- \ \ \/ Version:
+-- \ \
+-- / / Filename: AdcToplevel.vhd
+-- /___/ /\ Date Created: Nov 07
+-- \ \ / \ Date Last Modified: 7 Mar 2011
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: defossez
+-- Entity Name: AdcToplevel
+-- Purpose: Top level for an interface between a Virtex-6 FPGA and ADS6245
+-- Tools: ISE_13.1
+-- Limitations: none
+--
+-- Revision History:
+-- Rev. 20 Oct 09
+-- Made the ADC interface more generic, with speate FPGA IO file and etcetera.
+-- Rev. 27 Dec 10
+-- Retrived the file after accidental delete.
+-- Rev. 7 Mar 11
+-- - Adjustment of the range, in the entity declaration, of "AdcMemFlags" when
+-- used for 1 and 2 wire interface.
+-- - Brought the generic C_FrmPattern to the top level entity declaration. Now it is
+-- possible to provide the frame pattern to search for when the AdcToplevel component
+-- is instantiated.
+-- - Added extensive comments for teh top level entity generics and ports.
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+-- GENERICS
+-- C_AdcChnls -- ADC Channels available in a package.
+-- C_AdcBits -- Value can be 12, 14, or 16 (14 is means 14-bit burried in 16-bit)
+-- C_AdcWireInt -- 0 = 1-wire, 1 = 2-wire
+-- C_FrmPattern -- Pattern to lock the frame to.
+--
+-- A 14 or 16 bit ADC in 2-wire mode has a 8-bit frame pattern. The C_FrmPattern parameter
+-- must be set to: C_FrmPattern ==> "0000000011110000".
+-- A 14 or 16 bit ADC in 1-wire mode has a 16-bit frame pattern. The C_FrmPattern parameter
+-- must be set to: C_FrmPattern ==> "1111111100000000".
+-- The same applies for a 12-bit ADC device.
+-- C_FrmPattern : string := "111111000000"; -- 1-wire, 12 bit.
+-- C_FrmPattern : string := "000000111000"; -- 2-wire, 12 bit.
+--
+-- C_StatTaps -- Number of taps the IDELAY starts from (Middle of the Tap chain).
+-- C_IdelayCtrlLoc -- Hard location of the IDELAYCTRL component.
+-- PORTS
+-- DATA_n -- I -- ADC data input signals from the ADC device.
+-- DATA_p -- I --
+-- DCLK_n, DCLK_p -- I -- High speed clock from the ADC device.
+-- FCLK_n, FCLK_p -- I -- Word or frame clock from the ADC device.
+-- SysRefClk -- I -- Reference clock for IDELAYCTRL (200 MHz).
+-- AdcIntrfcRst -- I -- Reset for the interface from the application.
+-- AdcIntrfcEna -- I -- Enable signal for the interface from the application.
+-- AdcReSync -- I -- Signal to restart the resync process.
+-- AdcFrmSyncWrn -- O -- Warning from the sync logic, alignment is not possible
+-- AdcBitClkAlgnWrn -- O -- Status signal. BitClock adjusted.
+-- AdcBitClkInvrtd -- O -- Bit clock state, rising or falling
+-- AdcBitClkDone -- O -- Bit clock alignment done
+-- AdcIdlyCtrlRdy -- O -- IDELAYCTRL ready
+
+-----------------------------------------------------------------------------------------------
+entity AdcToplevel is
+ generic (
+ C_AdcChnls : integer := 4; -- Number of ADC in a package
+ C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc : string := "BUFIODQS_X0Y12";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_AdcBits : integer := 16;
+ C_StatTaps : integer := 16;
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";
+ C_FrmPattern : string := "0000000011110000" -- Read above text!
+ );
+ port (
+ DCLK_p : in std_logic;
+ DCLK_n : in std_logic; -- Not used.
+ FCLK_p : in std_logic;
+ FCLK_n : in std_logic;
+ DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ -- application connections
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
+ AdcIntrfcRst : in std_logic;
+ AdcIntrfcEna : in std_logic;
+ AdcReSync : in std_logic;
+ AdcFrmSyncWrn : out std_logic;
+ AdcBitClkAlgnWrn : out std_logic;
+ AdcBitClkInvrtd : out std_logic;
+ AdcBitClkDone : out std_logic;
+ AdcIdlyCtrlRdy : out std_logic;
+
+ AdcClkDiv : out std_logic;
+ AdcDataClk : in std_logic;
+ AdcDataClkNot : in std_logic;
+ AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+ ADCs_ready : out std_logic;
+ testOK : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end AdcToplevel;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcToplevel_struct of AdcToplevel is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Functions
+function int_to_chr(int: integer) return character is
+ variable temp : character;
+begin
+ case int is
+ when 0 => temp := '0';
+ when 1 => temp := '1';
+ when 2 => temp := '2';
+ when 3 => temp := '3';
+ when 4 => temp := '4';
+ when 5 => temp := '5';
+ when 6 => temp := '6';
+ when 7 => temp := '7';
+ when 8 => temp := '8';
+ when 9 => temp := '9';
+ when 10 => temp := 'A';
+ when 11 => temp := 'B';
+ when 12 => temp := 'C';
+ when 13 => temp := 'D';
+ when 14 => temp := 'E';
+ when 15 => temp := 'F';
+ when 16 => temp := 'G';
+ when 17 => temp := 'H';
+ when 18 => temp := 'I';
+ when 19 => temp := 'J';
+ when 20 => temp := 'K';
+ when 21 => temp := 'L';
+ when 22 => temp := 'M';
+ when 23 => temp := 'N';
+ when 24 => temp := 'O';
+ when 25 => temp := 'P';
+ when 26 => temp := 'Q';
+ when 27 => temp := 'R';
+ when 28 => temp := 'S';
+ when 29 => temp := 'T';
+ when 30 => temp := 'U';
+ when 31 => temp := 'V';
+ when 32 => temp := 'W';
+ when 33 => temp := 'X';
+ when 34 => temp := 'Y';
+ when 35 => temp := 'Z';
+ when others => temp := '?';
+ end case;
+return temp;
+end function int_to_chr;
+--
+function int_to_str(int: integer; base: integer) return string is
+ variable temp: string(1 to 10);
+ variable num: integer;
+ variable abs_int: integer;
+ variable len: integer := 1;
+ variable power: integer := 1;
+begin
+ abs_int := abs(int); -- Negative numbers
+ num := abs_int;
+
+ while num >= base loop -- Determine how many
+ len := len + 1; -- characters required
+ num := num / base; -- to represent the
+ end loop ; -- number.
+
+ for i in len downto 1 loop -- Convert the number to
+ temp(i) := int_to_chr(abs_int/power mod base); -- a string starting
+ power := power * base; -- with the right hand
+ end loop ; -- side.
+
+ -- return result and add sign if required
+ if int < 0 then
+ return '-'& temp(1 to len);
+ else
+ return temp(1 to len);
+ end if;
+end function int_to_str;
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
+function AdcBits (Bits : integer) return integer is
+variable Temp : integer;
+begin
+ if (Bits = 12) then
+ Temp := 12;
+ elsif (Bits = 14) then
+ Temp := 16;
+ elsif (Bits = 16) then
+ Temp := 16;
+ end if;
+return Temp;
+end function AdcBits;
+
+component AdcClock is
+ generic (
+ C_BufioLoc : string := C_BufioLoc;
+ C_BufrLoc : string := C_BufrLoc;
+ C_AdcBits : integer := C_AdcBits;
+ C_StatTaps : integer := C_StatTaps
+ );
+ port (
+ BitClk : in std_logic;
+ BitClkRst : in std_logic;
+ BitClkEna : in std_logic;
+ BitClkReSync : in std_logic;
+ BitClkDivReset : in std_logic;
+ BitClk_MonClkOut : out std_logic; -- CLK output
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input
+ BitClkAlignWarn : out std_logic;
+ BitClkInvrtd : out std_logic;
+ BitClkDone : out std_logic
+ );
+end component;
+
+component AdcFrame is
+ generic (
+ C_AdcBits : integer;
+ C_AdcWireInt : integer;
+ C_FrmPattern : string
+ );
+ port (
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT
+ FrmClkRst : in std_logic;
+ FrmClkEna : in std_logic;
+ FrmClk : in std_logic;
+ FrmClkDiv : in std_logic;
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.
+ FrmClkReSync : in std_logic;
+ FrmClkBitSlip_p : out std_logic;
+ FrmClkBitSlip_n : out std_logic;
+ FrmClkSwapMux : out std_logic;
+ FrmClkMsbRegEna : out std_logic;
+ FrmClkLsbRegEna : out std_logic;
+ FrmClkReSyncOut : out std_logic;
+ FrmClkDat : out std_logic_vector(15 downto 0);
+ FrmClkSyncWarn : out std_logic;
+ Frame_out : out std_logic;
+ testOK : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component AdcData is
+ generic (
+ C_AdcBits : integer := C_AdcBits; -- Can be 12, 14 or 16
+ C_AdcBytOrBitMode : integer := 1; -- 1 = BIT mode, 0 = BYTE mode,
+ C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
+ C_AdcWireInt : integer := C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.
+ );
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatBitSlip_p : in std_logic;
+ DatBitSlip_n : in std_logic;
+ DatSwapMux : in std_logic;
+ DatMsbRegEna : in std_logic;
+ DatLsbRegEna : in std_logic;
+ DatReSync : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+attribute keep : string;
+
+-- Constants
+constant Low : std_logic := '0';
+constant High : std_logic := '1';
+-- Signals
+signal IntIdlyCtrlRdy : std_logic := '0';
+signal IntRst0 : std_logic := '0';
+signal IntRst : std_logic := '0';
+signal IntEna_d : std_logic := '0';
+signal IntEna : std_logic := '0';
+--
+signal IntBitClkDone : std_logic := '0';
+signal IntClk : std_logic := '0';
+signal IntClkDiv : std_logic := '0';
+attribute keep of IntClkDiv : signal is "TRUE";
+signal IntClkBitSlip_p : std_logic := '0';
+signal IntClkBitSlip_n : std_logic := '0';
+signal IntClkSwapMux : std_logic := '0';
+signal IntClkMsbRegEna : std_logic := '0';
+signal IntClkLsbRegEna : std_logic := '0';
+signal IntFrmClkReSyncOut : std_logic := '0';
+signal IntDataOut : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');
+signal IntDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');
+-- Attributes
+attribute LOC : string;
+-----------------------------------------------------------------------------------------------
+--
+signal AdcBitClkAlgnWrn_S : std_logic := '0';
+signal AdcBitClkInvrtd_S : std_logic := '0';
+signal adcfrmsyncwrn_S : std_logic := '0';
+signal AdcIdlyCtrlRdy_S : std_logic := '0';
+signal testOK_S : std_logic := '0';
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal AdcReSync_S : std_logic := '0';
+signal slipoccurred_S : std_logic := '0';
+signal slipsoccurred_S : std_logic := '0';
+signal slipcounter_S : integer range 0 to 255 := 0;
+signal IntBitClkDone_S : std_logic := '0';
+signal ClockResync_S : std_logic := '0';
+signal ClockResync0_S : std_logic := '0';
+
+signal IntEna_S : std_logic := '0';
+signal IntRst_S : std_logic := '0';
+signal frame_S : std_logic := '0';
+signal reset_clockdiv_S : std_logic := '0';
+
+signal AdcData_negedge : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+signal AdcDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+
+
+-- Attributes
+attribute keep of reset_clockdiv_S : signal is "TRUE";
+
+begin
+
+AdcClkDiv <= IntClkDiv;
+--AdcDataOut <= IntDataOut;
+
+--process(IntClkDiv)
+--begin
+-- if falling_edge(IntClkDiv) then
+-- AdcData_negedge <= IntDataOut;
+-- end if;
+--end process;
+
+process(IntClkDiv)
+begin
+ if rising_edge(IntClkDiv) then
+ IntDataOut_S <= IntDataOut;
+ end if;
+end process;
+
+process(AdcDataClkNot)
+begin
+ if rising_edge(AdcDataClkNot) then
+ AdcData_negedge <= IntDataOut_S;
+ end if;
+end process;
+
+process(AdcDataClk)
+begin
+ if rising_edge(AdcDataClk) then
+ AdcDataOut <= AdcDataOut_S;
+ AdcDataOut_S <= AdcData_negedge;
+ end if;
+end process;
+
+
+-----------------------------------------------------------------------------------------------
+-- IDELAYCTRL
+-- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole
+-- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.
+-- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL
+-- component is needed.
+-- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and
+-- enable for each ADC block.
+-- Don not forget to LOC the IDELAYCTRL components down.
+-----------------------------------------------------------------------------------------------
+Gen_0 : if C_AdcUseIdlyCtrl = 0 generate
+ AdcIdlyCtrlRdy_S <= High;
+end generate Gen_0;
+Gen_1 : if C_AdcUseIdlyCtrl = 1 generate
+attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;
+begin
+ AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL
+ port map (REFCLK => SysRefClk, RST => reset_clockdiv_S , RDY => AdcIdlyCtrlRdy_S);--peter AdcIntrfcRst
+end generate Gen_1;
+AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;
+-- IntRst and IntEna are the reset and enable signals to be used in the interafce.
+-- they are generated from the incomming system enable and reset.
+
+AdcToplevel_I_Fdpe_Rst : FDPE
+ generic map (INIT => '1')
+ port map (C => IntClkDiv, CE => High, PRE => reset_clockdiv_S, D => Low, Q => IntRst);--peter AdcIntrfcRst
+
+
+
+AdcToplevel_I_Fdce_Ena_0 : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => High, Q => IntEna_d);
+AdcToplevel_I_Fdce_Ena_1 : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => High, CLR => IntRst, D => IntEna_d, Q => IntEna);
+-----------------------------------------------------------------------------------------------
+-- C_AdcChnls = c
+-- C_AdcWireInt = w
+-- C_AdcBits = b
+-----------------------------------------------------------------------------------------------
+-- BIT CLOCK
+-- IntClk and IntClkDiv are the clock to be used in the interface.
+-----------------------------------------------------------------------------------------------
+-- There is no IBUFGDS used on this level of the design.
+-- The IBUFGDS can be found in the AdcIo level.
+-- That is this the reason why the DCLK_n is not used here.
+-- At the AdcIo level the DCLK_n output is connected to GND.
+AdcToplevel_I_AdcClock : AdcClock -- entity AdcClock.AdcClock
+generic map (
+ C_BufioLoc => C_BufioLoc, -- string
+ C_BufrLoc => C_BufrLoc, -- string
+ C_AdcBits => C_AdcBits, -- integer
+ C_StatTaps => C_StatTaps -- integer
+ )
+port map (
+ BitClk => DCLK_p, -- in
+ BitClkRst => IntRst, -- in
+ BitClkEna => '1', -- IntEna_S, -- in
+ BitClkReSync => ClockResync_S, -- AdcReSync_S, -- in
+ BitClkDivReset => reset_clockdiv_S,
+ BitClk_MonClkOut => IntClk, -- out -->--|---->----
+ BitClk_MonClkIn => IntClk, -- in --<--|
+ BitClk_RefClkOut => IntClkDiv, -- out -->----|-->----
+ BitClk_RefClkIn => IntClkDiv, -- in --<----|
+ BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out
+ BitClkInvrtd => AdcBitClkInvrtd_S, -- out
+ BitClkDone => IntBitClkDone -- out Enables the AdcFrame block.
+);
+AdcBitClkDone <= IntBitClkDone; -- IntBitClkDone_S;
+AdcBitClkInvrtd <= AdcBitClkInvrtd_S;
+AdcBitClkAlgnWrn <= AdcBitClkAlgnWrn_S;
+-----------------------------------------------------------------------------------------------
+-- WORD / FRAME CLOCK
+-----------------------------------------------------------------------------------------------
+AdcToplevel_I_AdcFrame : AdcFrame -- entity AdcFrame_Lib.AdcFrame
+generic map (
+ C_AdcBits => C_AdcBits, -- integer;
+ C_AdcWireInt => C_AdcWireInt, -- integer;
+ C_FrmPattern => C_FrmPattern -- string -- 1 or 2-wire, 12 or 16(14)-bit
+)
+port map (
+ FrmClk_n => FCLK_n, -- in input n from IBUFDS_DIFF_OUT
+ FrmClk_p => FCLK_p, -- in input p from IBUFDS_DIFF_OUT
+ FrmClkRst => IntRst_S, -- in
+ FrmClkEna => IntEna_S, -- in
+ FrmClk => IntClk, -- in
+ FrmClkDiv => IntClkDiv, -- in
+ FrmClkDone => IntBitClkDone, -- IntBitClkDone_S, -- in From AdcClock done.
+ FrmClkReSync => AdcReSync_S, -- in
+ FrmClkBitSlip_p => IntClkBitSlip_p, -- out
+ FrmClkBitSlip_n => IntClkBitSlip_n, -- out
+ FrmClkSwapMux => IntClkSwapMux, -- out
+ FrmClkMsbRegEna => IntClkMsbRegEna, -- out
+ FrmClkLsbRegEna => IntClkLsbRegEna, -- out
+ FrmClkReSyncOut => IntFrmClkReSyncOut, -- out
+ FrmClkDat => open, -- out
+ FrmClkSyncWarn => AdcFrmSyncWrn_S, -- out
+ Frame_out => frame_S,
+ testOK => testOK_S,
+ testword0 => testword0_S
+);
+adcfrmsyncwrn <= adcfrmsyncwrn_S;
+testOK <= testOK_S;
+-----------------------------------------------------------------------------------------------
+-- DATA INPUTS
+-- Default the interface is set in BYTE and MSB first mode.
+-- This is coded in the AdcData level and can be mnodified if wanted.
+-- Enable the generics and all selection possibilities are available.
+-----------------------------------------------------------------------------------------------
+Gen_2 : for cw in ((C_AdcChnls/2)*C_AdcWireInt)-1 downto 0 generate
+-- assert false
+-- report int_to_str((32*((cw+1)+(p*C_AdcChnls))),10)
+-- severity note;
+ AdcToplevel_I_AdcData : AdcData -- entity AdcData.AdcData
+ generic map (
+ C_AdcBits => C_AdcBits, -- Can be 12, 14 or 16
+ C_AdcWireInt => C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.
+ )
+ port map (
+ DatD0_n => DATA_n(cw*2), -- in
+ DatD0_p => DATA_p(cw*2), -- in
+ DatD1_n => DATA_n((cw*2)+1), -- in
+ DatD1_p => DATA_p((cw*2)+1), -- in
+ DatClk => IntClk, -- in
+ DatClkDiv => IntClkDiv, -- in
+ DatRst => IntRst_S, -- in
+ DatEna => IntEna_S, -- in
+ DatDone => IntBitClkDone, -- IntBitClkDone_S, -- in
+ DatBitSlip_p => IntClkBitSlip_p, -- in
+ DatBitSlip_n => IntClkBitSlip_n, -- in
+ DatSwapMux => IntClkSwapMux, -- in
+ DatMsbRegEna => IntClkMsbRegEna, -- in
+ DatLsbRegEna => IntClkLsbRegEna, -- in
+ DatReSync => IntFrmClkReSyncOut, -- in
+ DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)
+ );
+
+
+--AdcDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt)) <= IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt));
+
+
+
+end generate Gen_2;
+
+
+process(IntClkDiv)
+begin
+ if (rising_edge(IntClkDiv)) then
+ AdcReSync_S <= AdcReSync;
+ end if;
+end process;
+
+-- reset_clockdiv_S <= '1' when (frame_S='0') and (reset_clockdiv0_S='1') else '0';
+reset_clockdiv : FDPE
+ generic map (INIT => '1')
+ port map (C => frame_S, CE => High, PRE => AdcIntrfcRst, D => Low, Q => reset_clockdiv_S);
+
+--process(SysRefClk)
+--begin
+-- if (rising_edge(SysRefClk)) then
+-- if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then
+-- reset_clockdiv0_S <= '1';
+-- elsif frame_S='1' then
+-- reset_clockdiv0_S <= '0';
+-- end if;
+-- end if;
+--end process;
+
+--process(IntClkDiv,reset_clockdiv0_S)
+--variable counter_V : integer range 0 to 3 := 0;
+--begin
+-- if reset_clockdiv0_S='1' then
+-- ClockResync_S <= '0';
+-- counter_V := 0;
+-- elsif (rising_edge(IntClkDiv)) then
+-- if counter_V<3 then
+-- counter_V := counter_V+1;
+-- ClockResync_S <= '1';
+-- else
+-- ClockResync_S <= '0';
+-- end if;
+-- end if;
+--end process;
+ClockResync_S <= ClockResync0_S;
+process(IntClkDiv,AdcIntrfcRst) -- reset_clockdiv_S)
+begin
+-- if reset_clockdiv_S='1' then
+ if AdcIntrfcRst='1' then
+ slipoccurred_S <= '0';
+ slipsoccurred_S <= '0';
+ slipcounter_S <= 0;
+ ClockResync0_S <= '0';
+ IntBitClkDone_S <= '0';
+ IntEna_S <= '0';
+ IntRst_S <= '0';
+ ADCs_ready <= '0';
+ elsif (rising_edge(IntClkDiv)) then
+ if (IntBitClkDone='0') or (ClockResync_S='1') then
+ slipcounter_S <= 0;
+ slipoccurred_S <= '0';
+ slipsoccurred_S <= '0';
+ ClockResync0_S <= '0';
+ IntBitClkDone_S <= '0';
+ IntEna_S <= '0';
+ IntRst_S <= '0';
+ ADCs_ready <= '0';
+ elsif slipcounter_S<2 then
+ slipcounter_S <= slipcounter_S+1;
+ ClockResync0_S <= '0';
+ slipoccurred_S <= '0';
+ slipsoccurred_S <= '0';
+ IntBitClkDone_S <= '0';
+ IntEna_S <= '0';
+ IntRst_S <= '0';
+ elsif slipcounter_S<31 then
+ slipcounter_S <= slipcounter_S+1;
+ ClockResync0_S <= '0';
+ slipoccurred_S <= '0';
+ slipsoccurred_S <= '0';
+ IntBitClkDone_S <= '0';
+ IntEna_S <= '0';
+ IntRst_S <= '0';
+ elsif slipcounter_S<33 then
+ slipcounter_S <= slipcounter_S+1;
+ IntRst_S <= '1';
+ elsif slipcounter_S<63 then
+ slipcounter_S <= slipcounter_S+1;
+ IntRst_S <= '0';
+ elsif slipcounter_S<95 then
+ slipcounter_S <= slipcounter_S+1;
+ IntEna_S <= '1';
+ elsif slipcounter_S<111 then
+ slipcounter_S <= slipcounter_S+1;
+ IntBitClkDone_S <= '1';
+ elsif slipcounter_S<254 then
+ slipcounter_S <= slipcounter_S+1;
+ IntBitClkDone_S <= '1';
+ if (IntClkBitSlip_p='1') then
+ if slipoccurred_S='1' then
+ slipsoccurred_S <= '1';
+ end if;
+ slipoccurred_S <= '1';
+ end if;
+ if (IntClkBitSlip_n='1') then
+ slipsoccurred_S <= '1';
+ slipoccurred_S <= '1';
+ end if;
+ elsif slipcounter_S<255 then
+ slipcounter_S <= slipcounter_S+1;
+-- if (slipsoccurred_S='1') or (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkInvrtd_S='0') or (AdcBitClkAlgnWrn_S='1') then
+ if (slipsoccurred_S='1') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then
+-- if (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then
+ ClockResync0_S <= '1';
+ else
+ ADCs_ready <= '1';
+ end if;
+ else
+ ClockResync0_S <= '0';
+ end if;
+ end if;
+end process;
+
+
+
+
+-----------------------------------------------------------------------------------------------
+--
+
+--1000
+testword0(0) <= IntRst;
+testword0(1) <= AdcReSync_S;
+testword0(2) <= AdcBitClkAlgnWrn_S;
+testword0(3) <= AdcBitClkInvrtd_S;
+
+--0001
+testword0(4) <= IntBitClkDone;
+testword0(5) <= IntClkBitSlip_p;
+testword0(6) <= IntClkBitSlip_n;
+testword0(7) <= IntClkSwapMux;
+
+--0011
+testword0(8) <= IntRst_S; -- IntClkMsbRegEna;
+testword0(9) <= IntEna_S; -- IntClkLsbRegEna;
+testword0(10) <= IntFrmClkReSyncOut;
+testword0(11) <= AdcFrmSyncWrn_S;
+
+--1000
+testword0(12) <= AdcIntrfcRst;
+testword0(13) <= testOK_S;
+testword0(14) <= Frame_S;
+testword0(15) <= AdcIdlyCtrlRdy_S;
+
+testword0(16) <= AdcReSync_S;
+testword0(17) <= slipoccurred_S;
+testword0(18) <= slipsoccurred_S;
+testword0(19) <= IntBitClkDone_S;
+testword0(20) <= ClockResync_S;
+testword0(21) <= ClockResync0_S;
+testword0(22) <= reset_clockdiv_S;
+testword0(23) <= reset_clockdiv_S;
+
+
+-- testword0(23 downto 16) <= testword0_S(7 downto 0);
+
+testword0(35 downto 24) <= (others => '0');
+
+end AdcToplevel_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd b/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd
new file mode 100644
index 0000000..0152478
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd
@@ -0,0 +1,293 @@
+---------------------------------------------------------------------------------------------
+-- © Copyright 2011, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+---------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx Inc.
+-- \ \ \/ Version:
+-- \ \ Filename: DoubleNibbleDetect.vhd
+-- / / Date Created: 16 March, 2011
+-- /___/ /\ Date Last Modified: 16 March, 2011
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: defossez
+-- Entity Name: DoubleNibbleDetect
+-- Purpose: Create a on-off signal that already reacts at the combinatorial input.
+-- Tools: ISE_13.1
+-- Limitations: none
+--
+-- Revision History:
+-- Rev.
+--
+------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+---------------------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+ use UNISIM.vcomponents.all;
+---------------------------------------------------------------------------------------------
+-- Entity pin description
+---------------------------------------------------------------------------------------------
+-- Clock : Clock for the design.
+-- RstIn : Reset input. Resets the necessary logic at startup.
+-- Final : This circuit checks a nibble (4-bit) for appearing twice, when for rotations or
+-- slips are made, teh fifth ossurence resets the circuit. this is signalled ouside
+-- so that a upper layer of design can take action.
+-- DataIn : Nibble input.
+-- DataOut : Corrected nibble output.
+---------------------------------------------------------------------------------------------
+entity DoubleNibbleDetect is
+ port (
+ Clock : in std_logic;
+ RstIn : in std_logic;
+ Final : out std_logic;
+ DataIn : in std_logic_vector(3 downto 0);
+ DataOut : out std_logic_vector(3 downto 0)
+ );
+end DoubleNibbleDetect;
+---------------------------------------------------------------------------------------------
+-- Architecture section
+---------------------------------------------------------------------------------------------
+architecture DoubleNibbleDetect_struct of DoubleNibbleDetect is
+---------------------------------------------------------------------------------------------
+-- Component Instantiation
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+---------------------------------------------------------------------------------------------
+-- Functions
+-- Constants
+constant Low : std_logic := '0';
+constant High : std_logic := '1';
+-- Signals
+signal IntRegOutIn : std_logic_vector(3 downto 0);
+signal IntAddr : std_logic_vector(4 downto 0);
+signal IntSrlOut : std_logic_vector(3 downto 0);
+--
+signal IntRegOutIn_s : std_logic_vector(3 downto 0);
+signal IntAddr_s : std_logic_vector(4 downto 0);
+signal IntSrlOut_s : std_logic_vector(3 downto 0);
+signal DataOut_s : std_logic_vector(3 downto 0);
+--
+signal IntEqu : std_logic;
+signal IntEqu_d : std_logic;
+signal IntPulse : std_logic;
+signal IntSlipCnt : std_logic_vector(3 downto 0);
+signal IntSlipCnt_d : std_logic_vector(3 downto 0);
+signal IntSlipCntRst : std_logic;
+signal IntEquCnt : std_logic_vector(3 downto 0);
+signal IntEquCnt_d : std_logic_vector(3 downto 0);
+--
+signal IntRstSet : std_logic;
+signal IntRstIn : std_logic;
+signal IntRstFf_d : std_logic_vector(7 downto 0) := X"00";
+signal IntRstIn_d : std_logic;
+--
+signal IntAddrSet : std_logic_vector(3 downto 0);
+-- Attributes
+attribute IOB : string;
+attribute HBLKNM : string;
+---------------------------------------------------------------------------------------------
+begin
+---------------------------------------------------------------------------------------------
+-- Delay the start of the ciruit after reset.
+---------------------------------------------------------------------------------------------
+IntRstIn <= RstIn or IntRstSet;
+--
+Gen_Rst : for n in 0 to 7 generate
+ Reg_Lsb : if n = 0 generate
+ DbleNibl_I_Fdse : FDSE -- Synchronous set
+ generic map (INIT => '0')
+ port map (D => Low, CE => High, C => Clock, S => IntRstSet, Q => IntRstFf_d(n));
+ end generate Reg_Lsb;
+ Reg_MidL : if n > 0 and n <= 5 generate
+ DbleNibl_I_Fdse : FDSE -- Synchronous set
+ generic map (INIT => '0')
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstSet,
+ Q => IntRstFf_d(n));
+ end generate Reg_MidL;
+ Reg_MidH : if n = 6 generate
+ DbleNibl_I_Fdse : FDSE -- Synchronous set
+ generic map (INIT => '0')
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,
+ Q => IntRstFf_d(n));
+ end generate Reg_MidH;
+ Reg_Msb : if n = 7 generate
+ DbleNibl_I_Fdse : FDSE -- Synchronous set
+ generic map (INIT => '0')
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,
+ Q => IntRstFf_d(n));
+ --
+ IntRstIn_d <= IntRstFf_d(n);
+ end generate Reg_Msb;
+end generate Gen_Rst;
+---------------------------------------------------------------------------------------------
+-- Data path registers
+---------------------------------------------------------------------------------------------
+Gen_Reg : for n in 3 downto 0 generate
+ In_I_Fdce : FDCE
+ generic map (INIT => '0')
+ port map (D => DataIn(n), CE => High, C => Clock, CLR => IntRstIn_d,
+ Q => IntRegOutIn_s(n));
+IntRegOutIn(n) <= IntRegOutIn_s(n); -- after 100 ps;
+ DbleNibl_I_Srlc32e : SRLC32E
+ generic map (INIT => X"00000000")
+ port map (D => IntRegOutIn(n), A => IntAddr, CE => High, CLK => Clock, Q31 => open,
+ Q => IntSrlOut_s(n));
+IntSrlOut(n) <= IntSrlOut_s(n); -- after 100 ps;
+ Out_I_Fdce : FDCE
+ generic map (INIT => '0')
+ port map (D => IntSrlOut(n), CE => High, C => Clock, CLR => IntRstIn_d,
+ Q => DataOut_s(n));
+DataOut(n) <= DataOut_s(n); -- after 100 ps;
+end generate Gen_Reg;
+---------------------------------------------------------------------------------------------
+-- Compare present and past for equality.
+---------------------------------------------------------------------------------------------
+IntEqu <= '1' when (DataIn = IntRegOutIn) else '0';
+-----------------------------------------------------------------------------------------------
+-- Generate the SRL addresses
+---------------------------------------------------------------------------------------------
+IntAddr(3 downto 0) <= "0100" when (IntEquCnt_d = "0000" and IntSlipCnt_d = "0000") else
+ "0011" when (IntEquCnt_d = "0001" and IntSlipCnt_d = "0111") else
+ "0010" when (IntEquCnt_d = "0011" and IntSlipCnt_d = "0110") else
+ "0001" when (IntEquCnt_d = "0010" and IntSlipCnt_d = "0010") else
+ "0000" when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0011") else
+ "0100" when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001");
+IntAddr(4) <= Low;
+--IntRstSet <= '1' when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001") else '0';
+IntRstSet <= '1' when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0000" and IntPulse = '1')
+ else '0';
+Final <= IntRstSet;
+---------------------------------------------------------------------------------------------
+-- Equal/Double nibble detect counters
+---------------------------------------------------------------------------------------------
+IntPulse <= IntEqu or IntEqu_d;
+--
+DbleNibl_I_Fdce : FDCE -- Asynchronous reset
+ generic map (INIT => '0')
+ port map (D => High, CE => IntEqu, C => Clock, CLR => IntSlipCntRst, Q => IntEqu_d);
+-- When a double nibble is detected shift the pulse over four taps and reset the shifter
+-- at the fifth tap.
+---------------------------------------------------------------------------------------------
+-- Slip Counter
+-- When equality is detected, this counter counts till a preset number and then resets.
+---------------------------------------------------------------------------------------------
+IntSlipCntRst <= '1' when (IntRstIn_d = '1' or IntSlipCnt_d = "0101") else '0';
+--
+Gen_SlipCnt : for n in 3 downto 0 generate
+ attribute HBLKNM of Cnt_I_Fdre : label is "SlipCnt";
+ attribute IOB of Cnt_I_Fdre : label is "FALSE";
+ begin
+ Cnt_I_Fdre : FDRE -- Synchronous reset
+ generic map (INIT => '0')
+ port map (D => IntSlipCnt(n), CE => IntPulse, C => Clock, R => IntSlipCntRst,
+ Q => IntSlipCnt_d(n));
+end generate Gen_SlipCnt;
+-- These ar the "SlipCnt" states, orginized in Gray mode
+DbleNibl_SlipCnt_PROCESS : process (IntSlipCnt_d)
+begin
+ case IntSlipCnt_d(3 downto 0) is
+ when "0000" => IntSlipCnt <= "0001"; -- after 100 ps;
+ when "0001" => IntSlipCnt <= "0011"; -- after 100 ps;
+ when "0011" => IntSlipCnt <= "0010"; -- after 100 ps;
+ when "0010" => IntSlipCnt <= "0110"; -- after 100 ps;
+ when "0110" => IntSlipCnt <= "0111"; -- after 100 ps;
+ when "0111" => IntSlipCnt <= "0101"; -- after 100 ps;
+ when "0101" => IntSlipCnt <= "0000"; -- after 100 ps;
+ when others => IntSlipCnt <= "0000"; -- after 100 ps;
+ end case;
+end process;
+---------------------------------------------------------------------------------------------
+-- Equ Counter
+-- Count how many times a double nibble is detected.
+-- becuase a nibble of data is taken, it can only be four times.
+-- When equality is detected for the fift time the system is reset.
+---------------------------------------------------------------------------------------------
+Gen_EquCnt : for n in 3 downto 0 generate
+ attribute HBLKNM of Equ_I_Fdre : label is "EquCnt";
+ attribute IOB of Equ_I_Fdre : label is "FALSE";
+ begin
+ Equ_I_Fdre : FDRE -- Synchronous reset
+ generic map (INIT => '0')
+ port map (D => IntEquCnt(n), CE => IntEqu, C => Clock, R => IntRstIn_d,
+ Q => IntEquCnt_d(n));
+end generate Gen_EquCnt;
+--
+DbleNibl_EquCnt_PROCESS : process (IntEquCnt_d)
+begin
+ case IntEquCnt_d(3 downto 0) is
+ when "0000" => IntEquCnt <= "0001"; -- after 100 ps;
+ when "0001" => IntEquCnt <= "0011"; -- after 100 ps;
+ when "0011" => IntEquCnt <= "0010"; -- after 100 ps;
+ when "0010" => IntEquCnt <= "0110"; -- after 100 ps;
+ when "0110" => IntEquCnt <= "0111"; -- after 100 ps;
+ when "0111" => IntEquCnt <= "0101"; -- after 100 ps;
+ when "0101" => IntEquCnt <= "0100"; -- after 100 ps;
+ when "0100" => IntEquCnt <= "1100"; -- after 100 ps;
+ when "1100" => IntEquCnt <= "1101"; -- after 100 ps;
+ when "1101" => IntEquCnt <= "1111"; -- after 100 ps;
+ when "1111" => IntEquCnt <= "1110"; -- after 100 ps;
+ when "1110" => IntEquCnt <= "1010"; -- after 100 ps;
+ when "1010" => IntEquCnt <= "1011"; -- after 100 ps;
+ when "1011" => IntEquCnt <= "1001"; -- after 100 ps;
+ when "1001" => IntEquCnt <= "1000"; -- after 100 ps;
+ when "1000" => IntEquCnt <= "0000"; -- after 100 ps;
+ when others => IntEquCnt <= "0000"; -- after 100 ps;
+ end case;
+end process;
+--
+---------------------------------------------------------------------------------------------
+end DoubleNibbleDetect_struct;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd b/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd
new file mode 100644
index 0000000..dd77e92
--- /dev/null
+++ b/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd
@@ -0,0 +1,132 @@
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2008 - 2009, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version:
+-- \ \ Filename: GenPulse.vhd
+-- / / Date Last Modified:
+-- /___/ /\ Date Created: 08 Mar 08
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device:
+-- Author: Marc Defossez
+-- Entity Name: GenPulse
+-- Purpose: Generate a clock cycle wide pulse from a wide high input
+-- Tools: ISE_10.1
+-- Limitations: none
+--
+-- Revision History:
+-- Rev.
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------------------------
+entity GenPulse is
+ port (
+ Clk : in std_logic;
+ Ena : in std_logic;
+ SigIn : in std_logic;
+ SigOut : out std_logic
+ );
+end GenPulse;
+
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture GenPulse_struct of GenPulse is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Functions
+-- Constants
+-- constant Low : std_logic := '0';
+-- constant High : std_logic := '1';
+-- Signals
+signal IntSigOut : std_logic;
+signal IntSigIn_n : std_logic;
+signal IntSigClr : std_logic;
+-- Attributes
+-----------------------------------------------------------------------------------------------
+--
+begin
+--
+GenPulse_I_Fdce_1 : FDCE
+ generic map (INIT => '0')
+ port map (D => SigIn, C => Clk, CLR => IntSigClr, CE => Ena, Q => IntSigOut);
+--
+IntSigIn_n <= not SigIn;
+--
+GenPulse_I_Fdce_2 : FDCE
+ generic map (INIT => '0')
+ port map (D => IntSigOut, C => Clk, CLR => IntSigIn_n, CE => IntSigOut, Q => IntSigClr);
+--
+SigOut <= IntSigOut;
+--
+-----------------------------------------------------------------------------------------------
+end GenPulse_struct;
+--
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/FEE_ADCinput_module.vhd b/FEE_ADC32board/modules/FEE_ADCinput_module.vhd
new file mode 100644
index 0000000..05c8721
--- /dev/null
+++ b/FEE_ADC32board/modules/FEE_ADCinput_module.vhd
@@ -0,0 +1,961 @@
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 23-9-2014
+-- Module Name: FEE_ADCinput_module
+-- Description: Module to convert serial data from ADCs (LTM9009-14) to parallel
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_ADCinput_module
+-- Module to convert serial data from ADCs (LTM9009-14) to parallel
+-- Based on Xilinx serial ADC reference design
+--
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock200MHz : 200MHz clock input for IODELAYCTRL
+-- reset : reset ADCs
+-- ADCs_enable : enable signal for ADCs
+-- AD*_P : serial data links from ADCs, LVDS positive
+-- AD*_N : serial data links from ADCs, LVDS negative
+-- DCO*_P : data clock from ADCs, LVDS positive
+-- DCO*_N : data clock from ADCs, LVDS negative
+-- FRA*_P : frame start signals from ADCs, LVDS positive
+-- FRA*_N : frame start signals from ADCs, LVDS negative
+--
+-- Outputs:
+-- ADC_clk : clock for parallel ADC data
+-- adcdata : parallel ADC data
+--
+-- Components:
+-- AdcToplevel : top-level module from Xilinx serial ADC reference design
+--
+----------------------------------------------------------------------------------
+
+entity FEE_ADCinput_module is
+ port (
+ clock200MHz : in std_logic;
+ reset : in std_logic;
+ ADCs_enable : in std_logic;
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+ ADC_clk : out std_logic;
+ ADCs_ready : out std_logic;
+ adcdata : out array_adc_type
+ );
+end FEE_ADCinput_module;
+
+architecture Behavioral of FEE_ADCinput_module is
+
+
+
+component AdcToplevel is
+ generic (
+ C_AdcChnls : integer := 4; -- Number of ADC in a package
+ C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc : string := "BUFIODQS_X1Y15";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_AdcBits : integer := 16;
+ C_StatTaps : integer := 16;
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";
+ C_FrmPattern : string := "0000000000001111" -- "0000000011110000" -- Read above text!
+ );
+ port (
+ DCLK_p : in std_logic;
+ DCLK_n : in std_logic; -- Not used.
+ FCLK_p : in std_logic;
+ FCLK_n : in std_logic;
+ DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ -- application connections
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
+ AdcIntrfcRst : in std_logic;
+ AdcIntrfcEna : in std_logic;
+ AdcReSync : in std_logic;
+ AdcFrmSyncWrn : out std_logic;
+ AdcBitClkAlgnWrn : out std_logic;
+ AdcBitClkInvrtd : out std_logic;
+ AdcBitClkDone : out std_logic;
+ AdcIdlyCtrlRdy : out std_logic;
+
+ AdcClkDiv : out std_logic;
+ AdcDataClk : in std_logic;
+ AdcDataClkNot : in std_logic;
+ AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+ ADCs_ready : out std_logic;
+ testOK : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_clockbuf80MHz
+ port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic
+ );
+end component;
+
+function TermOrNot (Term : integer) return boolean is
+begin
+ if (Term = 0) then
+ return FALSE;
+ else
+ return TRUE;
+ end if;
+end TermOrNot;
+
+constant C_OnChipLvdsTerm : integer := 1;
+
+--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0);
+
+signal adcdata1458_P : adcdataserial_type;
+signal adcdata1458_N : adcdataserial_type;
+signal adcdata2367_P : adcdataserial_type;
+signal adcdata2367_N : adcdataserial_type;
+
+signal DCOA1_P_S : std_logic;
+signal DCOA1_N_S : std_logic;
+signal DCOA2_P_S : std_logic;
+signal DCOA2_N_S : std_logic;
+signal DCOA3_P_S : std_logic;
+signal DCOA3_N_S : std_logic;
+signal DCOA4_P_S : std_logic;
+signal DCOA4_N_S : std_logic;
+
+signal DCOB1_P_S : std_logic;
+signal DCOB1_N_S : std_logic;
+signal DCOB2_P_S : std_logic;
+signal DCOB2_N_S : std_logic;
+signal DCOB3_P_S : std_logic;
+signal DCOB3_N_S : std_logic;
+signal DCOB4_P_S : std_logic;
+signal DCOB4_N_S : std_logic;
+
+signal FRA1_P_S : std_logic;
+signal FRA1_N_S : std_logic;
+signal FRA2_P_S : std_logic;
+signal FRA2_N_S : std_logic;
+signal FRA3_P_S : std_logic;
+signal FRA3_N_S : std_logic;
+signal FRA4_P_S : std_logic;
+signal FRA4_N_S : std_logic;
+
+signal FRB1_P_S : std_logic;
+signal FRB1_N_S : std_logic;
+signal FRB2_P_S : std_logic;
+signal FRB2_N_S : std_logic;
+signal FRB3_P_S : std_logic;
+signal FRB3_N_S : std_logic;
+signal FRB4_P_S : std_logic;
+signal FRB4_N_S : std_logic;
+
+signal AdcFrmSyncWrnA_S : std_logic_vector(0 to 3);
+signal AdcBitClkAlgnWrnA_S : std_logic_vector(0 to 3);
+signal AdcBitClkDoneA_S : std_logic_vector(0 to 3);
+signal AdcIdlyCtrlRdyA_S : std_logic_vector(0 to 3);
+signal AdcBitClkInvrtdA_S : std_logic_vector(0 to 3);
+signal adcclockA_S : std_logic_vector(0 to 3);
+signal AdcDataOutA_S : AdcDataOut_type;
+
+signal AdcFrmSyncWrnB_S : std_logic_vector(0 to 3);
+signal AdcBitClkAlgnWrnB_S : std_logic_vector(0 to 3);
+signal AdcBitClkDoneB_S : std_logic_vector(0 to 3);
+signal AdcIdlyCtrlRdyB_S : std_logic_vector(0 to 3);
+signal AdcBitClkInvrtdB_S : std_logic_vector(0 to 3);
+signal adcclockB_S : std_logic_vector(0 to 3);
+signal AdcDataOutB_S : AdcDataOut_type;
+
+signal ADCs_ready_S : std_logic_vector(0 to 7);
+
+signal adcdata0_S : array_adc_type;
+signal adcdata1_S : array_adc_type;
+
+signal ADC_clk_S : std_logic;
+signal ADC_clknot_S : std_logic;
+
+attribute keep : string;
+attribute keep of ADC_clk_S : signal is "TRUE";
+attribute keep of ADC_clknot_S: signal is "TRUE";
+
+begin
+
+ADC_clk <= ADC_clk_S;
+ADCs_ready <= '1' when (ADCs_ready_S=x"ff") and (reset='0') else '0';
+
+
+-- ADC inputs ----------------------------------------------------------------------
+---- B and A swopped !!!
+adcdata1458_0B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD11B_P, IB => AD11B_N, O => adcdata1458_P(0)(0), OB => adcdata1458_N(0)(0));
+adcdata1458_0A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD11A_P, IB => AD11A_N, O => adcdata1458_P(0)(1), OB => adcdata1458_N(0)(1));
+adcdata1458_0B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD14B_P, IB => AD14B_N, O => adcdata1458_P(0)(2), OB => adcdata1458_N(0)(2));
+adcdata1458_0A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD14A_P, IB => AD14A_N, O => adcdata1458_P(0)(3), OB => adcdata1458_N(0)(3));
+adcdata1458_0B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD15B_P, IB => AD15B_N, O => adcdata1458_P(0)(4), OB => adcdata1458_N(0)(4));
+adcdata1458_0A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD15A_P, IB => AD15A_N, O => adcdata1458_P(0)(5), OB => adcdata1458_N(0)(5));
+adcdata1458_0B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD18B_P, IB => AD18B_N, O => adcdata1458_P(0)(6), OB => adcdata1458_N(0)(6));
+adcdata1458_0A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD18A_P, IB => AD18A_N, O => adcdata1458_P(0)(7), OB => adcdata1458_N(0)(7));
+
+adcdata2367_0B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD12B_P, IB => AD12B_N, O => adcdata2367_P(0)(0), OB => adcdata2367_N(0)(0));
+adcdata2367_0A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD12A_P, IB => AD12A_N, O => adcdata2367_P(0)(1), OB => adcdata2367_N(0)(1));
+adcdata2367_0B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD13B_P, IB => AD13B_N, O => adcdata2367_P(0)(2), OB => adcdata2367_N(0)(2));
+adcdata2367_0A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD13A_P, IB => AD13A_N, O => adcdata2367_P(0)(3), OB => adcdata2367_N(0)(3));
+adcdata2367_0B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD16B_P, IB => AD16B_N, O => adcdata2367_P(0)(4), OB => adcdata2367_N(0)(4));
+adcdata2367_0A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD16A_P, IB => AD16A_N, O => adcdata2367_P(0)(5), OB => adcdata2367_N(0)(5));
+adcdata2367_0B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD17B_P, IB => AD17B_N, O => adcdata2367_P(0)(6), OB => adcdata2367_N(0)(6));
+adcdata2367_0A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD17A_P, IB => AD17A_N, O => adcdata2367_P(0)(7), OB => adcdata2367_N(0)(7));
+
+adcdata1458_1B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD21B_P, IB => AD21B_N, O => adcdata1458_P(1)(0), OB => adcdata1458_N(1)(0));
+adcdata1458_1A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD21A_P, IB => AD21A_N, O => adcdata1458_P(1)(1), OB => adcdata1458_N(1)(1));
+adcdata1458_1B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD24B_P, IB => AD24B_N, O => adcdata1458_P(1)(2), OB => adcdata1458_N(1)(2));
+adcdata1458_1A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD24A_P, IB => AD24A_N, O => adcdata1458_P(1)(3), OB => adcdata1458_N(1)(3));
+adcdata1458_1B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD25B_P, IB => AD25B_N, O => adcdata1458_P(1)(4), OB => adcdata1458_N(1)(4));
+adcdata1458_1A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD25A_P, IB => AD25A_N, O => adcdata1458_P(1)(5), OB => adcdata1458_N(1)(5));
+adcdata1458_1B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD28B_P, IB => AD28B_N, O => adcdata1458_P(1)(6), OB => adcdata1458_N(1)(6));
+adcdata1458_1A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD28A_P, IB => AD28A_N, O => adcdata1458_P(1)(7), OB => adcdata1458_N(1)(7));
+
+adcdata2367_1B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD22B_P, IB => AD22B_N, O => adcdata2367_P(1)(0), OB => adcdata2367_N(1)(0));
+adcdata2367_1A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD22A_P, IB => AD22A_N, O => adcdata2367_P(1)(1), OB => adcdata2367_N(1)(1));
+adcdata2367_1B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD23B_P, IB => AD23B_N, O => adcdata2367_P(1)(2), OB => adcdata2367_N(1)(2));
+adcdata2367_1A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD23A_P, IB => AD23A_N, O => adcdata2367_P(1)(3), OB => adcdata2367_N(1)(3));
+adcdata2367_1B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD26B_P, IB => AD26B_N, O => adcdata2367_P(1)(4), OB => adcdata2367_N(1)(4));
+adcdata2367_1A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD26A_P, IB => AD26A_N, O => adcdata2367_P(1)(5), OB => adcdata2367_N(1)(5));
+adcdata2367_1B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD27B_P, IB => AD27B_N, O => adcdata2367_P(1)(6), OB => adcdata2367_N(1)(6));
+adcdata2367_1A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD27A_P, IB => AD27A_N, O => adcdata2367_P(1)(7), OB => adcdata2367_N(1)(7));
+
+adcdata1458_2B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD31B_P, IB => AD31B_N, O => adcdata1458_P(2)(0), OB => adcdata1458_N(2)(0));
+adcdata1458_2A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD31A_P, IB => AD31A_N, O => adcdata1458_P(2)(1), OB => adcdata1458_N(2)(1));
+adcdata1458_2B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD34B_P, IB => AD34B_N, O => adcdata1458_P(2)(2), OB => adcdata1458_N(2)(2));
+adcdata1458_2A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD34A_P, IB => AD34A_N, O => adcdata1458_P(2)(3), OB => adcdata1458_N(2)(3));
+adcdata1458_2B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD35B_P, IB => AD35B_N, O => adcdata1458_P(2)(4), OB => adcdata1458_N(2)(4));
+adcdata1458_2A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD35A_P, IB => AD35A_N, O => adcdata1458_P(2)(5), OB => adcdata1458_N(2)(5));
+adcdata1458_2B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD38B_P, IB => AD38B_N, O => adcdata1458_P(2)(6), OB => adcdata1458_N(2)(6));
+adcdata1458_2A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD38A_P, IB => AD38A_N, O => adcdata1458_P(2)(7), OB => adcdata1458_N(2)(7));
+
+adcdata2367_2B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD32B_P, IB => AD32B_N, O => adcdata2367_P(2)(0), OB => adcdata2367_N(2)(0));
+adcdata2367_2A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD32A_P, IB => AD32A_N, O => adcdata2367_P(2)(1), OB => adcdata2367_N(2)(1));
+adcdata2367_2B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD33B_P, IB => AD33B_N, O => adcdata2367_P(2)(2), OB => adcdata2367_N(2)(2));
+adcdata2367_2A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD33A_P, IB => AD33A_N, O => adcdata2367_P(2)(3), OB => adcdata2367_N(2)(3));
+adcdata2367_2B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD36B_P, IB => AD36B_N, O => adcdata2367_P(2)(4), OB => adcdata2367_N(2)(4));
+adcdata2367_2A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD36A_P, IB => AD36A_N, O => adcdata2367_P(2)(5), OB => adcdata2367_N(2)(5));
+adcdata2367_2B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD37B_P, IB => AD37B_N, O => adcdata2367_P(2)(6), OB => adcdata2367_N(2)(6));
+adcdata2367_2A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD37A_P, IB => AD37A_N, O => adcdata2367_P(2)(7), OB => adcdata2367_N(2)(7));
+
+adcdata1458_3B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD41B_P, IB => AD41B_N, O => adcdata1458_P(3)(0), OB => adcdata1458_N(3)(0));
+adcdata1458_3A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD41A_P, IB => AD41A_N, O => adcdata1458_P(3)(1), OB => adcdata1458_N(3)(1));
+adcdata1458_3B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD44B_P, IB => AD44B_N, O => adcdata1458_P(3)(2), OB => adcdata1458_N(3)(2));
+adcdata1458_3A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD44A_P, IB => AD44A_N, O => adcdata1458_P(3)(3), OB => adcdata1458_N(3)(3));
+adcdata1458_3B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD45B_P, IB => AD45B_N, O => adcdata1458_P(3)(4), OB => adcdata1458_N(3)(4));
+adcdata1458_3A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD45A_P, IB => AD45A_N, O => adcdata1458_P(3)(5), OB => adcdata1458_N(3)(5));
+adcdata1458_3B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD48B_P, IB => AD48B_N, O => adcdata1458_P(3)(6), OB => adcdata1458_N(3)(6));
+adcdata1458_3A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD48A_P, IB => AD48A_N, O => adcdata1458_P(3)(7), OB => adcdata1458_N(3)(7));
+
+adcdata2367_3B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD42B_P, IB => AD42B_N, O => adcdata2367_P(3)(0), OB => adcdata2367_N(3)(0));
+adcdata2367_3A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD42A_P, IB => AD42A_N, O => adcdata2367_P(3)(1), OB => adcdata2367_N(3)(1));
+adcdata2367_3B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD43B_P, IB => AD43B_N, O => adcdata2367_P(3)(2), OB => adcdata2367_N(3)(2));
+adcdata2367_3A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD43A_P, IB => AD43A_N, O => adcdata2367_P(3)(3), OB => adcdata2367_N(3)(3));
+adcdata2367_3B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD46B_P, IB => AD46B_N, O => adcdata2367_P(3)(4), OB => adcdata2367_N(3)(4));
+adcdata2367_3A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD46A_P, IB => AD46A_N, O => adcdata2367_P(3)(5), OB => adcdata2367_N(3)(5));
+adcdata2367_3B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD47B_P, IB => AD47B_N, O => adcdata2367_P(3)(6), OB => adcdata2367_N(3)(6));
+adcdata2367_3A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD47A_P, IB => AD47A_N, O => adcdata2367_P(3)(7), OB => adcdata2367_N(3)(7));
+
+DCOA1_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA1_P, IB => DCOA1_N, O => DCOA1_P_S);
+DCOA1_N_S <= '0';
+DCOA2_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA2_P, IB => DCOA2_N, O => DCOA2_P_S);
+DCOA2_N_S <= '0';
+DCOA3_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA3_P, IB => DCOA3_N, O => DCOA3_P_S);
+DCOA3_N_S <= '0';
+DCOA4_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA4_P, IB => DCOA4_N, O => DCOA4_P_S);
+DCOA4_N_S <= '0';
+
+DCOB1_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB1_P, IB => DCOB1_N, O => DCOB1_P_S);
+DCOB1_N_S <= '0';
+DCOB2_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB2_P, IB => DCOB2_N, O => DCOB2_P_S);
+DCOB2_N_S <= '0';
+DCOB3_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB3_P, IB => DCOB3_N, O => DCOB3_P_S);
+DCOB3_N_S <= '0';
+DCOB4_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB4_P, IB => DCOB4_N, O => DCOB4_P_S);
+DCOB4_N_S <= '0';
+
+FRA1_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA1_P, IB => FRA1_N, O => FRA1_P_S, OB => FRA1_N_S);
+FRA2_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA2_P, IB => FRA2_N, O => FRA2_P_S, OB => FRA2_N_S);
+FRA3_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA3_P, IB => FRA3_N, O => FRA3_P_S, OB => FRA3_N_S);
+FRA4_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA4_P, IB => FRA4_N, O => FRA4_P_S, OB => FRA4_N_S);
+
+
+FRB1_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB1_P, IB => FRB1_N, O => FRB1_P_S, OB => FRB1_N_S);
+FRB2_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB2_P, IB => FRB2_N, O => FRB2_P_S, OB => FRB2_N_S);
+FRB3_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB3_P, IB => FRB3_N, O => FRB3_P_S, OB => FRB3_N_S);
+FRB4_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB4_P, IB => FRB4_N, O => FRB4_P_S, OB => FRB4_N_S);
+
+
+ AdcToplevel1458_1: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X1Y14",
+ C_BufrLoc => "BUFR_X1Y7",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA1_P_S,
+ DCLK_n => DCOA1_N_S,
+ FCLK_p => FRA1_P_S,
+ FCLK_n => FRA1_N_S,
+ DATA_p => adcdata1458_P(0),
+ DATA_n => adcdata1458_n(0),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(0),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(0),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(0),
+ AdcBitClkDone => AdcBitClkDoneA_S(0),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(0),
+ AdcClkDiv => adcclockA_S(0),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(0),
+ ADCs_ready => ADCs_ready_S(0),
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_1: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X1Y13",
+ C_BufrLoc => "BUFR_X1Y6",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3"
+ )
+ port map(
+ DCLK_p => DCOB1_P_S,
+ DCLK_n => DCOB1_N_S,
+ FCLK_p => FRB1_P_S,
+ FCLK_n => FRB1_N_S,
+ DATA_p => adcdata2367_P(0),
+ DATA_n => adcdata2367_N(0),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(0),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(0),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(0),
+ AdcBitClkDone => AdcBitClkDoneB_S(0),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(0),
+ AdcClkDiv => adcclockB_S(0),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(0),
+ ADCs_ready => ADCs_ready_S(1),
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_2: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y13",
+ C_BufrLoc => "BUFR_X0Y6",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA2_P_S,
+ DCLK_n => DCOA2_N_S,
+ FCLK_p => FRA2_P_S,
+ FCLK_n => FRA2_N_S,
+ DATA_p => adcdata1458_P(1),
+ DATA_n => adcdata1458_n(1),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(1),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(1),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(1),
+ AdcBitClkDone => AdcBitClkDoneA_S(1),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(1),
+ AdcClkDiv => adcclockA_S(1),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(1),
+ ADCs_ready => ADCs_ready_S(2),
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_2: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y14",
+ C_BufrLoc => "BUFR_X0Y7",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
+ )
+ port map(
+ DCLK_p => DCOB2_P_S,
+ DCLK_n => DCOB2_N_S,
+ FCLK_p => FRB2_P_S,
+ FCLK_n => FRB2_N_S,
+ DATA_p => adcdata2367_P(1),
+ DATA_n => adcdata2367_N(1),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(1),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(1),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(1),
+ AdcBitClkDone => AdcBitClkDoneB_S(1),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(1),
+ AdcClkDiv => adcclockB_S(1),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(1),
+ ADCs_ready => ADCs_ready_S(3),
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_3: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y10",
+ C_BufrLoc => "BUFR_X0Y5",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA3_P_S,
+ DCLK_n => DCOA3_N_S,
+ FCLK_p => FRA3_P_S,
+ FCLK_n => FRA3_N_S,
+ DATA_p => adcdata1458_P(2),
+ DATA_n => adcdata1458_n(2),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(2),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(2),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(2),
+ AdcBitClkDone => AdcBitClkDoneA_S(2),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(2),
+ AdcClkDiv => adcclockA_S(2),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(2),
+ ADCs_ready => ADCs_ready_S(4),
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_3: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y9",
+ C_BufrLoc => "BUFR_X0Y4",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2"
+ )
+ port map(
+ DCLK_p => DCOB3_P_S,
+ DCLK_n => DCOB3_N_S,
+ FCLK_p => FRB3_P_S,
+ FCLK_n => FRB3_N_S,
+ DATA_p => adcdata2367_P(2),
+ DATA_n => adcdata2367_N(2),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(2),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(2),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(2),
+ AdcBitClkDone => AdcBitClkDoneB_S(2),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(2),
+ AdcClkDiv => adcclockB_S(2),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(2),
+ ADCs_ready => ADCs_ready_S(5),
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_4: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X2Y9",
+ C_BufrLoc => "BUFR_X2Y4",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA4_P_S,
+ DCLK_n => DCOA4_N_S,
+ FCLK_p => FRA4_P_S,
+ FCLK_n => FRA4_N_S,
+ DATA_p => adcdata1458_P(3),
+ DATA_n => adcdata1458_n(3),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(3),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(3),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(3),
+ AdcBitClkDone => AdcBitClkDoneA_S(3),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(3),
+ AdcClkDiv => adcclockA_S(3),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(3),
+ ADCs_ready => ADCs_ready_S(6),
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_4: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X2Y10",
+ C_BufrLoc => "BUFR_X2Y5",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2"
+ )
+ port map(
+ DCLK_p => DCOB4_P_S,
+ DCLK_n => DCOB4_N_S,
+ FCLK_p => FRB4_P_S,
+ FCLK_n => FRB4_N_S,
+ DATA_p => adcdata2367_P(3),
+ DATA_n => adcdata2367_N(3),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(3),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(3),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(3),
+ AdcBitClkDone => AdcBitClkDoneB_S(3),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(3),
+ AdcClkDiv => adcclockB_S(3),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(3),
+ ADCs_ready => ADCs_ready_S(7),
+ testOK => open,
+ testword0 => open);
+
+--ADCclkbuf : BUFG port map (
+-- O => ADC_clk_S,
+-- I => adcclockB_S(0));
+
+FEE_clockbuf80MHz1: FEE_clockbuf80MHz port map(
+ CLK_IN1 => adcclockA_S(0),
+ CLK_OUT1 => ADC_clk_S,
+ CLK_OUT2 => ADC_clknot_S);
+
+gen_adcpar1: for chipnr in 0 to 3 generate
+
+adcdata0_S((3-chipnr)*8+1) <= AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10);
+adcdata0_S((3-chipnr)*8+2) <= not (AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((3-chipnr)*8+5) <= AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10);
+adcdata0_S((3-chipnr)*8+6) <= not (AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+
+adcdata0_S((3-chipnr)*8+0) <= not (AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((3-chipnr)*8+3) <= AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10);
+adcdata0_S((3-chipnr)*8+4) <= not (AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((3-chipnr)*8+7) <= AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10);
+
+end generate;
+
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+ if (rising_edge(ADC_clk_S)) then
+ adcdata1_S <= adcdata0_S;
+ adcdata <= adcdata1_S;
+ end if;
+end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/modules/LMK03806.vhd b/FEE_ADC32board/modules/LMK03806.vhd
new file mode 100644
index 0000000..5314b04
--- /dev/null
+++ b/FEE_ADC32board/modules/LMK03806.vhd
@@ -0,0 +1,564 @@
+-----------------------------------------------------------
+-- LMK03033 CONTROL UNIT --
+-- --
+-- uWIRE configuration Loader --
+-----------------------------------------------------------
+-- Device: xc5vlx50t-3ff665 --
+-- ISE 11.4 --
+-- created 15 Nov 2011 by Walter Puccio --
+-- Uppsala University, IRFU --
+-- Modified 23 Jan 2011 by P. Marciniewski --
+-- Uppsala University, Dept of Physics and Astronomy --
+-----------------------------------------------------------
+
+
+-- LMK03806:
+-- refclock/R = VCO/(P*N)
+-- CLKout = VCO/Divide
+--
+-- refclock : reference input clock
+-- R = R-divider (register 28)
+-- VCO = Voltage Controlled Oscillator = 2370..2600 MHz
+-- P = Prescaler : 2..8
+-- N = N-divider
+-- CLKout = Clock outputs (CLKout0..11)
+-- Divide = outputclock divider
+--
+-- 80MHz -> 80 MHz :
+-- R=1, VCO=2560, P=2, N=16, divide=32
+--
+-- 40MHz -> 80 MHz :
+-- R=1, VCO=2560, P=2, N=32, divide=32
+-- 40MHz -> 80 MHz :
+-- R=1, VCO=2560, P=4, N=16, divide=32
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+--use work.util_pack.ALL;
+
+entity LMK03806 is
+ generic(
+ CLK_DIV : integer := 6; -- slow down transfer
+ ADCCLOCKFREQUENCY : natural := 62500000
+ );
+ PORT(
+ clock : in std_logic; --Master clock
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDn : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high
+ reset_GTX : out std_logic; --delayed reset for GTX
+ reset_ADCs : out std_logic; --delayed reset for ADCs
+ booting : out std_logic; --busy signal
+ testwordin : in std_logic_vector(15 downto 0)
+ );
+end LMK03806;
+
+
+----------------------------------------------------------------
+
+architecture Behavioral of LMK03806 is
+constant NROFREGS : integer := 23+1+6;
+type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
+type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
+-- parameters based on 'Clock design tool' from National Semiconductor
+CONSTANT TAB80M : RomType :=
+-- 80MHz reference to 80MHz
+ (
+ x"00020000", -- R0 (Reset=1)
+ x"00020000", -- R0 (Reset=1)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+ x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+ x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+ x"55555549", -- R9 (fixed pattern)
+ x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+ x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+ x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+ x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+ x"0300000E", -- R14 (GPout1=weak pulldown)
+ x"C1550410", -- R16 (fixed pattern)
+ x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+ x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+ x"0010001C", -- R28 (R_divider=1
+ x"0080041D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=32
+ x"0200041E", -- R30 (N_prescaler=2 N_divider=32)
+ x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+ );
+
+
+CONSTANT TAB80M_orig : RomType :=
+-- 80MHz reference to 80MHz
+ (
+ x"00020000", -- R0 (Reset=1)
+ x"00020000", -- R0 (Reset=1)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+ x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+ x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+ x"55555549", -- R9 (fixed pattern)
+ x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+ x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+ x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+ x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+ x"0300000E", -- R14 (GPout1=weak pulldown)
+ x"C1550410", -- R16 (fixed pattern)
+ x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+ x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+ x"0010001C", -- R28 (R_divider=1 ????????? :2
+ x"0180021D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=16
+ x"0200021E", -- R30 (N_prescaler=2 N_divider=16)
+ x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+ );
+
+--CONSTANT TAB62M5 : RomType :=
+---- 62.5MHz reference to 62.5MHz
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
+-- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
+-- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
+-- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
+-- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
+-- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
+-- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
+-- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
+-- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
+-- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
+-- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
+-- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+-- x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1 ????????? :2
+-- x"0080029D", -- R29 (OSCin=0..63MHz N_CALdivider=20
+-- x"0200029E", -- R30 (N_prescaler=2 N_divider=20)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+-- (
+-- X"000204c0", --R0 (Reset=1, Div=38 OUT0,1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
+-- X"00000163", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"11110006", --R6 (OUT3,2,1,0 : LVDS)
+-- X"11110007", --R7 (OUT7,6,5,4 : LVDS)
+-- X"11110008", --R8 (OUT11,10,9,8 : LVDS)
+-- X"55555549", --R9 (fixed)
+-- X"1002400a", --R10 (OSCout0=700mV OSCout1=off OSCout=disabled OSC0,1=bypass_divider OSCoutDIV=2)
+-- X"3400000b", --R11 (SYNC=enabled, active=high, externalXTAL=disabled)
+-- X"138c006c", --R12 (LD_MUX=PLL_DLD, LD_TYPE=output, Force sync)
+-- X"7b03800d", --R13 (READ_BACK=pushpull, GPout0=weak pulldown)
+-- X"0300000e", --R14 (GPout1=weak pulldown)
+-- X"c1550410", --R16 (fixed)
+-- X"00000018", --R24 (LoopFilter: C4=10pF, C3=10pF, R4=200Ohm, R3=200Ohm)
+-- X"8fa8001a", --R26 (reffrequ=normal, chargepump=3.2mA, PLL_DLD_CNT=8192 ???????????)
+-- X"0010001c", --R28 (R_divider=1,
+-- X"0080027d", --R29 (OSCin=0..63MHz, N_CALdivider=19 ?????????????)
+-- X"0100027e", --R30 (N_prescaler=2, N_divider=19)
+-- X"0000001f" --R31 (ReadbackReg=0, Regs:unlocked)
+-- );
+
+-- (
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"343f100B", -- R11 (SYNC=enabled active=low, pulldownR externalXTAL=disabled) -- peter, was 3401100B
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync) -- peter, was 130C006C
+-- x"3B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) -- peter, was 3B03826D
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=2 -- peter, was 0010001C
+-- x"0180021D", -- R29 (OSCin=127..255Hz N_CALdivider=16 ?????????????) -- peter, was 0280011D
+-- x"0200021E", -- R30 (N_prescaler=2 N_divider=16) -- peter, was 0200011E
+-- x"001F001F" -- R31 (ReadbackReg=31 Regs:unlocked)
+-- );
+
+-- ( -- Pawel
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=high externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1
+-- x"0080021D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
+-- x"0200021E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
+-- );
+
+-- ( -- Pawel
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0020001C", -- R28 (R_divider=2
+-- x"0180051D", -- R29 (OSCin=0..63MHz N_CALdivider=40 ?????????????)
+-- x"0200051E", -- R30 (N_prescaler=2 N_divider=40)
+-- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
+-- );
+
+
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
+-- X"000004c2", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+------ x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
+------ x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+------ x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1 ????????? :2
+-- x"0080027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
+-- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+------ x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+------ x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
+-- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+------ x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"77110018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0020001C", -- R28 (R_divider=1 ????????? :2
+-- x"0180027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????) 0080027D
+-- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+
+
+
+
+
+
+signal tab : RomType;
+signal SHIFT_REG : std_logic_vector(31 downto 0);
+signal PLLbootstate : std_logic_vector(3 downto 0);
+signal bit_cnt : std_logic_vector(6 downto 0);
+signal cnt_dly : std_logic_vector(3 downto 0);
+signal ptr : std_logic_vector(4 downto 0);
+
+signal boot_dly_cnt : std_logic_vector(31 downto 0) := (others => '0');
+signal pll_res : std_logic;
+
+signal pll_boot : std_logic;
+signal pll_clk : std_logic;
+signal pll_data : std_logic;
+signal pll_le : std_logic;
+signal pll_sync : std_logic;
+signal pll_reset_GTX : std_logic;
+signal pll_reset_ADCs : std_logic;
+
+signal reset_counter_V1 : std_logic_vector(15 downto 0);
+signal reset_counter_V2 : std_logic_vector(7 downto 0);
+
+--------------------------------------------------------------------
+BEGIN
+
+tab <= TAB80M;-- when ADCCLOCKFREQUENCY=80000000 else TAB62M5;
+
+--******************************************************************
+-- RESET SEQUENCER
+--******************************************************************
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if PLLbootstate /= x"0" then
+ reset_counter_V1 <= (others => '0');
+ pll_reset_ADCs <= '1';
+ pll_reset_GTX <= '1';
+ booting <= '1';
+ else
+ booting <= '0';
+ if reset_counter_V1 < x"ffff" then
+ reset_counter_V1 <= reset_counter_V1 + 1;
+ else
+ pll_reset_ADCs <= '0';
+ pll_reset_GTX <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset_counter_V2 < x"ff" then
+ reset_counter_V2 <= reset_counter_V2 + 1;
+ pll_res <= '1';
+ else
+ pll_res <= '0';
+ end if;
+ end if;
+end process;
+
+
+--******************************************************************
+-- PLL BOOT STATEMACHINE
+--******************************************************************
+
+process(clock, pll_res)
+begin
+ if pll_res = '1' then
+ PLLbootstate <= (others => '0');
+ pll_sync <= '1';
+ --GOE <= '0';
+ pll_clk <= '0';
+ pll_le <= '0';
+ ptr <= (others => '0');
+
+ elsif rising_edge(clock) then
+
+ pll_boot <= BOOT_PLL;
+
+ case PLLbootstate is
+ when x"0" => --IDLE here until BOOT_DLY goes High
+ pll_sync <= '1';
+ --GOE <= '0';
+ pll_clk <= '0';
+ pll_le <= '0';
+ ptr <= (others => '0');
+ if pll_boot = '1' then PLLbootstate <= x"1";
+ end if;
+
+--*******Start
+ when x"1" => --Set up for TX
+ pll_le <= '0';
+ pll_clk <= '0';
+if ptr=24 then
+SHIFT_REG(15 downto 0) <= x"0018";
+SHIFT_REG(31 downto 16) <= testwordin;
+else
+ SHIFT_REG <= tab(conv_integer(ptr));
+end if;
+ bit_cnt <= (others => '0');
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"2";
+
+ when x"2" => --CLK low
+ pll_clk <= '0';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"3";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"3" => --CLK high
+ pll_clk <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ bit_cnt <= bit_cnt + 1;
+ PLLbootstate <= x"4";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"4" => --Loop through all bits and regs
+ pll_clk <= '0';
+ cnt_dly <= (others => '0');
+ SHIFT_REG <= SHIFT_REG(30 downto 0) & '0';
+ if bit_cnt > 31 then --32 bits
+ pll_le <= '1';
+ if conv_integer(ptr) < NROFREGS-1 then --nr of regs
+ ptr <= ptr + 1;
+ PLLbootstate <= x"5";
+ else
+----peter pll_sync <= '0';
+ PLLbootstate <= x"6";
+ end if;
+ else PLLbootstate <= x"2";
+ end if;
+
+ when x"5" => --Latch Delay
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"1";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"6" => --pll_sync Delay
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"7";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"7" => --SYNC
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"8";
+ pll_sync <= '0';
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+ pll_le <= '0';
+
+ when x"8" => --SYNC
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"9";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+ pll_le <= '0';
+
+ when x"9" => --IDLE here until BOOT_PLL goes low
+ pll_sync <= '1';
+ pll_le <= '0';
+ if pll_boot = '0' then PLLbootstate <= x"0";
+ end if;
+
+ when others => -- make sure other states wont lock up.
+ PLLbootstate <= (others => '0');
+ end case;
+ end if;
+end process;
+
+--Shift out bits, MSB first
+pll_data <= SHIFT_REG(31);
+
+
+CLKu <= pll_clk;
+DATAu <= pll_data;
+LEu <= pll_le;
+SYNC <= pll_sync;
+reset_GTX <= pll_reset_GTX;
+reset_ADCs <= pll_reset_ADCs;
+
+
+END Behavioral;
+
+
diff --git a/FEE_ADC32board/modules/SystemMonitorModule.vhd b/FEE_ADC32board/modules/SystemMonitorModule.vhd
new file mode 100644
index 0000000..a045402
--- /dev/null
+++ b/FEE_ADC32board/modules/SystemMonitorModule.vhd
@@ -0,0 +1,281 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 10-10-2012
+-- Module Name: SystemMonitorModule
+-- Description: Reads FPGA system parameters
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- SystemMonitorModule
+-- Reads FPGA system parameters: temperature and voltages
+-- The Xilinx System Monitor measures several FPGA physical operating parameters.
+-- For further information see Xilinx documentation
+-- The settings and parameters are accessable with a 16-bits data bus and 7 bits address bus.
+-- This module initializes the System Monitor so that the main parameters are continuously measured.
+-- This behaviour can bechanged because all settings are accessable.
+--
+--
+-- The main settings addresses and their initialize value are:
+-- 0x40 : 1000 -- average 16
+-- 0x41 : 2000 -- enable sequence & alarms, no calibration
+-- 0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
+-- 0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
+-- 0x49 : 0000 -- not Vaux
+-- 0x4a : 3700 -- enable averaging
+-- 0x4b : 0000 -- disable averaging Vau
+-- 0x4c : 0000 -- unipolar inputs
+-- 0x4d : 0000 -- unipolar inputs
+-- 0x4e : 0000 -- default Acquisition Time
+-- 0x4f : 0000 -- default Acquisition Time
+--
+--
+-- The system parameters are measured with an 10 bits ADC:
+--
+-- For die Temperature (address 0) :
+-- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15
+--
+-- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) :
+-- Supply Voltage (Volts) = (ADCcode / 1024) x 3V
+--
+-- For VrefN(0.0V, address=5) :
+-- Voltage (Volts) = ADCcode(2-complement) * 977uV
+--
+--
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock for the system monitor (must not exceed 100MHz)
+-- reset : reset
+-- address : six bit address
+-- data_write : write signal for data to be set
+-- data_in : 16 bits data to be written
+-- data_read : read signal for reading data, data becomes available 3 clock cycles after this read signal!!
+--
+-- Outputs:
+-- data_out : data from the System Monitor, data becomes available 3 clock cycles after this read signal!!
+-- alarms :
+-- bit0 = user settable temperature
+-- bit1 = alarm on VCCint voltage
+-- bit2 = alarm on VCCaux voltage
+-- bit3 = alarm on over temperature
+-- bit7..4 = "0000" not yet used
+--
+-- Components:
+-- SystemMonitorVirtex : IP core generator module for Virtex
+--
+----------------------------------------------------------------------------------
+
+entity SystemMonitorModule is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(6 downto 0);
+ data_write : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ data_read : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ alarms : out std_logic_vector(7 downto 0);
+ testword0 : out std_logic_vector(35 downto 0));
+end SystemMonitorModule;
+
+
+architecture Behavioral of SystemMonitorModule is
+
+component SystemMonitorVirtex
+ port (
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
+ VN_IN : in STD_LOGIC
+);
+end component;
+constant NROFREGISTERS : natural :=11;
+type registerarray_type is array (0 to NROFREGISTERS-1)
+ of std_logic_vector (23 downto 0);
+
+constant REGISTERARRAY : registerarray_type := (
+x"401000", -- average 16
+x"412000", -- enable sequence & alarms, no calibration
+x"421400", -- clock division = 20 : 50MHz/2.5MHz
+x"483700", -- select temp,VCCint,VCCaux,VrefP,VrefN
+x"490000", -- not Vaux
+x"4a3700", -- enable averaging
+x"4b0000", -- disable averaging Vau
+x"4c0000", -- unipolar inputs
+x"4d0000", -- unipolar inputs
+x"4e0000", -- default Acquisition Time
+x"4f0000"); -- default Acquisition Time
+
+
+
+
+
+
+
+
+--0x40 : 1000 -- average 16
+--0x41 : 2000 -- enable sequence & alarms, no calibration
+--0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
+--0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
+--0x49 : 0000 -- not Vaux
+--0x4a : 3700 -- enable averaging
+--0x4b : 0000 -- disable averaging Vau
+--0x4c : 0000 -- unipolar inputs
+--0x4d : 0000 -- unipolar inputs
+--0x4e : 0000 -- default Acquisition Time
+--0x4f : 0000 -- default Acquisition Time
+
+
+signal registerindex_S : integer range 0 to NROFREGISTERS;
+signal accesscounter_S : integer range 0 to 7;
+signal delaycounter_S : std_logic_vector(11 downto 0);
+signal sysmon_active_S : std_logic := '0';
+
+signal DR_address_S : std_logic_vector(6 downto 0);
+signal DR_address_init_S : std_logic_vector(6 downto 0);
+signal DR_enable_S : std_logic := '0';
+signal DR_data_in_S : std_logic_vector(15 downto 0);
+signal DR_data_init_S : std_logic_vector(15 downto 0);
+
+signal DR_write_S : std_logic := '0';
+signal DR_write_init_S : std_logic := '0';
+signal ADC_busy_S : std_logic := '0';
+
+signal channel_S : std_logic_vector(4 downto 0);
+signal DR_data_out_S : std_logic_vector(15 downto 0);
+signal DR_ready_S : std_logic := '0';
+signal EndofConversion_S : std_logic := '0';
+signal EndofSequence_S : std_logic := '0';
+
+signal OverTemperatur_alarm_S : std_logic := '0';
+signal VCCaux_alarm_S : std_logic := '0';
+signal VCCint_alarm_S : std_logic := '0';
+signal USERtemp_alarm_S : std_logic := '0';
+
+
+
+begin
+
+
+SystemMonitorVirtex1: SystemMonitorVirtex port map (
+ DADDR_IN => DR_address_S,
+ DCLK_IN => clock,
+ DEN_IN => DR_enable_S,
+ DI_IN => DR_data_in_S,
+ DWE_IN => DR_write_S,
+ RESET_IN => reset,
+ BUSY_OUT => ADC_busy_S,
+ CHANNEL_OUT => channel_S,
+ DO_OUT => DR_data_out_S,
+ DRDY_OUT => DR_ready_S,
+ EOC_OUT => EndofConversion_S,
+ EOS_OUT => EndofSequence_S,
+ JTAGBUSY_OUT => open,
+ JTAGLOCKED_OUT => open,
+ JTAGMODIFIED_OUT => open,
+ OT_OUT => OverTemperatur_alarm_S,
+ VCCAUX_ALARM_OUT => VCCaux_alarm_S,
+ VCCINT_ALARM_OUT => VCCint_alarm_S,
+ USER_TEMP_ALARM_OUT => USERtemp_alarm_S,
+ VP_IN => '0',
+ VN_IN => '0'
+ );
+
+alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;
+alarms(7 downto 4) <= (others => '0');
+
+DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;
+DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';
+data_out <= DR_data_out_S;
+
+DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';
+DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if (reset = '1') and (sysmon_active_S='1') then
+ DR_write_init_S <= '0';
+ sysmon_active_S <= '0';
+ registerindex_S <= 0;
+ accesscounter_S <= 0;
+ delaycounter_S <= (others => '0');
+ else
+ if sysmon_active_S='0' then
+ if delaycounter_S(delaycounter_S'left)='0' then
+ delaycounter_S <= delaycounter_S+1;
+ DR_write_init_S <= '0';
+ registerindex_S <= 0;
+ accesscounter_S <= 0;
+ DR_address_init_S <= (others => '0');
+ else
+ if accesscounter_S<7 then
+ if accesscounter_S=0 then
+ DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);
+ DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);
+ DR_write_init_S <= '1';
+ else
+ DR_write_init_S <= '0';
+ end if;
+ accesscounter_S <= accesscounter_S+1;
+ else
+ accesscounter_S <= 0;
+ DR_write_init_S <= '0';
+ if registerindex_S '0');
+ DR_data_init_S <= (others => '0');
+ registerindex_S <= 0;
+ sysmon_active_S <= '1';
+ end if;
+ end if;
+ end if;
+ else
+ accesscounter_S <= 0;
+ DR_write_init_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+testword0(15 downto 0) <= DR_data_out_S;
+testword0(22 downto 16) <= DR_address_S;
+testword0(23) <= sysmon_active_S;
+testword0(24) <= '0';
+testword0(25) <= DR_enable_S;
+testword0(26) <= ADC_busy_S;
+testword0(27) <= DR_ready_S;
+testword0(28) <= EndofConversion_S;
+testword0(29) <= EndofSequence_S;
+testword0(30) <= '1' when OverTemperatur_alarm_S='1' or VCCaux_alarm_S='1' or VCCint_alarm_S='1' or USERtemp_alarm_S='1' else '0';
+testword0(35 downto 31) <= channel_S;
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/project/FEE_ADC32board.gise b/FEE_ADC32board/project/FEE_ADC32board.gise
new file mode 100644
index 0000000..d8991cb
--- /dev/null
+++ b/FEE_ADC32board/project/FEE_ADC32board.gise
@@ -0,0 +1,33 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/project/FEE_ADC32board.ucf b/FEE_ADC32board/project/FEE_ADC32board.ucf
new file mode 100644
index 0000000..c20f4de
--- /dev/null
+++ b/FEE_ADC32board/project/FEE_ADC32board.ucf
@@ -0,0 +1,1009 @@
+NET "AD11A_N" DIFF_TERM = "TRUE";
+NET "AD11A_N" IOSTANDARD = LVDS_25;
+NET "AD11A_N" LOC = C17;
+NET "AD11A_P" DIFF_TERM = "TRUE";
+NET "AD11A_P" IOSTANDARD = LVDS_25;
+NET "AD11A_P" LOC = C16;
+NET "AD11B_N" DIFF_TERM = "TRUE";
+NET "AD11B_N" IOSTANDARD = LVDS_25;
+NET "AD11B_N" LOC = A18;
+NET "AD11B_P" DIFF_TERM = "TRUE";
+NET "AD11B_P" IOSTANDARD = LVDS_25;
+NET "AD11B_P" LOC = A17;
+NET "AD12A_N" DIFF_TERM = "TRUE";
+NET "AD12A_N" IOSTANDARD = LVDS_25;
+NET "AD12A_N" LOC = D18;
+NET "AD12A_P" DIFF_TERM = "TRUE";
+NET "AD12A_P" IOSTANDARD = LVDS_25;
+NET "AD12A_P" LOC = D17;
+NET "AD12B_N" DIFF_TERM = "TRUE";
+NET "AD12B_N" IOSTANDARD = LVDS_25;
+NET "AD12B_N" LOC = C18;
+NET "AD12B_P" DIFF_TERM = "TRUE";
+NET "AD12B_P" IOSTANDARD = LVDS_25;
+NET "AD12B_P" LOC = B18;
+NET "AD13A_N" DIFF_TERM = "TRUE";
+NET "AD13A_N" IOSTANDARD = LVDS_25;
+NET "AD13A_N" LOC = F17;
+NET "AD13A_P" DIFF_TERM = "TRUE";
+NET "AD13A_P" IOSTANDARD = LVDS_25;
+NET "AD13A_P" LOC = E17;
+NET "AD13B_N" DIFF_TERM = "TRUE";
+NET "AD13B_N" IOSTANDARD = LVDS_25;
+NET "AD13B_N" LOC = H15;
+NET "AD13B_P" DIFF_TERM = "TRUE";
+NET "AD13B_P" IOSTANDARD = LVDS_25;
+NET "AD13B_P" LOC = G15;
+NET "AD14A_N" DIFF_TERM = "TRUE";
+NET "AD14A_N" IOSTANDARD = LVDS_25;
+NET "AD14A_N" LOC = H16;
+NET "AD14A_P" DIFF_TERM = "TRUE";
+NET "AD14A_P" IOSTANDARD = LVDS_25;
+NET "AD14A_P" LOC = G16;
+NET "AD14B_N" DIFF_TERM = "TRUE";
+NET "AD14B_N" IOSTANDARD = LVDS_25;
+NET "AD14B_N" LOC = B16;
+NET "AD14B_P" DIFF_TERM = "TRUE";
+NET "AD14B_P" IOSTANDARD = LVDS_25;
+NET "AD14B_P" LOC = A16;
+NET "AD15A_N" DIFF_TERM = "TRUE";
+NET "AD15A_N" IOSTANDARD = LVDS_25;
+NET "AD15A_N" LOC = F14;
+NET "AD15A_P" DIFF_TERM = "TRUE";
+NET "AD15A_P" IOSTANDARD = LVDS_25;
+NET "AD15A_P" LOC = G14;
+NET "AD15B_N" DIFF_TERM = "TRUE";
+NET "AD15B_N" IOSTANDARD = LVDS_25;
+NET "AD15B_N" LOC = B14;
+NET "AD15B_P" DIFF_TERM = "TRUE";
+NET "AD15B_P" IOSTANDARD = LVDS_25;
+NET "AD15B_P" LOC = A14;
+NET "AD16A_N" DIFF_TERM = "TRUE";
+NET "AD16A_N" IOSTANDARD = LVDS_25;
+NET "AD16A_N" LOC = E14;
+NET "AD16A_P" DIFF_TERM = "TRUE";
+NET "AD16A_P" IOSTANDARD = LVDS_25;
+NET "AD16A_P" LOC = D14;
+NET "AD16B_N" DIFF_TERM = "TRUE";
+NET "AD16B_N" IOSTANDARD = LVDS_25;
+NET "AD16B_N" LOC = G13;
+NET "AD16B_P" DIFF_TERM = "TRUE";
+NET "AD16B_P" IOSTANDARD = LVDS_25;
+NET "AD16B_P" LOC = F13;
+NET "AD17A_N" DIFF_TERM = "TRUE";
+NET "AD17A_N" IOSTANDARD = LVDS_25;
+NET "AD17A_N" LOC = D13;
+NET "AD17A_P" DIFF_TERM = "TRUE";
+NET "AD17A_P" IOSTANDARD = LVDS_25;
+NET "AD17A_P" LOC = C13;
+NET "AD17B_N" DIFF_TERM = "TRUE";
+NET "AD17B_N" IOSTANDARD = LVDS_25;
+NET "AD17B_N" LOC = E12;
+NET "AD17B_P" DIFF_TERM = "TRUE";
+NET "AD17B_P" IOSTANDARD = LVDS_25;
+NET "AD17B_P" LOC = F12;
+NET "AD18A_N" DIFF_TERM = "TRUE";
+NET "AD18A_N" IOSTANDARD = LVDS_25;
+NET "AD18A_N" LOC = B13;
+NET "AD18A_P" DIFF_TERM = "TRUE";
+NET "AD18A_P" IOSTANDARD = LVDS_25;
+NET "AD18A_P" LOC = A13;
+NET "AD18B_N" DIFF_TERM = "TRUE";
+NET "AD18B_N" IOSTANDARD = LVDS_25;
+NET "AD18B_N" LOC = H13;
+NET "AD18B_P" DIFF_TERM = "TRUE";
+NET "AD18B_P" IOSTANDARD = LVDS_25;
+NET "AD18B_P" LOC = H12;
+
+NET "AD21A_N" DIFF_TERM = "TRUE";
+NET "AD21A_N" IOSTANDARD = LVDS_25;
+NET "AD21A_N" LOC = H22;
+NET "AD21A_P" DIFF_TERM = "TRUE";
+NET "AD21A_P" IOSTANDARD = LVDS_25;
+NET "AD21A_P" LOC = J22;
+NET "AD21B_N" DIFF_TERM = "TRUE";
+NET "AD21B_N" IOSTANDARD = LVDS_25;
+NET "AD21B_N" LOC = K22;
+NET "AD21B_P" DIFF_TERM = "TRUE";
+NET "AD21B_P" IOSTANDARD = LVDS_25;
+NET "AD21B_P" LOC = K21;
+NET "AD22A_N" DIFF_TERM = "TRUE";
+NET "AD22A_N" IOSTANDARD = LVDS_25;
+NET "AD22A_N" LOC = L17;
+NET "AD22A_P" DIFF_TERM = "TRUE";
+NET "AD22A_P" IOSTANDARD = LVDS_25;
+NET "AD22A_P" LOC = K17;
+NET "AD22B_N" DIFF_TERM = "TRUE";
+NET "AD22B_N" IOSTANDARD = LVDS_25;
+NET "AD22B_N" LOC = L19;
+NET "AD22B_P" DIFF_TERM = "TRUE";
+NET "AD22B_P" IOSTANDARD = LVDS_25;
+NET "AD22B_P" LOC = L18;
+NET "AD23A_N" DIFF_TERM = "TRUE";
+NET "AD23A_N" IOSTANDARD = LVDS_25;
+NET "AD23A_N" LOC = K20;
+NET "AD23A_P" DIFF_TERM = "TRUE";
+NET "AD23A_P" IOSTANDARD = LVDS_25;
+NET "AD23A_P" LOC = J20;
+NET "AD23B_N" DIFF_TERM = "TRUE";
+NET "AD23B_N" IOSTANDARD = LVDS_25;
+NET "AD23B_N" LOC = J17;
+NET "AD23B_P" DIFF_TERM = "TRUE";
+NET "AD23B_P" IOSTANDARD = LVDS_25;
+NET "AD23B_P" LOC = J18;
+NET "AD24A_N" DIFF_TERM = "TRUE";
+NET "AD24A_N" IOSTANDARD = LVDS_25;
+NET "AD24A_N" LOC = J19;
+NET "AD24A_P" DIFF_TERM = "TRUE";
+NET "AD24A_P" IOSTANDARD = LVDS_25;
+NET "AD24A_P" LOC = K19;
+NET "AD24B_N" DIFF_TERM = "TRUE";
+NET "AD24B_N" IOSTANDARD = LVDS_25;
+NET "AD24B_N" LOC = H21;
+NET "AD24B_P" DIFF_TERM = "TRUE";
+NET "AD24B_P" IOSTANDARD = LVDS_25;
+NET "AD24B_P" LOC = G21;
+NET "AD25A_N" DIFF_TERM = "TRUE";
+NET "AD25A_N" IOSTANDARD = LVDS_25;
+NET "AD25A_N" LOC = H18;
+NET "AD25A_P" DIFF_TERM = "TRUE";
+NET "AD25A_P" IOSTANDARD = LVDS_25;
+NET "AD25A_P" LOC = H17;
+NET "AD25B_N" DIFF_TERM = "TRUE";
+NET "AD25B_N" IOSTANDARD = LVDS_25;
+NET "AD25B_N" LOC = F19;
+NET "AD25B_P" DIFF_TERM = "TRUE";
+NET "AD25B_P" IOSTANDARD = LVDS_25;
+NET "AD25B_P" LOC = G19;
+NET "AD26A_N" DIFF_TERM = "TRUE";
+NET "AD26A_N" IOSTANDARD = LVDS_25;
+NET "AD26A_N" LOC = E22;
+NET "AD26A_P" DIFF_TERM = "TRUE";
+NET "AD26A_P" IOSTANDARD = LVDS_25;
+NET "AD26A_P" LOC = E21;
+NET "AD26B_N" DIFF_TERM = "TRUE";
+NET "AD26B_N" IOSTANDARD = LVDS_25;
+NET "AD26B_N" LOC = D19;
+NET "AD26B_P" DIFF_TERM = "TRUE";
+NET "AD26B_P" IOSTANDARD = LVDS_25;
+NET "AD26B_P" LOC = E19;
+NET "AD27A_N" DIFF_TERM = "TRUE";
+NET "AD27A_N" IOSTANDARD = LVDS_25;
+NET "AD27A_N" LOC = C20;
+NET "AD27A_P" DIFF_TERM = "TRUE";
+NET "AD27A_P" IOSTANDARD = LVDS_25;
+NET "AD27A_P" LOC = B20;
+NET "AD27B_N" DIFF_TERM = "TRUE";
+NET "AD27B_N" IOSTANDARD = LVDS_25;
+NET "AD27B_N" LOC = B21;
+NET "AD27B_P" DIFF_TERM = "TRUE";
+NET "AD27B_P" IOSTANDARD = LVDS_25;
+NET "AD27B_P" LOC = A21;
+NET "AD28A_N" DIFF_TERM = "TRUE";
+NET "AD28A_N" IOSTANDARD = LVDS_25;
+NET "AD28A_N" LOC = F18;
+NET "AD28A_P" DIFF_TERM = "TRUE";
+NET "AD28A_P" IOSTANDARD = LVDS_25;
+NET "AD28A_P" LOC = G18;
+NET "AD28B_N" DIFF_TERM = "TRUE";
+NET "AD28B_N" IOSTANDARD = LVDS_25;
+NET "AD28B_N" LOC = C21;
+NET "AD28B_P" DIFF_TERM = "TRUE";
+NET "AD28B_P" IOSTANDARD = LVDS_25;
+NET "AD28B_P" LOC = B22;
+
+NET "AD31A_N" DIFF_TERM = "TRUE";
+NET "AD31A_N" IOSTANDARD = LVDS_25;
+NET "AD31A_N" LOC = T21;
+NET "AD31A_P" DIFF_TERM = "TRUE";
+NET "AD31A_P" IOSTANDARD = LVDS_25;
+NET "AD31A_P" LOC = U21;
+NET "AD31B_N" DIFF_TERM = "TRUE";
+NET "AD31B_N" IOSTANDARD = LVDS_25;
+NET "AD31B_N" LOC = Y21;
+NET "AD31B_P" DIFF_TERM = "TRUE";
+NET "AD31B_P" IOSTANDARD = LVDS_25;
+NET "AD31B_P" LOC = AA21;
+NET "AD32A_N" DIFF_TERM = "TRUE";
+NET "AD32A_N" IOSTANDARD = LVDS_25;
+NET "AD32A_N" LOC = AB21;
+NET "AD32A_P" DIFF_TERM = "TRUE";
+NET "AD32A_P" IOSTANDARD = LVDS_25;
+NET "AD32A_P" LOC = AB20;
+NET "AD32B_N" DIFF_TERM = "TRUE";
+NET "AD32B_N" IOSTANDARD = LVDS_25;
+NET "AD32B_N" LOC = U20;
+NET "AD32B_P" DIFF_TERM = "TRUE";
+NET "AD32B_P" IOSTANDARD = LVDS_25;
+NET "AD32B_P" LOC = U19;
+NET "AD33A_N" DIFF_TERM = "TRUE";
+NET "AD33A_N" IOSTANDARD = LVDS_25;
+NET "AD33A_N" LOC = W20;
+NET "AD33A_P" DIFF_TERM = "TRUE";
+NET "AD33A_P" IOSTANDARD = LVDS_25;
+NET "AD33A_P" LOC = Y20;
+NET "AD33B_N" DIFF_TERM = "TRUE";
+NET "AD33B_N" IOSTANDARD = LVDS_25;
+NET "AD33B_N" LOC = V21;
+NET "AD33B_P" DIFF_TERM = "TRUE";
+NET "AD33B_P" IOSTANDARD = LVDS_25;
+NET "AD33B_P" LOC = V20;
+NET "AD34A_N" DIFF_TERM = "TRUE";
+NET "AD34A_N" IOSTANDARD = LVDS_25;
+NET "AD34A_N" LOC = AA22;
+NET "AD34A_P" DIFF_TERM = "TRUE";
+NET "AD34A_P" IOSTANDARD = LVDS_25;
+NET "AD34A_P" LOC = Y22;
+NET "AD34B_N" DIFF_TERM = "TRUE";
+NET "AD34B_N" IOSTANDARD = LVDS_25;
+NET "AD34B_N" LOC = T19;
+NET "AD34B_P" DIFF_TERM = "TRUE";
+NET "AD34B_P" IOSTANDARD = LVDS_25;
+NET "AD34B_P" LOC = T18;
+NET "AD35A_N" DIFF_TERM = "TRUE";
+NET "AD35A_N" IOSTANDARD = LVDS_25;
+NET "AD35A_N" LOC = R20;
+NET "AD35A_P" DIFF_TERM = "TRUE";
+NET "AD35A_P" IOSTANDARD = LVDS_25;
+NET "AD35A_P" LOC = R19;
+NET "AD35B_N" DIFF_TERM = "TRUE";
+NET "AD35B_N" IOSTANDARD = LVDS_25;
+NET "AD35B_N" LOC = P17;
+NET "AD35B_P" DIFF_TERM = "TRUE";
+NET "AD35B_P" IOSTANDARD = LVDS_25;
+NET "AD35B_P" LOC = N17;
+NET "AD36A_N" DIFF_TERM = "TRUE";
+NET "AD36A_N" IOSTANDARD = LVDS_25;
+NET "AD36A_N" LOC = R22;
+NET "AD36A_P" DIFF_TERM = "TRUE";
+NET "AD36A_P" IOSTANDARD = LVDS_25;
+NET "AD36A_P" LOC = P22;
+NET "AD36B_N" DIFF_TERM = "TRUE";
+NET "AD36B_N" IOSTANDARD = LVDS_25;
+NET "AD36B_N" LOC = N21;
+NET "AD36B_P" DIFF_TERM = "TRUE";
+NET "AD36B_P" IOSTANDARD = LVDS_25;
+NET "AD36B_P" LOC = N22;
+NET "AD37A_N" DIFF_TERM = "TRUE";
+NET "AD37A_N" IOSTANDARD = LVDS_25;
+NET "AD37A_N" LOC = M19;
+NET "AD37A_P" DIFF_TERM = "TRUE";
+NET "AD37A_P" IOSTANDARD = LVDS_25;
+NET "AD37A_P" LOC = M20;
+NET "AD37B_N" DIFF_TERM = "TRUE";
+NET "AD37B_N" IOSTANDARD = LVDS_25;
+NET "AD37B_N" LOC = L21;
+NET "AD37B_P" DIFF_TERM = "TRUE";
+NET "AD37B_P" IOSTANDARD = LVDS_25;
+NET "AD37B_P" LOC = L22;
+NET "AD38A_N" DIFF_TERM = "TRUE";
+NET "AD38A_N" IOSTANDARD = LVDS_25;
+NET "AD38A_N" LOC = N18;
+NET "AD38A_P" DIFF_TERM = "TRUE";
+NET "AD38A_P" IOSTANDARD = LVDS_25;
+NET "AD38A_P" LOC = M18;
+NET "AD38B_N" DIFF_TERM = "TRUE";
+NET "AD38B_N" IOSTANDARD = LVDS_25;
+NET "AD38B_N" LOC = N20;
+NET "AD38B_P" DIFF_TERM = "TRUE";
+NET "AD38B_P" IOSTANDARD = LVDS_25;
+NET "AD38B_P" LOC = M21;
+
+NET "AD41A_N" DIFF_TERM = "TRUE";
+NET "AD41A_N" IOSTANDARD = LVDS_25;
+NET "AD41A_N" LOC = U8;
+NET "AD41A_P" DIFF_TERM = "TRUE";
+NET "AD41A_P" IOSTANDARD = LVDS_25;
+NET "AD41A_P" LOC = V8;
+NET "AD41B_N" DIFF_TERM = "TRUE";
+NET "AD41B_N" IOSTANDARD = LVDS_25;
+NET "AD41B_N" LOC = Y7;
+NET "AD41B_P" DIFF_TERM = "TRUE";
+NET "AD41B_P" IOSTANDARD = LVDS_25;
+NET "AD41B_P" LOC = Y6;
+NET "AD42A_N" DIFF_TERM = "TRUE";
+NET "AD42A_N" IOSTANDARD = LVDS_25;
+NET "AD42A_N" LOC = T7;
+NET "AD42A_P" DIFF_TERM = "TRUE";
+NET "AD42A_P" IOSTANDARD = LVDS_25;
+NET "AD42A_P" LOC = T6;
+NET "AD42B_N" DIFF_TERM = "TRUE";
+NET "AD42B_N" IOSTANDARD = LVDS_25;
+NET "AD42B_N" LOC = AA6;
+NET "AD42B_P" DIFF_TERM = "TRUE";
+NET "AD42B_P" IOSTANDARD = LVDS_25;
+NET "AD42B_P" LOC = AB6;
+NET "AD43A_N" DIFF_TERM = "TRUE";
+NET "AD43A_N" IOSTANDARD = LVDS_25;
+NET "AD43A_N" LOC = W7;
+NET "AD43A_P" DIFF_TERM = "TRUE";
+NET "AD43A_P" IOSTANDARD = LVDS_25;
+NET "AD43A_P" LOC = V7;
+NET "AD43B_N" DIFF_TERM = "TRUE";
+NET "AD43B_N" IOSTANDARD = LVDS_25;
+NET "AD43B_N" LOC = AB8;
+NET "AD43B_P" DIFF_TERM = "TRUE";
+NET "AD43B_P" IOSTANDARD = LVDS_25;
+NET "AD43B_P" LOC = AB9;
+NET "AD44A_N" DIFF_TERM = "TRUE";
+NET "AD44A_N" IOSTANDARD = LVDS_25;
+NET "AD44A_N" LOC = V6;
+NET "AD44A_P" DIFF_TERM = "TRUE";
+NET "AD44A_P" IOSTANDARD = LVDS_25;
+NET "AD44A_P" LOC = U6;
+NET "AD44B_N" DIFF_TERM = "TRUE";
+NET "AD44B_N" IOSTANDARD = LVDS_25;
+NET "AD44B_N" LOC = W8;
+NET "AD44B_P" DIFF_TERM = "TRUE";
+NET "AD44B_P" IOSTANDARD = LVDS_25;
+NET "AD44B_P" LOC = W9;
+NET "AD45A_N" DIFF_TERM = "TRUE";
+NET "AD45A_N" IOSTANDARD = LVDS_25;
+NET "AD45A_N" LOC = T8;
+NET "AD45A_P" DIFF_TERM = "TRUE";
+NET "AD45A_P" IOSTANDARD = LVDS_25;
+NET "AD45A_P" LOC = R9;
+NET "AD45B_N" DIFF_TERM = "TRUE";
+NET "AD45B_N" IOSTANDARD = LVDS_25;
+NET "AD45B_N" LOC = Y11;
+NET "AD45B_P" DIFF_TERM = "TRUE";
+NET "AD45B_P" IOSTANDARD = LVDS_25;
+NET "AD45B_P" LOC = AA11;
+NET "AD46A_N" DIFF_TERM = "TRUE";
+NET "AD46A_N" IOSTANDARD = LVDS_25;
+NET "AD46A_N" LOC = Y10;
+NET "AD46A_P" DIFF_TERM = "TRUE";
+NET "AD46A_P" IOSTANDARD = LVDS_25;
+NET "AD46A_P" LOC = W10;
+NET "AD46B_N" DIFF_TERM = "TRUE";
+NET "AD46B_N" IOSTANDARD = LVDS_25;
+NET "AD46B_N" LOC = V11;
+NET "AD46B_P" DIFF_TERM = "TRUE";
+NET "AD46B_P" IOSTANDARD = LVDS_25;
+NET "AD46B_P" LOC = U11;
+NET "AD47A_N" DIFF_TERM = "TRUE";
+NET "AD47A_N" IOSTANDARD = LVDS_25;
+NET "AD47A_N" LOC = T11;
+NET "AD47A_P" DIFF_TERM = "TRUE";
+NET "AD47A_P" IOSTANDARD = LVDS_25;
+NET "AD47A_P" LOC = T12;
+NET "AD47B_N" DIFF_TERM = "TRUE";
+NET "AD47B_N" IOSTANDARD = LVDS_25;
+NET "AD47B_N" LOC = W12;
+NET "AD47B_P" DIFF_TERM = "TRUE";
+NET "AD47B_P" IOSTANDARD = LVDS_25;
+NET "AD47B_P" LOC = V12;
+NET "AD48A_N" DIFF_TERM = "TRUE";
+NET "AD48A_N" IOSTANDARD = LVDS_25;
+NET "AD48A_N" LOC = U10;
+NET "AD48A_P" DIFF_TERM = "TRUE";
+NET "AD48A_P" IOSTANDARD = LVDS_25;
+NET "AD48A_P" LOC = T9;
+NET "AD48B_N" DIFF_TERM = "TRUE";
+NET "AD48B_N" IOSTANDARD = LVDS_25;
+NET "AD48B_N" LOC = AA12;
+NET "AD48B_P" DIFF_TERM = "TRUE";
+NET "AD48B_P" IOSTANDARD = LVDS_25;
+NET "AD48B_P" LOC = Y12;
+
+NET "DATAu" LOC = B10;
+NET "CLKu" LOC = A11;
+NET "RDu" LOC = C10;
+NET "LEu" LOC = A12;
+NET "SYNC" LOC = G11;
+
+NET "S_CTRL" LOC = W14;
+NET "T_CTRL" LOC = Y14;
+NET "GEO" LOC = AB13;
+
+#
+NET "SCK" LOC = W17;
+NET "SDI" LOC = W18;
+NET "CSA[1]" LOC = AA17;
+NET "CSA[2]" LOC = AB18;
+NET "CSA[3]" LOC = V18;
+NET "CSA[4]" LOC = T16;
+NET "CSB[1]" LOC = Y17;
+NET "CSB[2]" LOC = AA18;
+NET "CSB[3]" LOC = V17;
+NET "CSB[4]" LOC = R16;
+
+NET "SDOA[1]" LOC = Y16;
+NET "SDOA[2]" LOC = AA19;
+NET "SDOA[3]" LOC = V13;
+NET "SDOA[4]" LOC = T17;
+NET "SDOB[1]" LOC = AA16;
+NET "SDOB[2]" LOC = AB19;
+NET "SDOB[3]" LOC = W13;
+NET "SDOB[4]" LOC = U18;
+
+#
+#NET "D<0>" LOC = "V15";
+#NET "D<1>" LOC = "U15";
+#NET "D<2>" LOC = "R15";
+#NET "D<3>" LOC = "R14";
+#NET "D<4>" LOC = "Y19";
+#NET "D<5>" LOC = "W19";
+#NET "D<6>" LOC = "U16";
+#NET "D<7>" LOC = "V16";
+NET "DCOA1_N" DIFF_TERM = "TRUE";
+NET "DCOA1_N" IOSTANDARD = LVDS_25;
+NET "DCOA1_N" LOC = F16;
+NET "DCOA1_P" DIFF_TERM = "TRUE";
+NET "DCOA1_P" IOSTANDARD = LVDS_25;
+NET "DCOA1_P" LOC = E16;
+NET "DCOA2_N" DIFF_TERM = "TRUE";
+NET "DCOA2_N" IOSTANDARD = LVDS_25;
+NET "DCOA2_N" LOC = D22;
+NET "DCOA2_P" DIFF_TERM = "TRUE";
+NET "DCOA2_P" IOSTANDARD = LVDS_25;
+NET "DCOA2_P" LOC = C22;
+NET "DCOA3_N" DIFF_TERM = "TRUE";
+NET "DCOA3_N" IOSTANDARD = LVDS_25;
+NET "DCOA3_N" LOC = P20;
+NET "DCOA3_P" DIFF_TERM = "TRUE";
+NET "DCOA3_P" IOSTANDARD = LVDS_25;
+NET "DCOA3_P" LOC = P19;
+NET "DCOA4_N" DIFF_TERM = "TRUE";
+NET "DCOA4_N" IOSTANDARD = LVDS_25;
+NET "DCOA4_N" LOC = Y9;
+NET "DCOA4_P" DIFF_TERM = "TRUE";
+NET "DCOA4_P" IOSTANDARD = LVDS_25;
+NET "DCOA4_P" LOC = AA9;
+NET "DCOB1_N" DIFF_TERM = "TRUE";
+NET "DCOB1_N" IOSTANDARD = LVDS_25;
+NET "DCOB1_N" LOC = B19;
+NET "DCOB1_P" DIFF_TERM = "TRUE";
+NET "DCOB1_P" IOSTANDARD = LVDS_25;
+NET "DCOB1_P" LOC = A19;
+NET "DCOB2_N" DIFF_TERM = "TRUE";
+NET "DCOB2_N" IOSTANDARD = LVDS_25;
+NET "DCOB2_N" LOC = E20;
+NET "DCOB2_P" DIFF_TERM = "TRUE";
+NET "DCOB2_P" IOSTANDARD = LVDS_25;
+NET "DCOB2_P" LOC = D20;
+NET "DCOB3_N" DIFF_TERM = "TRUE";
+NET "DCOB3_N" IOSTANDARD = LVDS_25;
+NET "DCOB3_N" LOC = V22;
+NET "DCOB3_P" DIFF_TERM = "TRUE";
+NET "DCOB3_P" IOSTANDARD = LVDS_25;
+NET "DCOB3_P" LOC = W22;
+NET "DCOB4_N" DIFF_TERM = "TRUE";
+NET "DCOB4_N" IOSTANDARD = LVDS_25;
+NET "DCOB4_N" LOC = AA8;
+NET "DCOB4_P" DIFF_TERM = "TRUE";
+NET "DCOB4_P" IOSTANDARD = LVDS_25;
+NET "DCOB4_P" LOC = AA7;
+
+NET "FRA1_N" DIFF_TERM = "TRUE";
+NET "FRA1_N" IOSTANDARD = LVDS_25;
+NET "FRA1_N" LOC = C15;
+NET "FRA1_P" DIFF_TERM = "TRUE";
+NET "FRA1_P" IOSTANDARD = LVDS_25;
+NET "FRA1_P" LOC = B15;
+NET "FRA2_N" DIFF_TERM = "TRUE";
+NET "FRA2_N" IOSTANDARD = LVDS_25;
+NET "FRA2_N" LOC = G20;
+NET "FRA2_P" DIFF_TERM = "TRUE";
+NET "FRA2_P" IOSTANDARD = LVDS_25;
+NET "FRA2_P" LOC = H20;
+NET "FRA3_N" DIFF_TERM = "TRUE";
+NET "FRA3_N" IOSTANDARD = LVDS_25;
+NET "FRA3_N" LOC = R17;
+NET "FRA3_P" DIFF_TERM = "TRUE";
+NET "FRA3_P" IOSTANDARD = LVDS_25;
+NET "FRA3_P" LOC = P18;
+NET "FRA4_N" DIFF_TERM = "TRUE";
+NET "FRA4_N" IOSTANDARD = LVDS_25;
+NET "FRA4_N" LOC = U9;
+NET "FRA4_P" DIFF_TERM = "TRUE";
+NET "FRA4_P" IOSTANDARD = LVDS_25;
+NET "FRA4_P" LOC = V10;
+NET "FRB1_N" DIFF_TERM = "TRUE";
+NET "FRB1_N" IOSTANDARD = LVDS_25;
+NET "FRB1_N" LOC = E15;
+NET "FRB1_P" DIFF_TERM = "TRUE";
+NET "FRB1_P" IOSTANDARD = LVDS_25;
+NET "FRB1_P" LOC = D15;
+NET "FRB2_N" DIFF_TERM = "TRUE";
+NET "FRB2_N" IOSTANDARD = LVDS_25;
+NET "FRB2_N" LOC = F22;
+NET "FRB2_P" DIFF_TERM = "TRUE";
+NET "FRB2_P" IOSTANDARD = LVDS_25;
+NET "FRB2_P" LOC = F21;
+NET "FRB3_N" DIFF_TERM = "TRUE";
+NET "FRB3_N" IOSTANDARD = LVDS_25;
+NET "FRB3_N" LOC = T22;
+NET "FRB3_P" DIFF_TERM = "TRUE";
+NET "FRB3_P" IOSTANDARD = LVDS_25;
+NET "FRB3_P" LOC = R21;
+NET "FRB4_N" DIFF_TERM = "TRUE";
+NET "FRB4_N" IOSTANDARD = LVDS_25;
+NET "FRB4_N" LOC = AB10;
+NET "FRB4_P" DIFF_TERM = "TRUE";
+NET "FRB4_P" IOSTANDARD = LVDS_25;
+NET "FRB4_P" LOC = AB11;
+
+NET "GCLK_N" DIFF_TERM = "TRUE";
+NET "GCLK_N" IOSTANDARD = LVDS_25;
+NET "GCLK_N" LOC = U13;
+NET "GCLK_P" DIFF_TERM = "TRUE";
+NET "GCLK_P" IOSTANDARD = LVDS_25;
+NET "GCLK_P" LOC = T13;
+
+
+NET "INTCOM0_N" LOC = "A6";
+NET "INTCOM0_P" LOC = "A7";
+NET "INTCOM1_N" LOC = "B6";
+NET "INTCOM1_P" LOC = "C6";
+NET "INTCOM2_N" LOC = "H10";
+NET "INTCOM2_P" LOC = "G10";
+NET "INTCOM3_N" LOC = "D9";
+NET "INTCOM3_P" LOC = "E9";
+NET "INTCOM4_N" LOC = "G9";
+NET "INTCOM4_P" LOC = "F9";
+NET "INTCOM5_N" LOC = "E6";
+NET "INTCOM5_P" LOC = "E7";
+NET "INTCOM6_N" LOC = "F11";
+NET "INTCOM6_P" LOC = "E11";
+NET "INTCOM7_N" LOC = "F7";
+NET "INTCOM7_P" LOC = "F8";
+
+NET "INTCOMC1_N" LOC = "C7";
+#NET "INTCOMC1_N" DIFF_TERM = "TRUE";
+#NET "INTCOMC1_N" IOSTANDARD = BLVDS_25;
+NET "INTCOMC1_P" LOC = "C8";
+#NET "INTCOMC1_P" DIFF_TERM = "TRUE";
+#NET "INTCOMC1_P" IOSTANDARD = BLVDS_25;
+NET "INTCOMC2_N" LOC = "D7";
+#NET "INTCOMC2_N" DIFF_TERM = "TRUE";
+#NET "INTCOMC2_N" IOSTANDARD = BLVDS_25;
+NET "INTCOMC2_P" LOC = "D8";
+#NET "INTCOMC2_P" DIFF_TERM = "TRUE";
+#NET "INTCOMC2_P" IOSTANDARD = BLVDS_25;
+
+
+NET "TCK_F" LOC = "AA14";
+NET "TDI_F" LOC = "AB16";
+NET "TDO_F" LOC = "AB15";
+NET "TMS_F" LOC = "AB14";
+
+
+
+#
+#NET "SM0_N" LOC = "B11";
+#NET "SM0_P" LOC = "C11";
+NET "SM1_N" LOC = "B9";
+NET "SM1_P" LOC = "A9";
+#NET "SM2_N" LOC = "E10";
+#NET "SM2_P" LOC = "D10";
+NET "SM3_N" LOC = "B8";
+NET "SM3_P" LOC = "A8";
+#
+#
+#NET "TEMP_IN" LOC = "U14";
+#NET "TEMP_OUT" LOC = "T14";
+#
+#NET "RX_N" LOC = "T2";
+#NET "RX_P" LOC = "T1";
+#NET "TX_N" LOC = "V2";
+#NET "TX_P" LOC = "V1";
+NET "MOD_DEF[0]" LOC = G8;
+NET "MOD_DEF[1]" LOC = H8;
+NET "MOD_DEF[2]" LOC = D12;
+NET "TX_DIS" LOC = H11;
+NET "LOS" LOC = C12;
+
+NET "MGTREFCLK_N" LOC = L3;
+NET "MGTREFCLK_P" LOC = L4;
+NET "RCV_CLK_N" LOC = Y15;
+NET "RCV_CLK_P" LOC = W15;
+NET "ST_CLK_N" LOC = G6;
+NET "ST_CLK_P" LOC = F6;
+NET "RX_N" LOC = G4;
+NET "RX_P" LOC = G3;
+NET "TX_N" LOC = K2;
+NET "TX_P" LOC = K1;
+
+#NET "PROGRAM_B" LOC = F5;
+
+#
+#NET "XRX0_N" LOC = "E4";
+#NET "XRX0_P" LOC = "E3";
+#NET "XRX1_N" LOC = "C4";
+#NET "XRX1_P" LOC = "C3";
+#NET "XTX0_N" LOC = "H2";
+#NET "XTX0_P" LOC = "H1";
+#NET "XTX1_N" LOC = "F2";
+#NET "XTX1_P" LOC = "F1";
+#Created by Constraints Editor (xc6vlx130t-ff484-3) - 2012/07/23
+#NET "DCOA1_P" TNM_NET = DCOA1_P;
+#TIMESPEC TS_DCOA1_P = PERIOD "DCOA1_P" 3.125 ns HIGH 50%;
+#NET "DCOA2_P" TNM_NET = DCOA2_P;
+#TIMESPEC TS_DCOA2_P = PERIOD "DCOA2_P" 3.125 ns HIGH 50%;
+#NET "DCOA3_P" TNM_NET = DCOA3_P;
+#TIMESPEC TS_DCOA3_P = PERIOD "DCOA3_P" 3.125 ns HIGH 50%;
+#NET "DCOA4_P" TNM_NET = DCOA4_P;
+#TIMESPEC TS_DCOA4_P = PERIOD "DCOA4_P" 3.125 HIGH 50%;
+#NET "DCOB1_P" TNM_NET = DCOB1_P;
+#TIMESPEC TS_DCOB1_P = PERIOD "DCOB1_P" 3.125 ns HIGH 50%;
+#NET "DCOB2_P" TNM_NET = DCOB2_P;
+#TIMESPEC TS_DCOB2_P = PERIOD "DCOB2_P" 3.125 ns HIGH 50%;
+#NET "DCOB3_P" TNM_NET = DCOB3_P;
+#TIMESPEC TS_DCOB3_P = PERIOD "DCOB3_P" 3.125 ns HIGH 50%;
+#NET "DCOB4_P" TNM_NET = DCOB4_P;
+#TIMESPEC TS_DCOB4_P = PERIOD "DCOB4_P" 3.125 ns HIGH 50%;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXSKEW = 100 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXDELAY = 500 ps;
+
+#390
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" MAXDELAY = 750 ps;
+
+# half of real frequency because of synchronisation with falling edge
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv";
+#TIMESPEC TS_AdcToplevel1458_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" 12.5 ns HIGH 50 %;
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv";
+#TIMESPEC TS_AdcToplevel2356_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" 12.5 ns HIGH 50 %;
+#
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv";
+#TIMESPEC TS_AdcToplevel1458_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" 12.5 ns HIGH 50 %;
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv";
+#TIMESPEC TS_AdcToplevel2356_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" 12.5 ns HIGH 50 %;
+#
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv";
+#TIMESPEC TS_AdcToplevel1458_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" 12.5 ns HIGH 50 %;
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv";
+#TIMESPEC TS_AdcToplevel2356_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" 12.5 ns HIGH 50 %;
+#
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv";
+#TIMESPEC TS_AdcToplevel1458_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" 12.5 ns HIGH 50 %;
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv";
+#TIMESPEC TS_AdcToplevel2356_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" 12.5 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";
+TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";
+TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";
+TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";
+TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";
+TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";
+TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";
+TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";
+TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;
+
+
+#NET "ADC_clk_S" TNM_NET = "ADC_clk_S";
+#TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;
+#NET "ADC_clk_S" MAXDELAY = 1.6 ns;
+#NET "ADC_clk_S" MAXSKEW = 1.6 ns;
+#NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "FEE_ADCinput_module1/ADC_clknot_S";
+#TIMESPEC TS_clknot_S = PERIOD "FEE_ADCinput_module1/ADC_clknot_S" 12.5 ns HIGH 50 %;
+#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.6 ns;
+#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1.6 ns;
+#
+#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#
+#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S_clk";
+TIMESPEC TS_ADC_clk_S_clk = PERIOD "ADC_clk_S_clk" 12.5 ns HIGH 50 %;
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S_net";
+NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_clk";
+TIMESPEC TS_ADC_clknot_S_clk = PERIOD "ADC_clknot_S_clk" 12.5 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_net";
+
+NET "ADC_clk_S" MAXDELAY = 1.6 ns;
+NET "ADC_clk_S" MAXSKEW = 1 ns;
+NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.4 ns;
+NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1 ns;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_per";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_per";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_per";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_per";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_per";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_per";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_per";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_per";
+
+TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_per = PERIOD "IntClkDiv1458_1_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_per = PERIOD "IntClkDiv1458_2_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_per = PERIOD "IntClkDiv1458_3_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_per = PERIOD "IntClkDiv1458_4_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_per = PERIOD "IntClkDiv2356_1_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_per = PERIOD "IntClkDiv2356_2_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_per = PERIOD "IntClkDiv2356_3_per" 12.5 ns HIGH 50 %;
+TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_per = PERIOD "IntClkDiv2356_4_per" 12.5 ns HIGH 50 %;
+
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_net";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_net";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_net";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_net";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_net";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_net";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_net";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_net";
+
+TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_net = FROM "IntClkDiv1458_1_net" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_net = FROM "IntClkDiv1458_2_net" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_net = FROM "IntClkDiv1458_3_per" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_net = FROM "IntClkDiv1458_4_per" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_net = FROM "IntClkDiv2356_1_per" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_net = FROM "IntClkDiv2356_2_per" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_net = FROM "IntClkDiv2356_3_per" TO "ADC_clknot_S_net" 4 ns;
+TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_net = FROM "IntClkDiv2356_4_per" TO "ADC_clknot_S_net" 4 ns;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXSKEW = 250 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXDELAY = 850 ps;
+
+
+NET "FEE_ADCinput_module1/FRA1_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA1_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA2_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA2_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA3_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA3_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA4_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA4_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB1_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB1_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB2_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB2_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB3_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB3_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB4_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB4_N_S" MAXDELAY = 20 ps;
+
+NET "ST_CLK_P" TNM_NET = "ST_CLK_P";
+TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;
+NET "ST_CLK_N" TNM_NET = "ST_CLK_N";
+TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;
+
+INST "*AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds";
+INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrm_Isrds";
+INST "*AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcDat_Isrds";
+INST "*AdcClock/*" TNM = FFS "AdcClk_Ffs";
+INST "*AdcFrame/*" TNM = FFS "AdcFrm_Ffs";
+INST "*AdcData/*" TNM = FFS "AdcDat_Ffs";
+TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 2.4 ns;
+TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 2.4 ns;
+TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 2.4 ns;
+
+NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_clk";
+TIMESPEC TS_clock_ADCref_S_clk = PERIOD "clock_ADCref_S_clk" 12.5 ns HIGH 50 %;
+NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_net";
+
+NET "ST_CLK_S" TNM_NET = "ST_CLK_S_clk";
+TIMESPEC TS_ST_CLK_S_clk = PERIOD "ST_CLK_S_clk" 6.43 ns HIGH 50 %;
+NET "ST_CLK_S" TNM_NET = "ST_CLK_S_net";
+
+NET "GCLK_S" TNM_NET = "GCLK_S_clk";
+TIMESPEC TS_GCLK_S_clk = PERIOD "GCLK_S_clk" 12.5 ns HIGH 50 %;
+NET "GCLK_S" TNM_NET = "GCLK_S_net";
+
+#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";
+#TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;
+#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S_net";
+
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S";
+TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S_net";
+
+
+TIMESPEC TS_ADC_to_ADC = FROM "clock_ADCref_S_net" TO "clock_ADCref_S_net" 12.5 ns;
+TIMESPEC TS_ST_to_ST = FROM "ST_CLK_S_net" TO "ST_CLK_S_net" 6.43 ns;
+TIMESPEC TS_G_to_G = FROM "GCLK_S_net" TO "GCLK_S_net" 12.5 ns;
+TIMESPEC TS_SODA_to_SODA = FROM "rxSodaClk_S_net" TO "rxSodaClk_S_net" 6.25 ns;
+
+
+TIMESPEC TS_ADC_to_ST = FROM "clock_ADCref_S_net" TO "ST_CLK_S_net" TIG;
+TIMESPEC TS_ST_to_ADC = FROM "ST_CLK_S_net" TO "clock_ADCref_S_net" TIG;
+TIMESPEC TS_G_to_ST = FROM "GCLK_S_net" TO "ST_CLK_S_net" TIG;
+TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S_net" TO "ST_CLK_S_net" TIG;
+TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S_net" TO "GCLK_S_net" TIG;
+TIMESPEC TS_SODA_to_ADC = FROM "rxSodaClk_S_net" TO "clock_ADCref_S_net" TIG;
+
+#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";
+#NET "GCLK_S" TNM_NET = "GCLK_S";
+#NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S";
+##NET "clock125Mhz_S" TNM_NET = "clock125MHz_S";
+#NET "clock200Mhz_S" TNM_NET = "clock200MHz_S";
+##NET "clock100Mhz_S" TNM_NET = "clock100MHz_S";
+#
+##TIMESPEC TS_125M_to_ref = FROM "clock125MHz_S" TO "clock_ADCref_S" TIG;
+##TIMESPEC TS_ref_to_125M = FROM "clock_ADCref_S" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_GCLK_to_ref = FROM "GCLK_S" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_ref_to_GCLK = FROM "clock_ADCref_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_GCLK_to_125M = FROM "GCLK_S" TO "clock125MHz_S" TIG;
+##TIMESPEC TS_125M_to_GCLK = FROM "clock125MHz_S" TO "GCLK_S" TIG;
+#
+#
+##TIMESPEC TS_62M5_to_100M = FROM "clock62M5Hz_S" TO "clock100MHz_S" TIG;
+##TIMESPEC TS_100M_to_62M5 = FROM "clock100MHz_S" TO "clock62M5Hz_S" TIG;
+##TIMESPEC TS_125M_to_100M = FROM "clock125MHz_S" TO "clock100MHz_S" TIG;
+##TIMESPEC TS_100M_to_125M = FROM "clock100MHz_S" TO "clock125MHz_S" TIG;
+#
+#TIMESPEC TS_ref_to_200M = FROM "clock62M5Hz_S" TO "clock200MHz_S" TIG;
+#TIMESPEC TS_200M_to_ref = FROM "clock200MHz_S" TO "clock62M5Hz_S" TIG;
+#TIMESPEC TS_GCLK_to_200M = FROM "GCLK_S" TO "clock200MHz_S" TIG;
+#TIMESPEC TS_200M_to_GCLK = FROM "clock200MHz_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_200M = FROM "clock125MHz_S" TO "clock200MHz_S" TIG;
+##TIMESPEC TS_200M_to_125M = FROM "clock200MHz_S" TO "clock125MHz_S" TIG;
+#
+#TIMESPEC TS_ref_to_ST_CLK = FROM "clock_ADCref_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_ref = FROM "ST_CLK_S" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_GCLK_to_ST_CLK = FROM "GCLK_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_GCLK = FROM "ST_CLK_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_ST_CLK = FROM "clock125MHz_S" TO "ST_CLK_S" TIG;
+##TIMESPEC TS_ST_CLK_to_125M = FROM "ST_CLK_S" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_200M_to_ST_CLK = FROM "clock200MHz_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_200M = FROM "ST_CLK_S" TO "clock200MHz_S" TIG;
+#
+#NET "ST_CLK_S_BUFG" TNM_NET = "ST_CLK_S_BUFG";
+#TIMESPEC TS_ref_to_ST_CLK_BUFG = FROM "clock_ADCref_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_ref = FROM "ST_CLK_S_BUFG" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_GCLK_to_ST_CLK_BUFG = FROM "GCLK_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_GCLK = FROM "ST_CLK_S_BUFG" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_ST_CLK_BUFG = FROM "clock125MHz_S" TO "ST_CLK_S_BUFG" TIG;
+##TIMESPEC TS_ST_CLK_BUFG_to_125M = FROM "ST_CLK_S_BUFG" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_200M_to_ST_CLK_BUFG = FROM "clock200MHz_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_200M = FROM "ST_CLK_S_BUFG" TO "clock200MHz_S" TIG;
+
+#TIMESPEC TS_62M5_to_txUsrClk2 = FROM "clock62M5Hz_S" TO "FEE_gtxModule1/txUsrClk2_S" 20 ns;
+#TIMESPEC TS_txUsrClk2_to_62M5 = FROM "FEE_gtxModule1/txUsrClk2_S" TO "clock62M5Hz_S" 20 ns;
+
+NET "GCLK_P" TNM_NET = "GCLK_P";
+TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;
+NET "GCLK_N" TNM_NET = "GCLK_N";
+TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;
+
+NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
+TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;
+NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
+TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;
+
+NET "FEE_gtxModule1/txUsrClk_S" TNM_NET = "FEE_gtxModule1/txUsrClk_S";
+TIMESPEC TS_FEE_gtxModule1_txUsrClk_S = PERIOD "FEE_gtxModule1/txUsrClk_S" 5 ns HIGH 50 %;
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" 5 ns HIGH 50 %;
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" TNM_NET = FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S;
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" 12.5 ns HIGH 50%;
+#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i/gtx0_gtxVirtex6FEE_i/gtxe1_i LOC=GTXE1_X0Y12;
+#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i LOC=GTXE1_X0Y12;
+
+#TIMESPEC TS_RXCLK_to_TXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/txUsrClk2_S" 3 ns;
+#TIMESPEC TS_TXCLK_to_RXCLK = FROM "FEE_gtxModule1/txUsrClk2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;
+#TIMESPEC TS_RXCLK_to_TXCLK0 = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" 3 ns;
+#TIMESPEC TS_TXCLK0_to_RXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;
+
+
+NET "GEO" IOSTANDARD = LVCMOS25;
+#NET "GEO" DRIVE = 12;
+NET "GEO" SLEW = SLOW;
+NET "GEO" PULLUP;
+net "GEO" TIG;
+#NET "S_CTRL" TIG;
+#NET "T_CTRL_S" TIG;
+
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_A1;
+#AREA_GROUP "pblock_adc_A1" RANGE=SLICE_X30Y140:SLICE_X35Y159;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_B1;
+#AREA_GROUP "pblock_adc_B1" RANGE=SLICE_X30Y120:SLICE_X35Y139;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_A2;
+#AREA_GROUP "pblock_adc_A2" RANGE=SLICE_X0Y120:SLICE_X5Y139;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_B2;
+#AREA_GROUP "pblock_adc_B2" RANGE=SLICE_X0Y140:SLICE_X5Y159;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_A3;
+#AREA_GROUP "pblock_adc_A3" RANGE=SLICE_X0Y100:SLICE_X5Y119;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_B3;
+#AREA_GROUP "pblock_adc_B3" RANGE=SLICE_X0Y80:SLICE_X5Y99;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_A4;
+#AREA_GROUP "pblock_adc_A4" RANGE=SLICE_X64Y100:SLICE_X69Y119;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_B4;
+#AREA_GROUP "pblock_adc_B4" RANGE=SLICE_X64Y80:SLICE_X69Y99;
+
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_1;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_1;
+AREA_GROUP "pblock_adc_1" RANGE=SLICE_X30Y120:SLICE_X35Y159;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_2;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_2;
+AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y120:SLICE_X5Y159;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_3;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_3;
+AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y80:SLICE_X5Y119;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_4;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_4;
+AREA_GROUP "pblock_adc_4" RANGE=SLICE_X64Y80:SLICE_X69Y119;
+
+
diff --git a/FEE_ADC32board/project/FEE_ADC32board.xise b/FEE_ADC32board/project/FEE_ADC32board.xise
new file mode 100644
index 0000000..dbe2747
--- /dev/null
+++ b/FEE_ADC32board/project/FEE_ADC32board.xise
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diff --git a/FEE_ADC32board/project/FEE_ADC32board_top.vhd b/FEE_ADC32board/project/FEE_ADC32board_top.vhd
new file mode 100644
index 0000000..b4e936e
--- /dev/null
+++ b/FEE_ADC32board/project/FEE_ADC32board_top.vhd
@@ -0,0 +1,2184 @@
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+library work;
+use work.panda_package.all;
+--use work.panda_pkg.all;
+
+entity top is
+ Port (
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ GCLK_P : in std_logic; -- clock equal to GTX refclock (62.5MHz or 80MHz)
+ GCLK_N : in std_logic;
+
+ ST_CLK_P : in std_logic; -- 155.52MHz
+ ST_CLK_N : in std_logic;
+
+
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+
+----ADCconfiguration---------------------------------------------
+ SCK : out std_logic;
+ SDI : out std_logic;
+ CSA : out std_logic_vector(1 to 4);
+ CSB : out std_logic_vector(1 to 4);
+ SDOA : inout std_logic_vector(1 to 4);
+ SDOB : inout std_logic_vector(1 to 4);
+
+----GTX---------------------------------------------
+ MOD_DEF : in std_logic_vector(2 downto 0);
+ LOS : in std_logic;
+ TX_DIS : out std_logic;
+ MGTREFCLK_P : in std_logic;
+ MGTREFCLK_N : in std_logic;
+
+ RX_P : in std_logic;
+ RX_N : in std_logic;
+ TX_P : out std_logic;
+ TX_N : out std_logic;
+
+----PLL---------------------------------------------
+
+ S_CTRL : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG
+ T_CTRL : out std_logic; -- T_CTRL from FPGA1<>FPGA2 : FPGA1 controls PLL&JTAG
+
+ RDu : in std_logic;
+ CLKu : out std_logic;
+ DATAu : out std_logic;
+ LEu : out std_logic;
+ SYNC : out std_logic;
+ RCV_CLK_P : out std_logic; -- ref clock for PLL LMK03806
+ RCV_CLK_N : out std_logic;
+
+----TMP104---------------------------------------------
+-- TEMP_IN : out std_logic;
+-- TEMP_OUT : in std_logic;
+
+----test---------------------------------------------
+ SM1_P : out std_logic;
+ SM1_N : out std_logic;
+ SM3_P : in std_logic;
+ SM3_N : in std_logic;
+
+ INTCOMC1_P : inout std_logic;
+ INTCOMC1_N : inout std_logic;
+ INTCOMC2_P : inout std_logic;
+ INTCOMC2_N : inout std_logic;
+
+ INTCOM0_P : inout std_logic;
+ INTCOM0_N : inout std_logic;
+ INTCOM1_P : inout std_logic;
+ INTCOM1_N : inout std_logic;
+ INTCOM2_P : inout std_logic;
+ INTCOM2_N : inout std_logic;
+ INTCOM3_P : inout std_logic;
+ INTCOM3_N : inout std_logic;
+ INTCOM4_P : inout std_logic;
+ INTCOM4_N : inout std_logic;
+ INTCOM5_P : inout std_logic;
+ INTCOM5_N : inout std_logic;
+ INTCOM6_P : inout std_logic;
+ INTCOM6_N : inout std_logic;
+ INTCOM7_P : inout std_logic;
+ INTCOM7_N : inout std_logic;
+
+ TCK_F : in std_logic;
+ TDI_F : in std_logic;
+ TDO_F : in std_logic;
+ TMS_F : in std_logic
+-- PROGRAM_B : inout std_logic
+
+
+-- D : in std_logic_VECTOR (7 downto 0)
+ );
+end top;
+
+
+
+architecture Behavioral of top is
+
+component clockmodule80M
+port (
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component clock155to200MHz
+port(
+ CLK_IN1 : in std_logic;
+ CLK_IN2 : in std_logic;
+ CLK_IN_SEL : in std_logic;
+ CLK_OUT1 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component clockmodule80to80M
+port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic;
+ CLK_OUT3 : out std_logic;
+ CLK_OUT4 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component clockmodule40to80
+port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component clockmodule40switch
+port(
+ CLK_IN1 : in std_logic;
+ CLK_IN2 : in std_logic;
+ CLK_IN_SEL : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component LMK03806 is
+ generic(
+ CLK_DIV : integer := 6; -- slow down transfer
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY
+ );
+ PORT(
+ clock : in std_logic; --Master clock
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDn : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high
+ reset_GTX : out std_logic; --delayed reset for GTX
+ reset_ADCs : out std_logic; --delayed reset for ADCs
+ booting : out std_logic; --busy signal
+ testwordin : in std_logic_vector(15 downto 0)
+ );
+end component;
+
+component FEE_ADCinput_module is
+ port (
+ clock200MHz : in std_logic;
+ reset : in std_logic;
+ ADCs_enable : in std_logic;
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+ ADC_clk : out std_logic;
+ ADCs_ready : out std_logic;
+ adcdata : out array_adc_type
+ );
+end component;
+
+component FEE_adc32_module is
+ generic (
+ NROFADCS : natural := NROFADCS;
+ ADCBITS : natural := 14;
+ BASELINE_BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY;
+ CF_DELAYBITS : natural := 4;
+ CF_FRACTIONBIT : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable_data : in std_logic;
+ ADCdata : in array_adc_type;
+ superburst_start : in std_logic;
+ superburst_received : in std_logic_vector(30 downto 0);
+ onesecondpulse : in std_logic;
+ rxNotInTable : in std_logic;
+ startupready : in std_logic;
+ request_init : in std_logic;
+ packet_in_data : in std_logic_vector (31 downto 0);
+ packet_in_present : in std_logic;
+ packet_in_read : out std_logic;
+ packet_out_data : out std_logic_vector(31 downto 0);
+ packet_out_last : out std_logic;
+ packet_out_write : out std_logic;
+ packet_out_fifofull : in std_logic;
+ errorbyte_out : out std_logic_vector(7 downto 0);
+ errorbyte_in : in std_logic_vector(7 downto 0);
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ sysmon_data : in std_logic_vector(15 downto 0);
+ sysmon_reset : out std_logic;
+ sysmon_address : out std_logic_vector(6 downto 0);
+ sysmon_read : out std_logic;
+ testindex : in integer range 0 to NROFADCS/2-1;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_gtxModule is
+ generic(
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY -- 80000000 -- 62500000
+ );
+ Port (
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncDataRead : in std_logic;
+ rxNotInTable : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component soda_FEE_endpoint is
+ generic(
+ SODA_16BIT_INTERFACE : boolean := FALSE
+ );
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic;
+ TX_DLM_OUT : out std_logic;
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+
+
+ START_OF_SUPERBURST : out std_logic := '0';
+ SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_VALID : out std_logic := '0';
+ SODA_CMD_WORD : out std_logic_vector(30 downto 0) := (others => '0');
+
+ STAT : out std_logic_vector(31 downto 0) := (others => '0') -- DEBUG
+ );
+end component;
+
+component SystemMonitorModule is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(6 downto 0);
+ data_write : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ data_read : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ alarms : out std_logic_vector(7 downto 0);
+ testword0 : out std_logic_vector(35 downto 0));
+end component;
+
+component posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component posedge_async_to_pulse is
+ port (
+ clock_out : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component icon0
+ port (
+ CONTROL0 : inout std_logic_vector(35 downto 0);
+ CONTROL1 : inout std_logic_vector(35 downto 0);
+ CONTROL2 : inout std_logic_vector(35 downto 0);
+ CONTROL3 : inout std_logic_vector(35 downto 0);
+ CONTROL4 : inout std_logic_vector(35 downto 0));
+end component;
+
+component ila36
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(35 downto 0));
+end component;
+
+component ila128
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(127 downto 0));
+end component;
+
+component vio36
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ ASYNC_OUT : out std_logic_vector(35 downto 0));
+end component;
+
+attribute keep : string;
+constant DEBUG : boolean := false;
+-- clocking
+signal ST_CLK_S : std_logic;
+attribute keep of ST_CLK_S : signal is "TRUE";
+signal clock_ADCrefdiv2_S : std_logic;
+signal clock_ADCref_S : std_logic; -- 62.5 or 80 MHz
+attribute keep of clock_ADCref_S : signal is "TRUE";
+signal clock100MHz_S : std_logic;
+signal clock200MHz_S : std_logic;
+signal clock80MHz_PLL1_S : std_logic;
+signal GCLK_S : std_logic;
+attribute keep of GCLK_S : signal is "TRUE";
+signal gtpClk_S : std_logic;
+signal RCV_CLK_P_S : std_logic;
+signal RCV_CLK_S : std_logic;
+signal RCV_CLK_not_S : std_logic;
+signal RCV_CLKref_S : std_logic;
+signal RCV_CLKrx_S : std_logic;
+signal ADC_clk_S : std_logic;
+attribute keep of ADC_clk_S : signal is "TRUE";
+signal txUsrClk_S : std_logic;
+
+
+signal clockPLL1_locked_S : std_logic;
+signal clockPLL2_reset_S : std_logic;
+signal clockmodule_locked_S : std_logic;
+signal clockswitch_locked_S : std_logic;
+
+-- resetting
+signal coldstart_counter_S : std_logic_vector(7 downto 0) := (others => '0');
+signal coldstart_S : std_logic := '0';
+signal reset_S : std_logic := '0';
+signal reset_FEE_S : std_logic := '0';
+signal reset_FEE_ADCclk_S : std_logic := '0';
+signal resetting_S : std_logic := '0';
+signal resetting_stclk_S : std_logic := '0';
+signal IcontrolPLL_S : std_logic := '0';
+signal otherFPGAnotconfigured0_S : std_logic := '0';
+signal otherFPGAnotconfigured_S : std_logic := '0';
+signal PLLconfigured_S : std_logic := '0';
+signal startupready_S : std_logic := '0';
+signal selectPLLclk_S : std_logic := '0';
+signal selectPLLclk_stclk_S : std_logic := '0';
+signal disable_GTX_reset_S : std_logic := '0';
+signal GEO_S : std_logic := '0';
+signal GEO_stclk_S : std_logic := '0';
+signal T_CTRL_S : std_logic := '0';
+signal S_CTRL0_S : std_logic := '0';
+signal phaseSYNC_S : std_logic := '0';
+signal boot_PLL_S : std_logic := '0';
+signal PLL_booting_S : std_logic := '0';
+signal adcintrfcena_s : std_logic := '0';
+signal reset_ADCs_S : std_logic := '0';
+signal ADCs_enable_S : std_logic := '0';
+signal reset_GTX_S : std_logic := '0';
+signal reset_counter_S : integer range 0 to 65535 := 0;
+signal timeout_counter_S : integer range 0 to 65535 := 0;
+signal external_sync_out_S : std_logic := '0';
+signal external_sync_in0_S : std_logic := '0';
+signal external_sync_in_S : std_logic := '0';
+signal reset_rxSodaClk_S : std_logic;
+signal ADCs_ready_S : std_logic;
+
+
+-- SODA
+signal EnableDataTaking_S : std_logic := '0';
+signal DisableDataTaking_S : std_logic := '0';
+signal enable_data_S : std_logic := '0';
+signal DataTaking_enabled_out_S : std_logic := '0';
+signal DataTaking_enabled_in_S : std_logic := '0';
+signal SODA_cmd_valid_S : std_logic := '0';
+signal SODA_cmd_word_S : std_logic_vector(30 downto 0);
+signal superburst_out_S : std_logic_vector(30 downto 0);
+signal superburst_in_S : std_logic_vector(30 downto 0);
+signal superburst_start0_S : std_logic;
+signal superburst_start1_S : std_logic;
+signal superburst_start_S : std_logic;
+signal superburst_startout0_S : std_logic;
+signal superburst_startout_S : std_logic;
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal RX_DLM_S : std_logic;
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
+
+-- fiber data
+signal packet_in_data_S : std_logic_vector(31 downto 0);
+signal packet_out_data_S : std_logic_vector(31 downto 0) := (others => '0');
+signal packet_in_present_S : std_logic := '0';
+signal packet_in_read_S : std_logic := '0';
+signal packet_out_last_S : std_logic := '0';
+signal packet_out_write_S : std_logic := '0';
+signal packet_out_fifofull_S : std_logic := '0';
+signal rxNotInTable0_S : std_logic;
+signal rxNotInTable_S : std_logic;
+
+
+-- clock check
+signal GCLKdiv10_S : std_logic := '0';
+signal GCLKdiv10_prev1_S : std_logic := '0';
+signal GCLKdiv10_prev2_S : std_logic := '0';
+signal PLLfrequencyERROR_S : std_logic := '0';
+
+-- lmk03806
+signal CLKu_S : std_logic := '0';
+signal DATAu_S : std_logic := '0';
+signal LEu_S : std_logic := '0';
+signal SYNC_S : std_logic := '0';
+signal SYNC0_S : std_logic := '0';
+signal SYNC1_S : std_logic := '0';
+signal SYNC2_S : std_logic := '0';
+signal debug_sync_S : std_logic := '0';
+
+-- ADCs
+signal adcdata_S : array_adc_type;
+
+-- GTX
+signal LOS_S : std_logic;
+signal rxSodaClk_S : std_logic;
+attribute keep of rxSodaClk_S : signal is "TRUE";
+signal rxSodaClk40_S : std_logic;
+signal rxSodaClk40b_S : std_logic;
+signal rxSodaClk80_S : std_logic;
+signal rxLocked_S : std_logic;
+signal rxLocked0_S : std_logic;
+signal rxLocked_sync_S : std_logic;
+
+-- phasedet
+signal phasedet_S : std_logic;
+signal GCLKdiv2_S : std_logic;
+signal GCLKdiv4_S : std_logic;
+signal rxSodaClkdiv4_S : std_logic;
+signal phaseerr_max_S : integer range 0 to 1023 := 0;
+signal phasedet_count_S : integer range 0 to 1023 := 0;
+signal phaseerr_count_S : integer range 0 to 1023 := 0;
+signal phasecheck_ready_S : std_logic := '0';
+signal phasecheck_ready1_S : std_logic := '0';
+signal phaseSYNCpulse_S : std_logic := '0';
+signal phasecheckcounter_S : integer range 0 to 255 := 0;
+
+
+-- timestamp reset
+--signal ResetToZero_S : std_logic;
+signal onesecondpulse_S : std_logic;
+
+signal SYNC_stclk_S : std_logic;
+signal SYNC_stclk2_S : std_logic;
+signal SYNC_adcclk_S : std_logic;
+signal SYNC_adcclk2_S : std_logic;
+signal SYNC_soda_S : std_logic;
+signal SYNC_soda2_S : std_logic;
+
+-- system monitor
+signal sysmon_data_S : std_logic_vector(15 downto 0);
+signal sysmon_reset_S : std_logic;
+signal sysmon_address_S : std_logic_vector(6 downto 0);
+signal sysmon_read_S : std_logic;
+
+-- test compare feature extraction results
+constant SECOND_FE_MODULE : boolean := false;
+signal adcdata2_S : array_adc_type;
+signal request_init_S : std_logic := '0';
+signal reset_FEE_ADCclk2_S : std_logic := '0';
+signal reset_FEE_ADCclk2a_S : std_logic := '0';
+signal packet_out_data2_S : std_logic_vector(31 downto 0);
+signal packet_in_read2_S : std_logic;
+signal packet_out_last2_S : std_logic;
+signal packet_out_write2_S : std_logic;
+signal unequal_counter_S : std_logic_vector(31 downto 0) := (others => '0');
+signal unequal_time_S : std_logic_vector(31 downto 0) := (others => '0');
+signal zero_data_S : std_logic;
+signal unequal_S : std_logic;
+signal errorbyte_S : std_logic_vector(7 downto 0) := (others => '0');
+
+
+-- test
+signal control0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control1_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control2_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control3_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control4_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0a_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0b_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testwordb_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword2_S : std_logic_vector(127 downto 0) := (others => '0');
+signal vioword_S : std_logic_vector(35 downto 0) := (others => '0');
+signal vioword2_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testwordA0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testwordB0_S : std_logic_vector(35 downto 0) := (others => '0');
+
+signal selectnr_S : integer range 0 to 3 := 0;
+signal testclockDiv2_S : std_logic_vector(7 downto 0) := (others => '0');
+signal forced_reset_S : std_logic := '0';
+signal test_resetadc_s : std_logic := '0';
+signal testclocks_S : std_logic_vector(8 downto 0) := (others => '0');
+signal testclockDiv100_S : std_logic_vector(8 downto 0) := (others => '0');
+
+begin
+-- GEO=0:this is FPGA1, GEO=1:this is FPGA2
+-- S_CTRL=1 : FPGA1 controls PLL&JTAG
+-- S_CTRL=0 : FPGA2 controls PLL&JTAG
+
+-- T_CTRL1 T_CTRL2 PLL_controlled_by S_CTRL
+-- 0 0 0 = FPGA2 0
+-- 1 0 1 = FPGA1 1
+-- 0 1 1 = FPGA1 1
+-- 1 1 0 = FPGA2 0
+
+IcontrolPLL_S <= '1' when (GEO/=S_CTRL) else '0'; -- '1' when this FPGA controls the PLL
+
+coldstartprocess: process(ST_CLK_S)
+begin
+ if rising_edge(ST_CLK_S) then
+ if coldstart_counter_S/=x"ff" then
+ coldstart_S <= '0';
+ coldstart_counter_S <= coldstart_counter_S+1;
+ else
+ coldstart_S <= '1';
+ end if;
+ end if;
+end process;
+
+
+T_CTRL <= T_CTRL_S;
+T_CTRL_S <=
+ coldstart_S when GEO='1' -- PLL_controlled_by FPGA2
+ else '0' when PLLconfigured_S='0' -- PLL_controlled_by FPGA1 during booting
+ else '1'; -- PLL_controlled_by FPGA2, but reference frequency from FPGA1
+PLLconfigured_S <= '1' when (PLL_booting_S='0') and (resetting_S='0') else '0';
+process(clock_ADCref_S)
+begin
+ if rising_edge(clock_ADCref_S) then
+ if GEO='0' then
+ if T_CTRL_S=S_CTRL then
+ if otherFPGAnotconfigured0_S='1' then
+ otherFPGAnotconfigured_S <= '1';
+ end if;
+ otherFPGAnotconfigured0_S <= '1';
+ else
+ otherFPGAnotconfigured0_S <= '0';
+ otherFPGAnotconfigured_S <= '0';
+ end if;
+ else
+ otherFPGAnotconfigured0_S <= '0';
+ otherFPGAnotconfigured_S <= '0';
+ end if;
+ end if;
+end process;
+
+sysclk_buf : IBUFGDS
+ port map ( I => GCLK_P,
+ IB => GCLK_N,
+ O => GCLK_S);
+ST_CLK_buf : IBUFGDS
+ port map ( I => ST_CLK_P,
+ IB => ST_CLK_N,
+ O => ST_CLK_S);
+
+clockmodule80Ma: clockmodule80M port map(
+ CLK_IN1 => ST_CLK_S,
+ CLK_OUT1 => clock80MHz_PLL1_S,
+ LOCKED => clockPLL1_locked_S);
+clockmodule80to80Ma: clockmodule80to80M port map(
+ CLK_IN1 => clock80MHz_PLL1_S,
+ CLK_OUT1 => clock_ADCrefdiv2_S, -- 40MHz
+ CLK_OUT2 => clock_ADCref_S, -- 80MHz
+ CLK_OUT3 => clock100MHz_S,
+ CLK_OUT4 => clock200MHz_S,
+ RESET => clockPLL2_reset_S,
+ LOCKED => clockmodule_locked_S);
+clockPLL2_reset_S <= '1' when clockPLL1_locked_S='0' else '0';
+
+
+reset_S <= '1' when (clockmodule_locked_S='0') or (forced_reset_S='1') else '0';
+resetprocess: process(clock_ADCref_S,reset_S,GEO)
+variable resetFEE_count_V : integer range 0 to 16 := 0;
+begin
+ if reset_S='1' then
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';
+ resetting_S <= '1';
+ rxLocked_sync_S <= '0';
+ GEO_S <= GEO;
+ resetFEE_count_V := 0;
+ reset_FEE_S <= '1';
+ disable_GTX_reset_S <= '0';
+ elsif rising_edge(clock_ADCref_S) then
+ rxLocked_sync_S <= rxLocked_S;
+ if resetFEE_count_V<16 then
+ resetFEE_count_V := resetFEE_count_V+1;
+ reset_FEE_S <= '1';
+ else
+ reset_FEE_S <= '0';
+ end if;
+ GEO_S <= GEO;
+ if GEO_S='0' then -- FPGA1
+ if ((PLLfrequencyERROR_S='1') and (selectPLLclk_S='1')) or (otherFPGAnotconfigured_S='1') then -- restart all
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';
+ resetting_S <= '1';
+ startupready_S <= '0';
+ disable_GTX_reset_S <= '0';
+ elsif reset_counter_S=1000 then -- start PLL boot
+ reset_counter_S <= reset_counter_S+1;
+ boot_PLL_S <= '1';
+ timeout_counter_S <= 0;
+ elsif reset_counter_S=1002 then -- wait for PLL boot finished
+ boot_PLL_S <= '0';
+ if PLL_booting_S='1' then
+ if timeout_counter_S<65535 then
+ timeout_counter_S <= timeout_counter_S+1;
+ else
+ timeout_counter_S <= 0;
+ end if;
+ else
+ reset_counter_S <= reset_counter_S+1;
+ timeout_counter_S <= 0;
+ end if;
+ elsif reset_counter_S=10000 then -- reset GTX
+ resetting_S <= '0';
+ reset_GTX_S <= '1';
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=10001 then -- wait for rx-locked
+ resetting_S <= '0';
+ startupready_S <= '0';
+ reset_GTX_S <= '0';
+ if rxLocked_sync_S='1' then
+ reset_counter_S <= reset_counter_S+1;
+ end if;
+ elsif reset_counter_S=11000 then -- disable resetting in GTX
+ disable_GTX_reset_S <= '1';
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=11010 then -- switch reference clock
+ startupready_S <= '1';
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=11080 then -- enable resetting in GTX
+ disable_GTX_reset_S <= '0';
+ reset_counter_S <= reset_counter_S+1;
+ else
+ if reset_counter_S/=65535 then
+ reset_counter_S <= reset_counter_S+1;
+ else -- final state
+ resetting_S <= '0';
+ startupready_S <= '1';
+ end if;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '0';
+ end if;
+ else -- GEO=1
+ disable_GTX_reset_S <= '0';
+ if (S_CTRL0_S='1') or (otherFPGAnotconfigured_S='1') then
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';
+ resetting_S <= '1';
+ startupready_S <= '0';
+ elsif reset_counter_S=10000 then -- reset GTX
+ resetting_S <= '0';
+ reset_GTX_S <= '1';
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=10001 then -- wait for rx-locked
+ resetting_S <= '0';
+ startupready_S <= '0';
+ reset_GTX_S <= '0';
+ if rxLocked_sync_S='1' then
+ reset_counter_S <= reset_counter_S+1;
+ end if;
+ elsif reset_counter_S=11000 then -- switch reference clock
+ startupready_S <= '1';
+ reset_counter_S <= reset_counter_S+1;
+ else
+ if reset_counter_S/=65535 then
+ reset_counter_S <= reset_counter_S+1;
+ else
+ resetting_S <= '0';
+ startupready_S <= '1';
+ end if;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '0';
+ if startupready_S='1' then
+ if rxLocked_sync_S='0' then
+ end if;
+ end if;
+ end if;
+ end if;
+ S_CTRL0_S <= S_CTRL;
+ end if;
+end process;
+
+ -- ICAP_VIRTEX6: Internal Configuration Access Port
+ -- Virtex-6
+ -- Xilinx HDL Language Template, version 13.3
+
+-- ICAP_VIRTEX6_inst : ICAP_VIRTEX6
+-- generic map (
+-- DEVICE_ID => X"4244093", -- Specifies the pre-programmed Device ID value
+-- ICAP_WIDTH => "X8", -- Specifies the input and output data width to be used with the
+-- -- ICAP_VIRTEX6.
+-- SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
+-- -- model
+-- )
+-- port map (
+-- BUSY => BUSY, -- 1-bit output: Busy/Ready output
+-- O => O, -- 32-bit output: Configuration data output bus
+-- CLK => CLK, -- 1-bit input: Clock Input
+-- CSB => CSB, -- 1-bit input: Active-Low ICAP input Enable
+-- I => I, -- 32-bit input: Configuration data input bus
+-- RDWRB => RDWRB -- 1-bit input: Read/Write Select input
+-- );
+
+resync_pulse1: posedge_to_pulse port map(
+ clock_in => ST_CLK_S,
+ clock_out => ST_CLK_S, -- clock_ADCref_S,
+ en_clk => '1',
+ signal_in => phaseSYNC_S,
+ pulse => phaseSYNCpulse_S);
+
+syncpulse_proc: process(ST_CLK_S)
+variable synccount_V : integer range 0 to 15 := 0;
+begin
+ if rising_edge(ST_CLK_S) then
+ if synccount_V<15 then
+ synccount_V := synccount_V+1;
+ external_sync_out_S <= '1';
+ else
+ external_sync_out_S <= '0';
+ if (phaseSYNCpulse_S='1') then
+ synccount_V := 0;
+ end if;
+ end if;
+ end if;
+end process;
+
+ADCresetprocess: process(clock_ADCref_S)
+variable adcreset_counter_V : integer range 0 to 65535 := 0;
+begin
+ if rising_edge(clock_ADCref_S) then
+ if (resetting_S='1') or ((PLL_booting_S='1') and (GEO_S='0')) or (startupready_S='0') or
+ (test_resetADC_S='1') or (external_sync_out_S='1') or (external_sync_in_S='1') or
+ ((phasecheck_ready1_S='0') and (GEO_S='0')) or
+ ((rxLocked_sync_S='0') and (GEO_S='0'))
+ then
+ reset_ADCs_S <= '1';
+ AdcIntrfcEna_S <= '0';
+ adcreset_counter_V := 0;
+ elsif adcreset_counter_V=65335 then -- wait for lock
+ if rxLocked_sync_S='1' then
+ adcreset_counter_V := adcreset_counter_V+1;
+ reset_ADCs_S <= '0';
+ end if;
+ elsif adcreset_counter_V=65535 then
+ reset_ADCs_S <= '0';
+ AdcIntrfcEna_S <= '1';
+ else
+ adcreset_counter_V := adcreset_counter_V+1;
+ end if;
+ if GEO='1' then
+ external_sync_in_S <= external_sync_in0_S;
+ else
+ external_sync_in_S <= '0';
+ end if;
+ if (SYNC0_S='0') or (external_sync_in_S='1') or (debug_sync_S='1') then
+ SYNC1_S <= '1';
+ else
+ SYNC1_S <= '0';
+ end if;
+ phasecheck_ready1_S <= phasecheck_ready_S;
+ end if;
+end process;
+
+
+--syncbuf1: IOBUFDS
+-- generic map (
+-- IOSTANDARD => "BLVDS_25"
+-- )
+-- port map (
+-- O => external_sync_in0_S, -- Buffer output
+-- IO => INTCOMC1_P, -- Diff_p inout (connect directly to top-level port)
+-- IOB => INTCOMC1_N, -- Diff_n inout (connect directly to top-level port)
+-- I => external_sync_out_S, -- Buffer input
+-- T => GEO -- 3-state enable input, high=input, low=output
+-- );
+--
+--startsuperburst1: IOBUFDS
+-- generic map (
+-- IOSTANDARD => "BLVDS_25"
+-- )
+-- port map (
+-- O => superburst_start0_S,
+-- IO => INTCOMC2_P,
+-- IOB => INTCOMC2_N,
+-- I => superburst_startout_S,
+-- T => GEO
+-- );
+
+IOBUF1 : IOBUF port map (
+ O => external_sync_in0_S, -- Buffer output
+ IO => INTCOMC1_P, -- Buffer inout port (connect directly to top-level port)
+ I => external_sync_out_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ );
+
+IOBUF2 : IOBUF port map (
+ O => superburst_start0_S, -- Buffer output
+ IO => INTCOMC1_N, -- Buffer inout port (connect directly to top-level port)
+ I => superburst_startout_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ );
+
+IOBUF3 : IOBUF port map (
+ O => DataTaking_enabled_in_S, -- Buffer output
+ IO => INTCOMC2_N, -- Buffer inout port (connect directly to top-level port)
+ I => DataTaking_enabled_out_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ );
+
+--INTCOMC1_P <= external_sync_out_S when GEO='0' else 'Z';
+--external_sync_in0_S <= INTCOMC1_P;
+--INTCOMC1_N <= superburst_startout_S when GEO='0' else 'Z';
+--superburst_start0_S <= INTCOMC1_N;
+--INTCOMC2_N <= DataTaking_enabled_out_S when GEO='0' else 'Z';
+--DataTaking_enabled_in_S <= INTCOMC2_N;
+
+
+process(ADC_clk_S,startupready_S)
+variable enable_data_V : std_logic := '0';
+variable DataTaking_enabled_V : std_logic := '0';
+begin
+ if (startupready_S='0') then
+ enable_data_V := '0';
+ enable_data_S <= '0';
+ elsif (rising_edge(ADC_clk_S)) then
+ enable_data_S <= DataTaking_enabled_V;
+ DataTaking_enabled_V := DataTaking_enabled_in_S;
+ end if;
+end process;
+
+process(ADC_clk_S)
+begin
+ if (rising_edge(ADC_clk_S)) then
+ superburst_start1_S <= superburst_start0_S;
+ end if;
+end process;
+
+sync_startofsuperburst: posedge_to_pulse port map(
+ clock_in => ADC_clk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => superburst_start1_S,
+ pulse => superburst_start_S);
+
+INTCOM0_P <= superburst_out_S(0) when GEO='0' else 'Z';
+INTCOM0_N <= superburst_out_S(1) when GEO='0' else 'Z';
+INTCOM1_P <= superburst_out_S(2) when GEO='0' else 'Z';
+INTCOM1_N <= superburst_out_S(3) when GEO='0' else 'Z';
+INTCOM2_P <= superburst_out_S(4) when GEO='0' else 'Z';
+INTCOM2_N <= superburst_out_S(5) when GEO='0' else 'Z';
+INTCOM3_P <= superburst_out_S(6) when GEO='0' else 'Z';
+INTCOM3_N <= superburst_out_S(7) when GEO='0' else 'Z';
+INTCOM4_P <= superburst_out_S(8) when GEO='0' else 'Z';
+INTCOM4_N <= superburst_out_S(9) when GEO='0' else 'Z';
+INTCOM5_P <= superburst_out_S(10) when GEO='0' else 'Z';
+INTCOM5_N <= superburst_out_S(11) when GEO='0' else 'Z';
+INTCOM6_P <= superburst_out_S(12) when GEO='0' else 'Z';
+INTCOM6_N <= superburst_out_S(13) when GEO='0' else 'Z';
+INTCOM7_P <= superburst_out_S(14) when GEO='0' else 'Z';
+INTCOM7_N <= superburst_out_S(15) when GEO='0' else 'Z';
+
+superburst_in_S(0) <= INTCOM0_P;
+superburst_in_S(1) <= INTCOM0_N;
+superburst_in_S(2) <= INTCOM1_P;
+superburst_in_S(3) <= INTCOM1_N;
+superburst_in_S(4) <= INTCOM2_P;
+superburst_in_S(5) <= INTCOM2_N;
+superburst_in_S(6) <= INTCOM3_P;
+superburst_in_S(7) <= INTCOM3_N;
+superburst_in_S(8) <= INTCOM4_P;
+superburst_in_S(9) <= INTCOM4_N;
+superburst_in_S(10) <= INTCOM5_P;
+superburst_in_S(11) <= INTCOM5_N;
+superburst_in_S(12) <= INTCOM6_P;
+superburst_in_S(13) <= INTCOM6_N;
+superburst_in_S(14) <= INTCOM7_P;
+superburst_in_S(15) <= INTCOM7_N;
+superburst_in_S(30 downto 16) <= (others => '0');
+
+sync_SYNC_stclk_S: posedge_to_pulse port map(
+ clock_in => clock_ADCref_S,
+ clock_out => ST_CLK_S,
+ en_clk => '1',
+ signal_in => SYNC1_S,
+ pulse => SYNC2_S);
+
+SYNC <= not SYNC2_S;
+
+
+process(rxSodaClk40_S)
+begin
+ if (rising_edge(rxSodaClk40_S)) then
+ rxSodaClkdiv4_S <= not rxSodaClkdiv4_S;
+ end if;
+end process;
+process(GCLK_S)
+begin
+ if (rising_edge(GCLK_S)) then
+ if GCLKdiv2_S='1' then
+ GCLKdiv4_S <= not GCLKdiv4_S;
+ end if;
+ GCLKdiv2_S <= not GCLKdiv2_S;
+ end if;
+end process;
+phaseerr_max_S <= 50 when vioword_S(23 downto 16)=x"00" else conv_integer(unsigned(vioword_S(23 downto 16)));
+phasedet_S <= '1' when GCLKdiv4_S/=rxSodaClkdiv4_S else '0';
+process(ST_CLK_S)
+variable waitcounter_V : integer range 0 to 155520 := 0;
+begin
+ if (rising_edge(ST_CLK_S)) then
+ if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
+ waitcounter_V := 0;
+ phasedet_count_S <= 0;
+ phaseerr_count_S <= 0;
+ phasecheckcounter_S <= 0;
+ phaseSYNC_S <= '0';
+ elsif (waitcounter_V<155520) then -- *(1+conv_integer(unsigned(vioword_S(27 downto 24))))) then
+ waitcounter_V := waitcounter_V+1;
+ phasedet_count_S <= 0;
+ phaseerr_count_S <= 0;
+ phasecheckcounter_S <= 0;
+ phaseSYNC_S <= '0';
+ elsif (waitcounter_V=155520) then -- always one syncpulse
+ waitcounter_V := waitcounter_V+1;
+ phasedet_count_S <= 0;
+ phaseerr_count_S <= 0;
+ phasecheckcounter_S <= 0;
+ phaseSYNC_S <= '1';
+ else
+ if phasedet_count_S=1023 then
+ if phasecheckcounter_S<255 then
+ phasecheck_ready_S <= '0';
+ phasecheckcounter_S <= phasecheckcounter_S+1;
+ if (phaseerr_count_S>phaseerr_max_S) then
+ if vioword_S(5)='0' then
+ phaseSYNC_S <= '1';
+ waitcounter_V := 0;
+ else
+ phaseSYNC_S <= '0';
+ end if;
+ else
+ phaseSYNC_S <= '0';
+ end if;
+ else
+ phasecheck_ready_S <= '1';
+ if (phaseerr_count_S>200) then
+-- if (phaseerr_count_S>400) then
+ if vioword_S(5)='0' then
+ phaseSYNC_S <= '1';
+ waitcounter_V := 0;
+ else
+ phaseSYNC_S <= '0';
+ end if;
+ else
+ phaseSYNC_S <= '0';
+ end if;
+ end if;
+ phasedet_count_S <= 0;
+ if phasedet_S='1' then
+ phaseerr_count_S <= 1;
+ else
+ phaseerr_count_S <= 0;
+ end if;
+ else
+ phaseSYNC_S <= '0';
+ phasedet_count_S <= phasedet_count_S+1;
+ if phasedet_S='1' then
+ phaseerr_count_S <= phaseerr_count_S+1;
+ end if;
+ end if;
+ end if;
+ resetting_stclk_S <= resetting_S;
+ selectPLLclk_stclk_S <= selectPLLclk_S;
+ GEO_stclk_S <= GEO;
+ end if;
+end process;
+
+
+gclk_div10_process: process(GCLK_S)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+ if (rising_edge(GCLK_S)) then
+ if counter_V<49 then -- 99 for 125MHz
+ counter_V := counter_V+1;
+ else
+ counter_V := 0;
+ GCLKdiv10_S <= not GCLKdiv10_S;
+ end if;
+ end if;
+end process;
+checkfrequency_process: process(ST_CLK_S)
+variable counter_V : integer range 0 to 255 := 0;
+variable first_check_V : integer range 0 to 7 := 0;
+begin
+ if (rising_edge(ST_CLK_S)) then
+ if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
+ PLLfrequencyERROR_S <= '0';
+ first_check_V := 0;
+ else
+ if GCLKdiv10_prev1_S/=GCLKdiv10_prev2_S then
+ if (((counter_V>=122) or (counter_V<=125)) and (ADCCLOCKFREQUENCY=62500000)) or
+ (((counter_V>=96) or (counter_V<=99)) and (ADCCLOCKFREQUENCY=80000000)) then
+ PLLfrequencyERROR_S <= '0';
+ if first_check_V/=7 then
+ first_check_V := first_check_V+1;
+ end if;
+ else
+ if first_check_V=7 then
+ PLLfrequencyERROR_S <= '1';
+ first_check_V := 0;
+ else
+ first_check_V := first_check_V+1;
+ end if;
+ end if;
+ counter_V := 0;
+ elsif counter_V<255 then
+ counter_V := counter_V+1;
+ end if;
+ end if;
+ GCLKdiv10_prev2_S <= GCLKdiv10_prev1_S;
+ GCLKdiv10_prev1_S <= GCLKdiv10_S;
+ end if;
+end process;
+
+external_PLL: LMK03806 port map(
+ clock => clock_ADCref_S,
+ CLKu => CLKu_S,
+ DATAu => DATAu_S,
+ LEu => LEu_S,
+ RDn => RDu,
+ SYNC => SYNC0_S,
+ boot_PLL => boot_PLL_S,
+ reset_GTX => open, -- reset_GTX_S,
+ reset_ADCs => open, -- reset_ADCs0_S,
+ booting => PLL_booting_S,
+ testwordin => vioword2_S(15 downto 0));
+CLKu <= CLKu_S;
+DATAu <= DATAu_S;
+LEu <= LEu_S;
+
+-- ADC configuration --------------------------------------------------------------
+ SCK <= '0'; -- 2-lane 16-bits serialization
+ SDI <= '0'; -- normal mode (not sleeping)
+ CSA <= (others => '0'); -- 2-lane 16-bits serialization
+ CSB <= (others => '0'); -- 2-lane 16-bits serialization
+ SDOA <= (others => '0'); -- no internal termination
+ SDOB <= (others => '0'); -- no internal termination
+
+
+
+GTX_refclock: IBUFDS_GTXE1 port map(
+ O => gtpClk_S,
+ ODIV2 => open,
+ CEB => '0',
+ I => MGTREFCLK_P,
+ IB => MGTREFCLK_N);
+
+--select_RCV_CLK : BUFGMUX_CTRL port map(
+-- O => RCV_CLK_S,
+-- I0 => clock_ADCref_S,
+-- I1 => rxSodaClk80_S,
+-- S => selectPLLclk_S); ---- rxLocked_S);
+--RCV_CLK_S <= clock_ADCref_S;
+process (clock_ADCref_S)
+begin
+ if (rising_edge(clock_ADCref_S)) then
+ if vioword_S(11)='0' then
+ if (startupready_S='1') and (rxLocked_S='1') then
+ selectPLLclk_S <= '1';
+ else
+ selectPLLclk_S <= '0';
+ end if;
+ else
+ selectPLLclk_S <= vioword_S(10); --//
+ end if;
+ end if;
+end process;
+
+--rxRecClk40_BUFG: BUFG port map(
+-- I => rxSodaClk40_S,
+-- O => rxSodaClk40b_S);
+--clockmodule40to80_1: clockmodule40to80 port map(
+-- CLK_IN1 => rxSodaClk40b_S,
+-- CLK_OUT1 => rxSodaClk80_S,
+-- LOCKED => open);
+
+clockmodule40switch1: clockmodule40switch port map(
+ CLK_IN1 => rxSodaClk40_S,
+ CLK_IN2 => clock_ADCrefdiv2_S,
+ CLK_IN_SEL => selectPLLclk_S,
+ CLK_OUT1 => RCV_CLK_S,
+ CLK_OUT2 => open,
+ RESET => '0',
+ LOCKED => clockswitch_locked_S);
+
+--process (clock_ADCref_S)
+--begin
+-- if (rising_edge(clock_ADCref_S)) then
+-- RCV_CLKref_S <= not RCV_CLKref_S;
+-- end if;
+--end process;
+--process (rxSodaClk80_S)
+--begin
+-- if (rising_edge(rxSodaClk80_S)) then
+-- RCV_CLKrx_S <= not RCV_CLKrx_S;
+-- end if;
+--end process;
+--RCV_CLK_S <= RCV_CLKrx_S when selectPLLclk_S='1' else RCV_CLKref_S;
+--
+--U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
+-- I => RCV_CLK_S,
+-- O => RCV_CLK_P,
+-- OB => RCV_CLK_N);
+
+
+RCV_CLK_not_S <= not RCV_CLK_S;
+U1 : FDDRRSE port map(
+ Q => RCV_CLK_P_S,
+ C0 => RCV_CLK_S,
+ C1 => RCV_CLK_not_S,
+ CE => '1', -- 1 for fpga1 not GEO, --
+ D0 => '1', -- 1 for fpga1 not GEO, --
+ D1 => '0',
+ R => '0',
+ S => '0');
+U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
+ I => RCV_CLK_P_S,
+ O => RCV_CLK_P,
+ OB => RCV_CLK_N);
+
+
+
+LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
+TX_DIS <= '0'; -- SFP always enabled
+
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+ if (rising_edge(ADC_clk_S)) then
+ reset_FEE_ADCclk_S <= reset_FEE_S;
+ ADCs_enable_S <= AdcIntrfcEna_S;
+ end if;
+end process;
+
+FEE_ADCinput_module1: FEE_ADCinput_module port map(
+ clock200MHz => clock200MHz_S,
+ reset => reset_ADCs_S,
+ ADCs_enable => ADCs_enable_S,
+----ADC1---------------------------------------------
+ AD11A_P => AD11A_P,
+ AD11A_N => AD11A_N,
+ AD11B_P => AD11B_P,
+ AD11B_N => AD11B_N,
+ AD12A_P => AD12A_P,
+ AD12A_N => AD12A_N,
+ AD12B_P => AD12B_P,
+ AD12B_N => AD12B_N,
+ AD13A_P => AD13A_P,
+ AD13A_N => AD13A_N,
+ AD13B_P => AD13B_P,
+ AD13B_N => AD13B_N,
+ AD14A_P => AD14A_P,
+ AD14A_N => AD14A_N,
+ AD14B_P => AD14B_P,
+ AD14B_N => AD14B_N,
+ AD15A_P => AD15A_P,
+ AD15A_N => AD15A_N,
+ AD15B_P => AD15B_P,
+ AD15B_N => AD15B_N,
+ AD16A_P => AD16A_P,
+ AD16A_N => AD16A_N,
+ AD16B_P => AD16B_P,
+ AD16B_N => AD16B_N,
+ AD17A_P => AD17A_P,
+ AD17A_N => AD17A_N,
+ AD17B_P => AD17B_P,
+ AD17B_N => AD17B_N,
+ AD18A_P => AD18A_P,
+ AD18A_N => AD18A_N,
+ AD18B_P => AD18B_P,
+ AD18B_N => AD18B_N,
+
+ DCOA1_P => DCOA1_P,
+ DCOA1_N => DCOA1_N,
+ DCOB1_P => DCOB1_P,
+ DCOB1_N => DCOB1_N,
+
+ FRA1_P => FRA1_P ,
+ FRA1_N => FRA1_N ,
+ FRB1_P => FRB1_P ,
+ FRB1_N => FRB1_N ,
+
+ ----ADC2---------------------------------------------
+ AD21A_P => AD21A_P,
+ AD21A_N => AD21A_N,
+ AD21B_P => AD21B_P,
+ AD21B_N => AD21B_N,
+ AD22A_P => AD22A_P,
+ AD22A_N => AD22A_N,
+ AD22B_P => AD22B_P,
+ AD22B_N => AD22B_N,
+ AD23A_P => AD23A_P,
+ AD23A_N => AD23A_N,
+ AD23B_P => AD23B_P,
+ AD23B_N => AD23B_N,
+ AD24A_P => AD24A_P,
+ AD24A_N => AD24A_N,
+ AD24B_P => AD24B_P,
+ AD24B_N => AD24B_N,
+ AD25A_P => AD25A_P,
+ AD25A_N => AD25A_N,
+ AD25B_P => AD25B_P,
+ AD25B_N => AD25B_N,
+ AD26A_P => AD26A_P,
+ AD26A_N => AD26A_N,
+ AD26B_P => AD26B_P,
+ AD26B_N => AD26B_N,
+ AD27A_P => AD27A_P,
+ AD27A_N => AD27A_N,
+ AD27B_P => AD27B_P,
+ AD27B_N => AD27B_N,
+ AD28A_P => AD28A_P,
+ AD28A_N => AD28A_N,
+ AD28B_P => AD28B_P,
+ AD28B_N => AD28B_N,
+
+ DCOA2_P => DCOA2_P,
+ DCOA2_N => DCOA2_N,
+ DCOB2_P => DCOB2_P,
+ DCOB2_N => DCOB2_N,
+
+ FRA2_P => FRA2_P ,
+ FRA2_N => FRA2_N ,
+ FRB2_P => FRB2_P ,
+ FRB2_N => FRB2_N ,
+
+ ----ADC3---------------------------------------------
+ AD31A_P => AD31A_P,
+ AD31A_N => AD31A_N,
+ AD31B_P => AD31B_P,
+ AD31B_N => AD31B_N,
+ AD32A_P => AD32A_P,
+ AD32A_N => AD32A_N,
+ AD32B_P => AD32B_P,
+ AD32B_N => AD32B_N,
+ AD33A_P => AD33A_P,
+ AD33A_N => AD33A_N,
+ AD33B_P => AD33B_P,
+ AD33B_N => AD33B_N,
+ AD34A_P => AD34A_P,
+ AD34A_N => AD34A_N,
+ AD34B_P => AD34B_P,
+ AD34B_N => AD34B_N,
+ AD35A_P => AD35A_P,
+ AD35A_N => AD35A_N,
+ AD35B_P => AD35B_P,
+ AD35B_N => AD35B_N,
+ AD36A_P => AD36A_P,
+ AD36A_N => AD36A_N,
+ AD36B_P => AD36B_P,
+ AD36B_N => AD36B_N,
+ AD37A_P => AD37A_P,
+ AD37A_N => AD37A_N,
+ AD37B_P => AD37B_P,
+ AD37B_N => AD37B_N,
+ AD38A_P => AD38A_P,
+ AD38A_N => AD38A_N,
+ AD38B_P => AD38B_P,
+ AD38B_N => AD38B_N,
+
+ DCOA3_P => DCOA3_P,
+ DCOA3_N => DCOA3_N,
+ DCOB3_P => DCOB3_P,
+ DCOB3_N => DCOB3_N,
+
+ FRA3_P => FRA3_P ,
+ FRA3_N => FRA3_N ,
+ FRB3_P => FRB3_P ,
+ FRB3_N => FRB3_N ,
+
+ ----ADC4---------------------------------------------
+ AD41A_P => AD41A_P,
+ AD41A_N => AD41A_N,
+ AD41B_P => AD41B_P,
+ AD41B_N => AD41B_N,
+ AD42A_P => AD42A_P,
+ AD42A_N => AD42A_N,
+ AD42B_P => AD42B_P,
+ AD42B_N => AD42B_N,
+ AD43A_P => AD43A_P,
+ AD43A_N => AD43A_N,
+ AD43B_P => AD43B_P,
+ AD43B_N => AD43B_N,
+ AD44A_P => AD44A_P,
+ AD44A_N => AD44A_N,
+ AD44B_P => AD44B_P,
+ AD44B_N => AD44B_N,
+ AD45A_P => AD45A_P,
+ AD45A_N => AD45A_N,
+ AD45B_P => AD45B_P,
+ AD45B_N => AD45B_N,
+ AD46A_P => AD46A_P,
+ AD46A_N => AD46A_N,
+ AD46B_P => AD46B_P,
+ AD46B_N => AD46B_N,
+ AD47A_P => AD47A_P,
+ AD47A_N => AD47A_N,
+ AD47B_P => AD47B_P,
+ AD47B_N => AD47B_N,
+ AD48A_P => AD48A_P,
+ AD48A_N => AD48A_N,
+ AD48B_P => AD48B_P,
+ AD48B_N => AD48B_N,
+
+ DCOA4_P => DCOA4_P,
+ DCOA4_N => DCOA4_N,
+ DCOB4_P => DCOB4_P,
+ DCOB4_N => DCOB4_N,
+
+ FRA4_P => FRA4_P ,
+ FRA4_N => FRA4_N ,
+ FRB4_P => FRB4_P ,
+ FRB4_N => FRB4_N ,
+
+ ADC_clk => ADC_clk_S,
+ ADCs_ready => ADCs_ready_S,
+ adcdata => adcdata_S
+ );
+
+gen_FEE: if DEBUG=false generate
+FEE_module1: FEE_adc32_module port map(
+ clock => ADC_clk_S,
+ reset => reset_FEE_ADCclk_S,
+ enable_data => enable_data_S,
+ ADCdata => adcdata_S,
+ superburst_start => superburst_start_S,
+ superburst_received => superburst_in_S,
+ onesecondpulse => onesecondpulse_S,
+ rxNotInTable => rxNotInTable_S,
+ startupready => startupready_S,
+ request_init => request_init_S,
+ packet_in_data => packet_in_data_S,
+ packet_in_present => packet_in_present_S,
+ packet_in_read => packet_in_read_S,
+ packet_out_data => packet_out_data_S,
+ packet_out_last => packet_out_last_S,
+ packet_out_write => packet_out_write_S,
+ packet_out_fifofull => packet_out_fifofull_S,
+ errorbyte_out => errorbyte_S,
+ errorbyte_in => errorbyte_S,
+ smaart_in => '0', -- TEMP_OUT,
+ smaart_out => open,
+ sysmon_data => sysmon_data_S,
+ sysmon_reset => sysmon_reset_S,
+ sysmon_address => sysmon_address_S,
+ sysmon_read => sysmon_read_S,
+ testindex => conv_integer(unsigned(vioword_S(15 downto 12))),
+ testword0 => open,
+ testword1 => open,
+ testword2 => open
+ ); -- TEMP_IN);
+end generate;
+
+gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
+
+
+ FEE_module2: FEE_adc32_module port map(
+ clock => ADC_clk_S,
+ reset => reset_FEE_ADCclk2_S,
+ enable_data => enable_data_S,
+ ADCdata => adcdata2_S,
+ superburst_start => superburst_start_S,
+ superburst_received => superburst_in_S,
+ onesecondpulse => onesecondpulse_S,
+ rxNotInTable => rxNotInTable_S,
+ startupready => startupready_S,
+ request_init => request_init_S,
+ packet_in_data => packet_in_data_S,
+ packet_in_present => packet_in_present_S,
+ packet_in_read => packet_in_read2_S,
+ packet_out_data => packet_out_data2_S,
+ packet_out_last => packet_out_last2_S,
+ packet_out_write => packet_out_write2_S,
+ packet_out_fifofull => packet_out_fifofull_S,
+ errorbyte_out => open,
+ errorbyte_in => errorbyte_S,
+ smaart_in => '0', -- TEMP_OUT,
+ smaart_out => open,
+ sysmon_data => sysmon_data_S,
+ sysmon_reset => open,
+ sysmon_address => open,
+ sysmon_read => open,
+ testindex => conv_integer(unsigned(vioword_S(15 downto 12))),
+ testword0 => open,
+ testword1 => testword0b_S, -- testword0_S,
+ testword2 => open
+ ); -- TEMP_IN);
+
+ reset_FEE_ADCclk2_S <= '1' when (reset_FEE_ADCclk_S='1') or (reset_FEE_ADCclk2a_S='1') else '0';
+ zero_data_S <= '1' when (vioword_S(9)='1') else '0';
+ adcdata2_S <= adcdata_S when zero_data_S='0' else (others => (others => '0'));
+
+ process(ADC_clk_S)
+ begin
+ if (rising_edge(ADC_clk_S)) then
+ unequal_S <= '0';
+ request_init_S <= '0';
+ if (zero_data_S='1') or (reset_FEE_ADCclk_S='1') or (vioword_S(8)='1') then
+ unequal_counter_S <= (others => '0');
+ reset_FEE_ADCclk2a_S <= '1';
+ unequal_time_S <= (others => '0');
+ else
+ if unequal_counter_S(31 downto 0)=x"0000000f" then
+ reset_FEE_ADCclk2a_S <= '0';
+ end if;
+ if unequal_counter_S=x"000000ff" then
+ request_init_S <= '1';
+ end if;
+ if (packet_in_read2_S/=packet_in_read_S) or
+ (packet_out_data2_S/=packet_out_data_S) or
+ (packet_out_last2_S/=packet_out_last_S) or
+ (packet_out_write2_S/=packet_out_write_S) then
+ unequal_time_S <= unequal_counter_S;
+ unequal_S <= '1';
+ end if;
+ if unequal_counter_S/=x"ffffffff" then
+ unequal_counter_S <= unequal_counter_S+1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end generate;
+
+process(ADC_clk_S)
+variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
+begin
+ if (rising_edge(ADC_clk_S)) then
+ if counter/=0 then
+ counter := counter-1;
+ onesecondpulse_S <= '0';
+ else
+ counter := ADCCLOCKFREQUENCY-1;
+ onesecondpulse_S <= '1';
+ end if;
+ end if;
+end process;
+
+FEE_gtxModule1: FEE_gtxModule port map(
+ gtpClk => gtpClk_S,
+ asyncclk => clock_ADCref_S,
+ reset => reset_GTX_S,
+ disable_GTX_reset => disable_GTX_reset_S,
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ RX_DLM => RX_DLM_S,
+ RX_DLM_WORD => RX_DLM_WORD_S,
+ txAsyncClk => ADC_clk_S,
+ txAsyncData => packet_out_data_S,
+ txAsyncDataWrite => packet_out_write_S,
+ txAsyncLastData => packet_out_last_S,
+ txAsyncFifoFull => packet_out_fifofull_S,
+ txUsrClk => txUsrClk_S,
+ txLocked => open,
+ rxAsyncClk => ADC_clk_S,
+ rxAsyncData => packet_in_data_S,
+ rxAsyncDataRead => packet_in_read_S,
+ rxNotInTable => rxNotInTable0_S,
+ rxAsyncDataOverflow => open,
+ rxAsyncDataPresent => packet_in_present_S,
+ rxSodaClk => rxSodaClk_S,
+ rxSodaClk40 => rxSodaClk40_S,
+ rxLocked => rxLocked0_S,
+ gtpTxP0 => TX_P,
+ gtpTxN0 => TX_N,
+ gtpRxP0 => RX_P,
+ gtpRxN0 => RX_N,
+ testword0 => testwordb_S -- testword0(35 downto 0)
+ );
+
+posedge_to_pulse_notintable: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => rxNotInTable0_S,
+ pulse => rxNotInTable_S);
+
+rxLocked_S <= '1' when ((rxLocked0_S='1') or (disable_GTX_reset_S='1')) and (LOS_S='0') else '0';
+
+
+datatakingprocess: process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ if DisableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '0';
+ elsif EnableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '1';
+ end if;
+ end if;
+end process;
+
+
+process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ reset_rxSodaClk_S <= reset_S;
+ end if;
+end process;
+
+
+posedge_to_pulse_superburst_startout: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => superburst_startout0_S,
+ pulse => superburst_startout_S);
+
+soda_FEE_endpoint1: soda_FEE_endpoint port map(
+ SYSCLK => rxSodaClk_S,
+ RESET => reset_rxSodaClk_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+ RX_DLM_WORD_IN => RX_DLM_WORD_S,
+ RX_DLM_IN => RX_DLM_S,
+ TX_DLM_OUT => TX_DLM_S,
+ TX_DLM_WORD_OUT => TX_DLM_WORD_S,
+ START_OF_SUPERBURST => superburst_startout0_S,
+ SUPER_BURST_NR => superburst_out_S,
+ SODA_CMD_VALID => SODA_cmd_valid_S,
+ SODA_CMD_WORD => SODA_cmd_word_S,
+ STAT => open);
+--ResetToZero_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(30)='1') else '0'; -- reset timestamp to I/O pin
+EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';
+DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';
+
+SystemMonitorModule1: SystemMonitorModule port map(
+ clock => ADC_clk_S,
+ reset => sysmon_reset_S,
+ address => sysmon_address_S,
+ data_write => '0',
+ data_in => (others => '0'),
+ data_read => sysmon_read_S,
+ data_out => sysmon_data_S,
+ alarms => open,
+ testword0 => open);
+
+
+icon1: icon0 port map(
+ CONTROL0 => control0_S,
+ CONTROL1 => control1_S,
+ CONTROL2 => control2_S,
+ CONTROL3 => control3_S,
+ CONTROL4 => control4_S);
+
+ila36_1: ila36 port map(
+ CONTROL => control0_S,
+ CLK => txUsrClk_S, -- ADC_clk_S, -- ST_CLK_S,
+ TRIG0 => testword1_S); -- testword0_S
+
+ila36_2: ila36 port map(
+ CONTROL => control1_S,
+ CLK => rxSodaClk_S, -- clock_ADCref_S, -- ADC_clk_S, ,clock_ADCref_S
+ TRIG0 => testword1_S);
+
+ila128_1: ila128 port map(
+ CONTROL => control2_S,
+ CLK => clock_ADCref_S, -- ADC_clk_S,
+ TRIG0 => testword2_S); -- (others => '0')); --
+
+vio36_1: vio36 port map (
+ CONTROL => control3_S,
+ ASYNC_OUT => vioword_S);
+
+vio36_2: vio36 port map (
+ CONTROL => control4_S,
+ ASYNC_OUT => vioword2_S);
+
+--testword0_S(31 downto 0) <= unequal_time_S;
+--testword0_S(32) <= reset_FEE_ADCclk2_S;
+--testword0_S(33) <= zero_data_S;
+--testword0_S(34) <= unequal_S;
+--testword0_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';
+
+-- testword0_S <= testword0a_S when vioword_S(10)='0' else testword0b_S;
+
+testclocks_S(0) <= clock_ADCref_S;
+testclocks_S(1) <= clock_ADCrefdiv2_S;
+testclocks_S(2) <= clock100MHz_S;
+testclocks_S(3) <= clock200MHz_S;
+testclocks_S(4) <= RCV_CLK_S;
+testclocks_S(5) <= GCLK_S;
+testclocks_S(6) <= rxSodaClk_S;
+testclocks_S(7) <= rxSodaClk40_S;
+testclocks_S(8) <= ADC_clk_S;
+gen_testclocks: for i in 0 to 8 generate
+process(testclocks_S(i))
+variable cnt_V : integer range 0 to 99 := 0;
+begin
+ if (rising_edge(testclocks_S(i))) then
+ if cnt_V<99 then
+ cnt_V := cnt_V+1;
+ else
+ cnt_V := 0;
+ testclockDiv100_S(i) <= not testclockDiv100_S(i);
+ end if;
+ end if;
+end process;
+end generate;
+--testword0_S(8 downto 0) <= testclockDiv100_S;
+--testword0_S(9) <= LOS_S;
+--testword0_S(10) <= rxLocked_S;
+--testword0_S(11) <= rxLocked0_S;
+--testword0_S(12) <= rxLocked_sync_S;
+--testword0_S(13) <= selectPLLclk_S;
+--testword0_S(14) <= rxLocked_S;
+--testword0_S(23 downto 16) <= RX_DLM_WORD_S;
+--testword0_S(24) <= RX_DLM_S;
+--testword0_S(32 downto 25) <= TX_DLM_WORD_S;
+--testword0_S(33) <= TX_DLM_S;
+--testword0_S(34) <= superburst_startout_S;
+--testword0_S(35) <= SODA_cmd_valid_S;
+
+testword0_S(15 downto 0) <= superburst_out_S(15 downto 0);
+testword0_S(31 downto 16) <= superburst_in_S(15 downto 0);
+testword0_S(32) <= superburst_startout_S;
+testword0_S(33) <= superburst_start0_S;
+testword0_S(34) <= superburst_start1_S;
+testword0_S(35) <= superburst_start_S;
+
+
+--testword2_S(31 downto 0) <= unequal_time_S;
+--testword2_S(32) <= reset_FEE_ADCclk2_S;
+--testword2_S(33) <= zero_data_S;
+--testword2_S(34) <= unequal_S;
+--testword2_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';
+--testword2_S(67 downto 36) <= packet_out_data_S;
+--testword2_S(68) <= packet_out_write_S;
+--testword2_S(69) <= packet_out_last_S;
+--testword2_S(70) <= packet_out_fifofull_S;
+--testword2_S(71) <= '0';
+--testword2_S(103 downto 72) <= packet_out_data2_S;
+--testword2_S(104) <= packet_out_write2_S;
+--testword2_S(105) <= packet_out_last2_S;
+--testword2_S(106) <= packet_out_fifofull_S;
+--testword2_S(107) <= '0';
+
+testword1_S(30 downto 0) <= testwordb_S(30 downto 0);
+testword1_S(31) <= errorbyte_S(0);
+testword1_S(32) <= errorbyte_S(1);
+testword1_S(33) <= errorbyte_S(2);
+testword1_S(34) <= errorbyte_S(4);
+testword1_S(35) <= errorbyte_S(6);
+
+testword2_S(0) <= rxLocked_sync_S; -- coldstart_S;
+testword2_S(1) <= reset_S;
+testword2_S(2) <= resetting_S;
+testword2_S(3) <= reset_GTX_S; -- IcontrolPLL_S;
+testword2_S(4) <= reset_ADCs_S; -- otherFPGAnotconfigured0_S;
+testword2_S(5) <= otherFPGAnotconfigured_S;
+testword2_S(6) <= PLLconfigured_S;
+testword2_S(7) <= selectPLLclk_S;
+testword2_S(8) <= startupready_S; -- T_CTRL_S;
+testword2_S(9) <= external_sync_in_S;
+testword2_S(10) <= rxLocked_S;
+testword2_S(11) <= S_CTRL0_S;
+testword2_S(12) <= boot_PLL_S;
+testword2_S(13) <= PLL_booting_S;
+testword2_S(14) <= adcintrfcena_s;
+testword2_S(15) <= phasecheck_ready1_S;
+testword2_S(16) <= GCLKdiv4_S; --reset_GTX_S;
+testword2_S(17) <= rxSodaClkdiv4_S; --ADCs_ready_S;
+testword2_S(18) <= '1' when phasedet_count_S=1023 else '0'; --GEO;
+testword2_S(19) <= '1' when phasecheckcounter_S<255 else '0'; -- PLLfrequencyERROR_S;
+testword2_S(20) <= SYNC_S;
+testword2_S(21) <= PLLfrequencyERROR_S;
+testword2_S(22) <= phasedet_S;
+testword2_S(23) <= phaseSYNC_S;
+testword2_S(24) <= clockswitch_locked_S;
+testword2_S(25) <= phaseSYNCpulse_S;
+testword2_S(35 downto 26) <= conv_std_logic_vector(phaseerr_count_S,10);
+
+selectnr_S <= conv_integer(vioword_S(35 downto 34));
+
+generatetest1 : for index in 0 to 7 generate
+-- testword2_S(index*16+13 downto index*16+0) <= adcdata_S(selectnr_S*8+index)(13 downto 0);
+-- testword2_S(index*16+15 downto index*16+14) <= (others => '0');
+end generate;
+
+forced_reset_S <= vioword_S(0);
+
+process(clock_ADCref_S)
+variable prev_vioword2 : std_logic := '0';
+variable prev_vioword3 : std_logic := '0';
+begin
+ if (rising_edge(clock_ADCref_S)) then
+ if prev_vioword2 /= vioword_S(2) then
+ test_resetADC_S <= '1';
+ else
+ test_resetADC_S <= '0';
+ end if;
+ prev_vioword2 := vioword_S(2);
+ if prev_vioword3 /= vioword_S(3) then
+ debug_sync_S <= '1';
+ else
+ debug_sync_S <= '0';
+ end if;
+ prev_vioword3 := vioword_S(3);
+ end if;
+end process;
+
+process(ST_CLK_S)
+begin
+ if (rising_edge(ST_CLK_S)) then
+ testclockDiv2_S(0) <= not testclockDiv2_S(0);
+ end if;
+end process;
+process(clock_ADCref_S)
+begin
+ if (rising_edge(clock_ADCref_S)) then
+ testclockDiv2_S(1) <= not testclockDiv2_S(1);
+ end if;
+end process;
+process(clock_ADCrefdiv2_S)
+begin
+ if (rising_edge(clock_ADCrefdiv2_S)) then
+ testclockDiv2_S(2) <= not testclockDiv2_S(2);
+ end if;
+end process;
+process(RCV_CLK_S)
+begin
+ if (rising_edge(RCV_CLK_S)) then
+ testclockDiv2_S(3) <= not testclockDiv2_S(3);
+ end if;
+end process;
+process(GCLK_S)
+begin
+ if (rising_edge(GCLK_S)) then
+ testclockDiv2_S(4) <= not testclockDiv2_S(4);
+ end if;
+end process;
+process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ testclockDiv2_S(5) <= not testclockDiv2_S(5);
+ end if;
+end process;
+process(txUsrClk_S)
+begin
+ if (rising_edge(txUsrClk_S)) then
+ testclockDiv2_S(6) <= not testclockDiv2_S(6);
+ end if;
+end process;
+process(ADC_clk_S)
+begin
+ if (rising_edge(ADC_clk_S)) then
+ testclockDiv2_S(7) <= not testclockDiv2_S(7);
+ end if;
+end process;
+
+
+SM1_P <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
+SM1_N <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
+
+--SM3_P <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
+--SM3_N <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy
new file mode 100644
index 0000000..b5b3c4e
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy
@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 FEE_clockbuf80MHz
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise
new file mode 100644
index 0000000..913f68e
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise
@@ -0,0 +1,52 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf
new file mode 100644
index 0000000..9b5a1f0
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf
@@ -0,0 +1,58 @@
+# file: FEE_clockbuf80MHz.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 12.500 ns HIGH 50% INPUT_JITTER 125.0ps;
+
+
+# FALSE PATH constraints
+
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd
new file mode 100644
index 0000000..251b107
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd
@@ -0,0 +1,209 @@
+-- file: FEE_clockbuf80MHz.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output Output Phase Duty Pk-to-Pk Phase"
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____80.000______0.000______50.0______147.966____103.963
+-- CLK_OUT2____80.000____180.000______50.0______147.966____103.963
+--
+------------------------------------------------------------------------------
+-- "Input Clock Freq (MHz) Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________80____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity FEE_clockbuf80MHz is
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic
+ );
+end FEE_clockbuf80MHz;
+
+architecture xilinx of FEE_clockbuf80MHz is
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "FEE_clockbuf80MHz,clk_wiz_v3_6,{component_name=FEE_clockbuf80MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=12.500,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2_unused : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3_unused : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal locked_unused : std_logic;
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1 <= CLK_IN1;
+
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+ mmcm_adv_inst : MMCM_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ CLOCK_HOLD => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => 1,
+ CLKFBOUT_MULT_F => 12.000,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => 12.000,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKOUT1_DIVIDE => 12,
+ CLKOUT1_PHASE => 180.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => 12.500,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2_unused,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3_unused,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout_buf,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => locked_unused,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => '0');
+
+ -- Output buffering
+ -------------------------------------
+ clkf_buf : BUFG
+ port map
+ (O => clkfbout_buf,
+ I => clkfbout);
+
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK_OUT1,
+ I => clkout0);
+
+
+
+ clkout2_buf : BUFG
+ port map
+ (O => CLK_OUT2,
+ I => clkout1);
+
+end xilinx;
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho
new file mode 100644
index 0000000..2174648
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho
@@ -0,0 +1,89 @@
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output Output Phase Duty Pk-to-Pk Phase"
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____80.000______0.000______50.0______147.966____103.963
+-- CLK_OUT2____80.000____180.000______50.0______147.966____103.963
+--
+------------------------------------------------------------------------------
+-- "Input Clock Freq (MHz) Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________80____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component FEE_clockbuf80MHz
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : FEE_clockbuf80MHz
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Clock out ports
+ CLK_OUT1 => CLK_OUT1,
+ CLK_OUT2 => CLK_OUT2);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco
new file mode 100644
index 0000000..d5db7fd
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Thu Sep 25 14:23:17 2014
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6vlx130t
+SET devicefamily = virtex6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ff484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=125.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=80
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=80
+CSET clkout2_requested_phase=180
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=80
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=80
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=80
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=80
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=80
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=MANUAL
+CSET component_name=FEE_clockbuf80MHz
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLK0
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=10.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=12.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=12.500
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=12.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=12
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=180.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=2
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=4
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=10.000
+CSET pll_clkout0_divide=1
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=80
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=MMCM_ADV
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=false
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=false
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=false
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: f339ac6c
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise
new file mode 100644
index 0000000..ff919f7
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise
@@ -0,0 +1,75 @@
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy
new file mode 100644
index 0000000..4d8a6f6
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy
@@ -0,0 +1,89 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 SystemMonitorVirtex
+RECTANGLE Normal 32 32 640 1504
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName di_in[15:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName daddr_in[6:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName den_in
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName dwe_in
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName dclk_in
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName reset_in
+PINATTR Polarity IN
+LINE Normal 0 400 32 400
+PIN 0 400 LEFT 36
+PINATTR PinName vp_in
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName vn_in
+PINATTR Polarity IN
+LINE Wide 672 80 640 80
+PIN 672 80 RIGHT 36
+PINATTR PinName do_out[15:0]
+PINATTR Polarity OUT
+LINE Normal 672 112 640 112
+PIN 672 112 RIGHT 36
+PINATTR PinName drdy_out
+PINATTR Polarity OUT
+LINE Normal 672 176 640 176
+PIN 672 176 RIGHT 36
+PINATTR PinName user_temp_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 208 640 208
+PIN 672 208 RIGHT 36
+PINATTR PinName vccint_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 240 640 240
+PIN 672 240 RIGHT 36
+PINATTR PinName vccaux_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 272 640 272
+PIN 672 272 RIGHT 36
+PINATTR PinName ot_out
+PINATTR Polarity OUT
+LINE Wide 672 336 640 336
+PIN 672 336 RIGHT 36
+PINATTR PinName channel_out[4:0]
+PINATTR Polarity OUT
+LINE Normal 672 368 640 368
+PIN 672 368 RIGHT 36
+PINATTR PinName eoc_out
+PINATTR Polarity OUT
+LINE Normal 672 400 640 400
+PIN 672 400 RIGHT 36
+PINATTR PinName eos_out
+PINATTR Polarity OUT
+LINE Normal 672 432 640 432
+PIN 672 432 RIGHT 36
+PINATTR PinName busy_out
+PINATTR Polarity OUT
+LINE Normal 672 464 640 464
+PIN 672 464 RIGHT 36
+PINATTR PinName jtaglocked_out
+PINATTR Polarity OUT
+LINE Normal 672 496 640 496
+PIN 672 496 RIGHT 36
+PINATTR PinName jtagmodified_out
+PINATTR Polarity OUT
+LINE Normal 672 528 640 528
+PIN 672 528 RIGHT 36
+PINATTR PinName jtagbusy_out
+PINATTR Polarity OUT
+
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise
new file mode 100644
index 0000000..b6a2bee
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise
@@ -0,0 +1,53 @@
+
+
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+ 11.1
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diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd
new file mode 100644
index 0000000..c196fb5
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd
@@ -0,0 +1,192 @@
+-- file: SystemMonitorVirtex.vhd
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+Library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity SystemMonitorVirtex is
+ port (
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
+ VN_IN : in STD_LOGIC
+);
+end SystemMonitorVirtex;
+
+architecture xilinx of SystemMonitorVirtex is
+
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";
+
+ signal aux_channel_p : std_logic_vector (15 downto 0);
+ signal aux_channel_n : std_logic_vector (15 downto 0);
+
+begin
+
+ aux_channel_p(0) <= '0';
+ aux_channel_n(0) <= '0';
+
+ aux_channel_p(1) <= '0';
+ aux_channel_n(1) <= '0';
+
+ aux_channel_p(2) <= '0';
+ aux_channel_n(2) <= '0';
+
+ aux_channel_p(3) <= '0';
+ aux_channel_n(3) <= '0';
+
+ aux_channel_p(4) <= '0';
+ aux_channel_n(4) <= '0';
+
+ aux_channel_p(5) <= '0';
+ aux_channel_n(5) <= '0';
+
+ aux_channel_p(6) <= '0';
+ aux_channel_n(6) <= '0';
+
+ aux_channel_p(7) <= '0';
+ aux_channel_n(7) <= '0';
+
+ aux_channel_p(8) <= '0';
+ aux_channel_n(8) <= '0';
+
+ aux_channel_p(9) <= '0';
+ aux_channel_n(9) <= '0';
+
+ aux_channel_p(10) <= '0';
+ aux_channel_n(10) <= '0';
+
+ aux_channel_p(11) <= '0';
+ aux_channel_n(11) <= '0';
+
+ aux_channel_p(12) <= '0';
+ aux_channel_n(12) <= '0';
+
+ aux_channel_p(13) <= '0';
+ aux_channel_n(13) <= '0';
+
+ aux_channel_p(14) <= '0';
+ aux_channel_n(14) <= '0';
+
+ aux_channel_p(15) <= '0';
+ aux_channel_n(15) <= '0';
+
+
+ SYSMON_INST : SYSMON
+ generic map(
+ INIT_40 => X"0000", -- config reg 0
+ INIT_41 => X"3000", -- config reg 1
+ INIT_42 => X"1900", -- config reg 2
+ INIT_48 => X"0100", -- Sequencer channel selection
+ INIT_49 => X"0000", -- Sequencer channel selection
+ INIT_4A => X"0000", -- Sequencer Average selection
+ INIT_4B => X"0000", -- Sequencer Average selection
+ INIT_4C => X"0000", -- Sequencer Bipolar selection
+ INIT_4D => X"0000", -- Sequencer Bipolar selection
+ INIT_4E => X"0000", -- Sequencer Acq time selection
+ INIT_4F => X"0000", -- Sequencer Acq time selection
+ INIT_50 => X"b5ed", -- Temp alarm trigger
+ INIT_51 => X"5999", -- Vccint upper alarm limit
+ INIT_52 => X"e000", -- Vccaux upper alarm limit
+ INIT_53 => X"ca33", -- Temp alarm OT upper
+ INIT_54 => X"a93a", -- Temp alarm reset
+ INIT_55 => X"5111", -- Vccint lower alarm limit
+ INIT_56 => X"caaa", -- Vccaux lower alarm limit
+ INIT_57 => X"ae4e", -- Temp alarm OT reset
+ SIM_DEVICE => "VIRTEX6",
+ SIM_MONITOR_FILE => "design.txt"
+ )
+
+port map (
+ CONVST => '0',
+ CONVSTCLK => '0',
+ DADDR(6 downto 0) => DADDR_IN(6 downto 0),
+ DCLK => DCLK_IN,
+ DEN => DEN_IN,
+ DI(15 downto 0) => DI_IN(15 downto 0),
+ DWE => DWE_IN,
+ RESET => RESET_IN,
+ VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
+ VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
+ ALM(2) => VCCAUX_ALARM_OUT,
+ ALM(1) => VCCINT_ALARM_OUT,
+ ALM(0) => USER_TEMP_ALARM_OUT,
+ BUSY => BUSY_OUT,
+ CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),
+ DO(15 downto 0) => DO_OUT(15 downto 0),
+ DRDY => DRDY_OUT,
+ EOC => EOC_OUT,
+ EOS => EOS_OUT,
+ JTAGBUSY => JTAGBUSY_OUT,
+ JTAGLOCKED => JTAGLOCKED_OUT,
+ JTAGMODIFIED => JTAGMODIFIED_OUT,
+ OT => OT_OUT,
+ VN => VN_IN,
+ VP => VP_IN
+ );
+end xilinx;
+
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho
new file mode 100644
index 0000000..320cf0c
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho
@@ -0,0 +1,112 @@
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component SystemMonitorVirtex
+ port (
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
+ VN_IN : in STD_LOGIC
+);
+end component;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : SystemMonitorVirtex
+ port map (
+ DADDR_IN => DADDR_IN,
+ DCLK_IN => DCLK_IN,
+ DEN_IN => DEN_IN,
+ DI_IN => DI_IN,
+ DWE_IN => DWE_IN,
+ RESET_IN => RESET_IN,
+ BUSY_OUT => BUSY_OUT,
+ CHANNEL_OUT => CHANNEL_OUT,
+ DO_OUT => DO_OUT,
+ DRDY_OUT => DRDY_OUT,
+ EOC_OUT => EOC_OUT,
+ EOS_OUT => EOS_OUT,
+ JTAGBUSY_OUT => JTAGBUSY_OUT,
+ JTAGLOCKED_OUT => JTAGLOCKED_OUT,
+ JTAGMODIFIED_OUT => JTAGMODIFIED_OUT,
+ OT_OUT => OT_OUT,
+ VCCAUX_ALARM_OUT => VCCAUX_ALARM_OUT,
+ VCCINT_ALARM_OUT => VCCINT_ALARM_OUT,
+ USER_TEMP_ALARM_OUT => USER_TEMP_ALARM_OUT,
+ VP_IN => VP_IN,
+ VN_IN => VN_IN
+ );
+
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco
new file mode 100644
index 0000000..d8fdbe6
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco
@@ -0,0 +1,163 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.3
+# Date: Wed Oct 17 13:30:12 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:sysmon_wiz:2.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6vlx130t
+SET devicefamily = virtex6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ff484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT System_Monitor_Wizard family Xilinx,_Inc. 2.1
+# END Select
+# BEGIN Parameters
+CSET acquisition_time_vauxp0_vauxn0=false
+CSET acquisition_time_vauxp10_vauxn10=false
+CSET acquisition_time_vauxp11_vauxn11=false
+CSET acquisition_time_vauxp12_vauxn12=false
+CSET acquisition_time_vauxp13_vauxn13=false
+CSET acquisition_time_vauxp14_vauxn14=false
+CSET acquisition_time_vauxp15_vauxn15=false
+CSET acquisition_time_vauxp1_vauxn1=false
+CSET acquisition_time_vauxp2_vauxn2=false
+CSET acquisition_time_vauxp3_vauxn3=false
+CSET acquisition_time_vauxp4_vauxn4=false
+CSET acquisition_time_vauxp5_vauxn5=false
+CSET acquisition_time_vauxp6_vauxn6=false
+CSET acquisition_time_vauxp7_vauxn7=false
+CSET acquisition_time_vauxp8_vauxn8=false
+CSET acquisition_time_vauxp9_vauxn9=false
+CSET acquisition_time_vp_vn=false
+CSET adc_conversion_rate=100.0
+CSET adc_offset_and_gain_calibration=false
+CSET adc_offset_calibration=false
+CSET average_enable_temperature=false
+CSET average_enable_vauxp0_vauxn0=false
+CSET average_enable_vauxp10_vauxn10=false
+CSET average_enable_vauxp11_vauxn11=false
+CSET average_enable_vauxp12_vauxn12=false
+CSET average_enable_vauxp13_vauxn13=false
+CSET average_enable_vauxp14_vauxn14=false
+CSET average_enable_vauxp15_vauxn15=false
+CSET average_enable_vauxp1_vauxn1=false
+CSET average_enable_vauxp2_vauxn2=false
+CSET average_enable_vauxp3_vauxn3=false
+CSET average_enable_vauxp4_vauxn4=false
+CSET average_enable_vauxp5_vauxn5=false
+CSET average_enable_vauxp6_vauxn6=false
+CSET average_enable_vauxp7_vauxn7=false
+CSET average_enable_vauxp8_vauxn8=false
+CSET average_enable_vauxp9_vauxn9=false
+CSET average_enable_vccaux=false
+CSET average_enable_vccint=false
+CSET average_enable_vp_vn=false
+CSET bipolar_operation=false
+CSET bipolar_vauxp0_vauxn0=false
+CSET bipolar_vauxp10_vauxn10=false
+CSET bipolar_vauxp11_vauxn11=false
+CSET bipolar_vauxp12_vauxn12=false
+CSET bipolar_vauxp13_vauxn13=false
+CSET bipolar_vauxp14_vauxn14=false
+CSET bipolar_vauxp15_vauxn15=false
+CSET bipolar_vauxp1_vauxn1=false
+CSET bipolar_vauxp2_vauxn2=false
+CSET bipolar_vauxp3_vauxn3=false
+CSET bipolar_vauxp4_vauxn4=false
+CSET bipolar_vauxp5_vauxn5=false
+CSET bipolar_vauxp6_vauxn6=false
+CSET bipolar_vauxp7_vauxn7=false
+CSET bipolar_vauxp8_vauxn8=false
+CSET bipolar_vauxp9_vauxn9=false
+CSET bipolar_vp_vn=false
+CSET channel_averaging=None
+CSET channel_enable_calibration=false
+CSET channel_enable_temperature=false
+CSET channel_enable_vauxp0_vauxn0=false
+CSET channel_enable_vauxp10_vauxn10=false
+CSET channel_enable_vauxp11_vauxn11=false
+CSET channel_enable_vauxp12_vauxn12=false
+CSET channel_enable_vauxp13_vauxn13=false
+CSET channel_enable_vauxp14_vauxn14=false
+CSET channel_enable_vauxp15_vauxn15=false
+CSET channel_enable_vauxp1_vauxn1=false
+CSET channel_enable_vauxp2_vauxn2=false
+CSET channel_enable_vauxp3_vauxn3=false
+CSET channel_enable_vauxp4_vauxn4=false
+CSET channel_enable_vauxp5_vauxn5=false
+CSET channel_enable_vauxp6_vauxn6=false
+CSET channel_enable_vauxp7_vauxn7=false
+CSET channel_enable_vauxp8_vauxn8=false
+CSET channel_enable_vauxp9_vauxn9=false
+CSET channel_enable_vccaux=false
+CSET channel_enable_vccint=false
+CSET channel_enable_vp_vn=false
+CSET channel_enable_vrefn=false
+CSET channel_enable_vrefp=false
+CSET component_name=SystemMonitorVirtex
+CSET dclk_frequency=62.5
+CSET enable_busy=true
+CSET enable_calibration_averaging=true
+CSET enable_channel=true
+CSET enable_convst=false
+CSET enable_convstclk=false
+CSET enable_dclk=true
+CSET enable_drp=true
+CSET enable_eoc=true
+CSET enable_eos=true
+CSET enable_jtagbusy=true
+CSET enable_jtaglocked=true
+CSET enable_jtagmodified=true
+CSET enable_reset=true
+CSET increase_acquisition_time=false
+CSET ot_alarm=true
+CSET sensor_offset_and_gain_calibration=false
+CSET sensor_offset_calibration=false
+CSET sequencer_mode=Off
+CSET sim_file_name=design
+CSET single_channel_acquisition_time=false
+CSET single_channel_enable_calibration=true
+CSET single_channel_selection=Temperature
+CSET startup_channel_selection=single_channel
+CSET temperature_alarm_ot_reset=70.0
+CSET temperature_alarm_ot_trigger=125.0
+CSET temperature_alarm_reset=60.0
+CSET temperature_alarm_trigger=85.0
+CSET timing_mode=Continuous
+CSET user_temp_alarm=true
+CSET vccaux_alarm=true
+CSET vccaux_alarm_lower=2.375
+CSET vccaux_alarm_upper=2.625
+CSET vccint_alarm=true
+CSET vccint_alarm_lower=0.95
+CSET vccint_alarm_upper=1.05
+# END Parameters
+GENERATE
+# CRC: f7c86d59
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise
new file mode 100644
index 0000000..e2f9a9c
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise
@@ -0,0 +1,68 @@
+
+
+
+
+
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+
diff --git a/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs b/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..bcb73a2
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+Parsing VHDL file "D:/Project/Panda/GIT/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd" into library work
+
+
+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy
new file mode 100644
index 0000000..203f9b9
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 async_fifo_16x9
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[8:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[8:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise
new file mode 100644
index 0000000..5e02c17
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
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+
+
+ 11.1
+
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+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc
new file mode 100644
index 0000000..9dda322
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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0,
+ c_application_type_axis => 0,
+ c_application_type_rach => 0,
+ c_application_type_rdch => 0,
+ c_application_type_wach => 0,
+ c_application_type_wdch => 0,
+ c_application_type_wrch => 0,
+ c_axi_addr_width => 32,
+ c_axi_aruser_width => 1,
+ c_axi_awuser_width => 1,
+ c_axi_buser_width => 1,
+ c_axi_data_width => 64,
+ c_axi_id_width => 4,
+ c_axi_ruser_width => 1,
+ c_axi_type => 0,
+ c_axi_wuser_width => 1,
+ c_axis_tdata_width => 64,
+ c_axis_tdest_width => 4,
+ c_axis_tid_width => 8,
+ c_axis_tkeep_width => 4,
+ c_axis_tstrb_width => 4,
+ c_axis_tuser_width => 4,
+ c_axis_type => 0,
+ c_common_clock => 0,
+ c_count_type => 0,
+ c_data_count_width => 4,
+ c_default_value => "BlankString",
+ c_din_width => 9,
+ c_din_width_axis => 1,
+ c_din_width_rach => 32,
+ c_din_width_rdch => 64,
+ c_din_width_wach => 32,
+ c_din_width_wdch => 64,
+ c_din_width_wrch => 2,
+ c_dout_rst_val => "0",
+ c_dout_width => 9,
+ c_enable_rlocs => 0,
+ c_enable_rst_sync => 1,
+ c_error_injection_type => 0,
+ c_error_injection_type_axis => 0,
+ c_error_injection_type_rach => 0,
+ c_error_injection_type_rdch => 0,
+ c_error_injection_type_wach => 0,
+ c_error_injection_type_wdch => 0,
+ c_error_injection_type_wrch => 0,
+ c_family => "virtex6",
+ c_full_flags_rst_val => 1,
+ c_has_almost_empty => 0,
+ c_has_almost_full => 0,
+ c_has_axi_aruser => 0,
+ c_has_axi_awuser => 0,
+ c_has_axi_buser => 0,
+ c_has_axi_rd_channel => 0,
+ c_has_axi_ruser => 0,
+ c_has_axi_wr_channel => 0,
+ c_has_axi_wuser => 0,
+ c_has_axis_tdata => 0,
+ c_has_axis_tdest => 0,
+ c_has_axis_tid => 0,
+ c_has_axis_tkeep => 0,
+ c_has_axis_tlast => 0,
+ c_has_axis_tready => 1,
+ c_has_axis_tstrb => 0,
+ c_has_axis_tuser => 0,
+ c_has_backup => 0,
+ c_has_data_count => 0,
+ c_has_data_counts_axis => 0,
+ c_has_data_counts_rach => 0,
+ c_has_data_counts_rdch => 0,
+ c_has_data_counts_wach => 0,
+ c_has_data_counts_wdch => 0,
+ c_has_data_counts_wrch => 0,
+ c_has_int_clk => 0,
+ c_has_master_ce => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_has_prog_flags_axis => 0,
+ c_has_prog_flags_rach => 0,
+ c_has_prog_flags_rdch => 0,
+ c_has_prog_flags_wach => 0,
+ c_has_prog_flags_wdch => 0,
+ c_has_prog_flags_wrch => 0,
+ c_has_rd_data_count => 0,
+ c_has_rd_rst => 0,
+ c_has_rst => 1,
+ c_has_slave_ce => 0,
+ c_has_srst => 0,
+ c_has_underflow => 0,
+ c_has_valid => 0,
+ c_has_wr_ack => 0,
+ c_has_wr_data_count => 0,
+ c_has_wr_rst => 0,
+ c_implementation_type => 2,
+ c_implementation_type_axis => 1,
+ c_implementation_type_rach => 1,
+ c_implementation_type_rdch => 1,
+ c_implementation_type_wach => 1,
+ c_implementation_type_wdch => 1,
+ c_implementation_type_wrch => 1,
+ c_init_wr_pntr_val => 0,
+ c_interface_type => 0,
+ c_memory_type => 1,
+ c_mif_file_name => "BlankString",
+ c_msgon_val => 1,
+ c_optimization_mode => 0,
+ c_overflow_low => 0,
+ c_preload_latency => 1,
+ c_preload_regs => 0,
+ c_prim_fifo_type => "512x36",
+ c_prog_empty_thresh_assert_val => 2,
+ c_prog_empty_thresh_assert_val_axis => 1022,
+ c_prog_empty_thresh_assert_val_rach => 1022,
+ c_prog_empty_thresh_assert_val_rdch => 1022,
+ c_prog_empty_thresh_assert_val_wach => 1022,
+ c_prog_empty_thresh_assert_val_wdch => 1022,
+ c_prog_empty_thresh_assert_val_wrch => 1022,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_type => 0,
+ c_prog_empty_type_axis => 0,
+ c_prog_empty_type_rach => 0,
+ c_prog_empty_type_rdch => 0,
+ c_prog_empty_type_wach => 0,
+ c_prog_empty_type_wdch => 0,
+ c_prog_empty_type_wrch => 0,
+ c_prog_full_thresh_assert_val => 13,
+ c_prog_full_thresh_assert_val_axis => 1023,
+ c_prog_full_thresh_assert_val_rach => 1023,
+ c_prog_full_thresh_assert_val_rdch => 1023,
+ c_prog_full_thresh_assert_val_wach => 1023,
+ c_prog_full_thresh_assert_val_wdch => 1023,
+ c_prog_full_thresh_assert_val_wrch => 1023,
+ c_prog_full_thresh_negate_val => 12,
+ c_prog_full_type => 0,
+ c_prog_full_type_axis => 0,
+ c_prog_full_type_rach => 0,
+ c_prog_full_type_rdch => 0,
+ c_prog_full_type_wach => 0,
+ c_prog_full_type_wdch => 0,
+ c_prog_full_type_wrch => 0,
+ c_rach_type => 0,
+ c_rd_data_count_width => 4,
+ c_rd_depth => 16,
+ c_rd_freq => 1,
+ c_rd_pntr_width => 4,
+ c_rdch_type => 0,
+ c_reg_slice_mode_axis => 0,
+ c_reg_slice_mode_rach => 0,
+ c_reg_slice_mode_rdch => 0,
+ c_reg_slice_mode_wach => 0,
+ c_reg_slice_mode_wdch => 0,
+ c_reg_slice_mode_wrch => 0,
+ c_synchronizer_stage => 2,
+ c_underflow_low => 0,
+ c_use_common_overflow => 0,
+ c_use_common_underflow => 0,
+ c_use_default_settings => 0,
+ c_use_dout_rst => 1,
+ c_use_ecc => 0,
+ c_use_ecc_axis => 0,
+ c_use_ecc_rach => 0,
+ c_use_ecc_rdch => 0,
+ c_use_ecc_wach => 0,
+ c_use_ecc_wdch => 0,
+ c_use_ecc_wrch => 0,
+ c_use_embedded_reg => 0,
+ c_use_fifo16_flags => 0,
+ c_use_fwft_data_count => 0,
+ c_valid_low => 0,
+ c_wach_type => 0,
+ c_wdch_type => 0,
+ c_wr_ack_low => 0,
+ c_wr_data_count_width => 4,
+ c_wr_depth => 16,
+ c_wr_depth_axis => 1024,
+ c_wr_depth_rach => 16,
+ c_wr_depth_rdch => 1024,
+ c_wr_depth_wach => 16,
+ c_wr_depth_wdch => 1024,
+ c_wr_depth_wrch => 16,
+ c_wr_freq => 1,
+ c_wr_pntr_width => 4,
+ c_wr_pntr_width_axis => 10,
+ c_wr_pntr_width_rach => 4,
+ c_wr_pntr_width_rdch => 10,
+ c_wr_pntr_width_wach => 4,
+ c_wr_pntr_width_wdch => 10,
+ c_wr_pntr_width_wrch => 4,
+ c_wr_response_latency => 1,
+ c_wrch_type => 0
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_async_fifo_16x9
+ PORT MAP (
+ rst => rst,
+ wr_clk => wr_clk,
+ rd_clk => rd_clk,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty
+ );
+-- synthesis translate_on
+
+END async_fifo_16x9_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho
new file mode 100644
index 0000000..fa03d03
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho
@@ -0,0 +1,95 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2014 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --
+-- --
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --
+-- memory queue generator. Use it to generate resource and performance --
+-- optimized FIFOs with common or independent read/write clock domains, --
+-- and optional fixed or programmable full and empty flags and --
+-- handshaking signals. Choose from a selection of memory resource --
+-- types for implementation. Optional Hamming code based error --
+-- detection and correction as well as error injection capability for --
+-- system test help to insure data integrity. FIFO width and depth are --
+-- parameterizable, and for native interface FIFOs, asymmetric read and --
+-- write port widths are also supported. --
+--------------------------------------------------------------------------------
+
+-- Interfaces:
+-- AXI4Stream_MASTER_M_AXIS
+-- AXI4Stream_SLAVE_S_AXIS
+-- AXI4_MASTER_M_AXI
+-- AXI4_SLAVE_S_AXI
+-- AXI4Lite_MASTER_M_AXI
+-- AXI4Lite_SLAVE_S_AXI
+-- master_aclk
+-- slave_aclk
+-- slave_aresetn
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT async_fifo_16x9
+ PORT (
+ rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ wr_en : IN STD_LOGIC;
+ rd_en : IN STD_LOGIC;
+ dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+ full : OUT STD_LOGIC;
+ empty : OUT STD_LOGIC
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : async_fifo_16x9
+ PORT MAP (
+ rst => rst,
+ wr_clk => wr_clk,
+ rd_clk => rd_clk,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file async_fifo_16x9.vhd when simulating
+-- the core, async_fifo_16x9. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco
new file mode 100644
index 0000000..c361245
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco
@@ -0,0 +1,213 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Thu Nov 27 10:27:02 2014
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:fifo_generator:9.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6vlx130t
+SET devicefamily = virtex6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ff484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=async_fifo_16x9
+CSET data_count=false
+CSET data_count_width=4
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=3
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=13
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=12
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=9
+CSET input_depth=16
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=9
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=4
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=4
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T12:39:56Z
+# END Extra information
+GENERATE
+# CRC: e70f47ef
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise
new file mode 100644
index 0000000..466e213
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise
@@ -0,0 +1,74 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy
new file mode 100644
index 0000000..bb91418
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 async_fifo_512x32
+RECTANGLE Normal 32 32 800 3680
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[31:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[31:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise
new file mode 100644
index 0000000..c15f6b8
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc
new file mode 100644
index 0000000..72932bd
--- /dev/null
+++ b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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