From: Michael Boehmer Date: Wed, 20 Jul 2022 06:28:03 +0000 (+0200) Subject: fixed length zero problem in random fwd tester X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3285e5d019a5508f0969cdc2fcb00551609a05cf;p=trbnet.git fixed length zero problem in random fwd tester --- diff --git a/gbe_trb/base/fwd_test_random.vhd b/gbe_trb/base/fwd_test_random.vhd index 57f23d5..81076fb 100644 --- a/gbe_trb/base/fwd_test_random.vhd +++ b/gbe_trb/base/fwd_test_random.vhd @@ -53,22 +53,18 @@ architecture fwd_test_random_arch of fwd_test_random is -- Signals signal sop_x : std_logic; - signal sop : std_logic; signal eop_x : std_logic; - signal eop : std_logic; signal rst_x : std_logic; - signal rst : std_logic; signal frame_len : std_logic_vector(15 downto 0); signal test_cnt : unsigned(15 downto 0); signal test_data : std_logic_vector(15 downto 0); signal test_done_x : std_logic; - signal test_done : std_logic; - signal test_ce_x : std_logic; + signal new_prng_x : std_logic; signal delay_ce_x : std_logic; - signal data_valid_x : std_logic; + signal decrement_x : std_logic; begin @@ -87,47 +83,46 @@ begin RESEED_IN => '0', NEWKEY_IN => (others => '0'), NEWIV_IN => (others => '0'), - READY_IN => test_ce_x, + READY_IN => new_prng_x, VALID_OUT => open, DATA_OUT => test_data ); -- store the random frame length + -- we allow 0..2047 bytes, the length will be 2 bytes THE_FL_PROC: process( CLK ) begin if( rising_edge(CLK) ) then if ( RESET = '1' ) then frame_len <= (others => '0'); - elsif( sop = '1' ) then - frame_len <= b"00000" & test_data(8 downto 0) & b"11"; + elsif( sop_x = '1' ) then + frame_len <= b"00000" & test_data(10 downto 0); end if; end if; end process THE_FL_PROC; - - -- TAKE CARE HERE: we write two bytes "length"... must be considered carefully. - + -- new PRNG data is produced when we are idle and in case we wrote a byte - test_ce_x <= '1' when ((STATE = IDLE) or (data_valid_x = '1')) - else '0'; + new_prng_x <= '1' when (STATE = IDLE) or + (STATE = FLL) or + ((STATE = DATA) and (FWD_FULL_IN = '0')) + else '0'; -- test data is only written when we are ready data_valid_x <= '1' when ((STATE = DATA) or (STATE = FLH) or (STATE = FLL)) and (FWD_FULL_IN = '0') else '0'; + -- length counter is only active when data is written, not during length field + decrement_x <= '1' when ((STATE = DATA) and (FWD_FULL_IN = '0')) + else '0'; + -- multiplex output data FWD_DATA_OUT <= frame_len(15 downto 8) when (STATE = FLH) else - frame_len(7 downto 0) when (STATE = FLL) else - test_data(7 downto 0) when (STATE = DATA); + frame_len(7 downto 0) when (STATE = FLL) else + test_data(7 downto 0) when (STATE = DATA); -- write signal for next stage FWD_DATA_VALID_OUT <= data_valid_x; --------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------- - - - ----------------------------------------------------------- -- Test counter ----------------------------------------------------------- @@ -136,11 +131,11 @@ begin if( rising_edge(CLK) ) then if ( RESET = '1' ) then test_cnt <= (others => '1'); - elsif( sop = '1' ) then - test_cnt <= unsigned(b"00000" & test_data(8 downto 0) & b"11"); - elsif( rst = '1' ) then + elsif( sop_x = '1' ) then + test_cnt <= unsigned(b"00000" & test_data(10 downto 0)); + elsif( rst_x = '1' ) then test_cnt <= unsigned(FWD_DELAY_IN); - elsif( (data_valid_x = '1') or (delay_ce_x = '1') ) then + elsif( (decrement_x = '1') or (delay_ce_x = '1') ) then test_cnt <= test_cnt - 1; end if; end if; @@ -150,12 +145,12 @@ begin test_done_x <= '1' when (test_cnt = x"0000") else '0'; - test_done <= test_done_x when rising_edge(CLK); - eop_x <= '1' when ((test_cnt = x"0000") and (STATE = DATA)) else '0'; - eop <= eop_x when rising_edge(CLK); - + sop_x <= '1' when (STATE = START) else '0'; + + rst_x <= '1' when (STATE = CLEANUP) else '0'; + ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- @@ -164,12 +159,8 @@ begin if( rising_edge(CLK) ) then if( RESET = '1' ) then STATE <= IDLE; - sop <= '0'; - rst <= '0'; else STATE <= NEXT_STATE; - sop <= sop_x; - rst <= rst_x; end if; end if; end process THE_FSM; @@ -177,17 +168,13 @@ begin ----------------------------------------------------------- -- ----------------------------------------------------------- - THE_STATE_TRANSITIONS: process( STATE, FWD_ENABLE_IN, FWD_START_IN, test_done ) + THE_STATE_TRANSITIONS: process( STATE, FWD_ENABLE_IN, FWD_START_IN, test_done_x ) begin - sop_x <= '0'; - rst_x <= '0'; - case STATE is when IDLE => if( (FWD_ENABLE_IN = '1') and (FWD_START_IN = '1') and (FWD_READY_IN = '1') and (FWD_FULL_IN = '0') ) then NEXT_STATE <= START; - sop_x <= '1'; else NEXT_STATE <= IDLE; end if; @@ -214,9 +201,8 @@ begin end if; when DATA => - if( test_done = '1' ) then + if( test_done_x = '1' ) then NEXT_STATE <= CLEANUP; - rst_x <= '1'; else NEXT_STATE <= DATA; end if; @@ -225,7 +211,7 @@ begin NEXT_STATE <= DELAY; when DELAY => - if( test_done = '1' ) then + if( test_done_x = '1' ) then NEXT_STATE <= IDLE; else NEXT_STATE <= DELAY; @@ -236,8 +222,8 @@ begin end case; end process THE_STATE_TRANSITIONS; - FWD_SOP_OUT <= sop; - FWD_EOP_OUT <= eop; + FWD_SOP_OUT <= sop_x; + FWD_EOP_OUT <= eop_x; FWD_BUSY_OUT <= '1' when (STATE /= IDLE) else '0';