From: Adrian Weber Date: Wed, 9 Jan 2019 18:07:33 +0000 (+0100) Subject: fix in mbs; files for mRICH Senosring X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3287a8d17d42f405eae05598db7f8ba9a4e1c09a;p=trb3sc.git fix in mbs; files for mRICH Senosring --- diff --git a/hub_cts/code/EnvBoardParser.vhd b/hub_cts/code/EnvBoardParser.vhd new file mode 100644 index 0000000..fc90678 --- /dev/null +++ b/hub_cts/code/EnvBoardParser.vhd @@ -0,0 +1,173 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity envBoardParser is + port( + INPUT : in std_logic_vector(7 downto 0); + CLK : in std_logic; + READY : in std_logic; + + SERIAL_NUMBER : out std_logic_vector(6 downto 0); + SENSOR_NUMBER : out std_logic_vector(1 downto 0); -- coding: 0= Mag, 1= BME, 2= Light + TYP_NUMBER : out std_logic_vector(1 downto 0); -- coding: 0 = T, 1 = X, 2 = Y, 3 = Z OR : 0 = T, 1=P , 2= H ;OR: 0=Light0, 1= Light1 + VALUE : out unsigned(30 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of envBoardParser is + type state_type is (idle, Mag_readInitSerialNumber, readSerialNumber, readSensorNumber, read_Mag_Typ, readValue, BME_read); + signal currentState : state_type := idle; + signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; + signal serialNumber_tmp : std_logic_vector(13 downto 0) := "00000000000000"; + signal sensorNumber : std_logic_vector(1 downto 0) := "00"; + signal typ : std_logic_vector(1 downto 0) := "00"; -- 0 = T, 1 = X, 2 = Y, 3 = Z + signal sign : std_logic := '0'; + signal valueIntern : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal valueIntern_tmp: unsigned(61 downto 0) := b"00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000"; + signal output_ID : std_logic_vector(31 downto 0) := x"00000000"; + signal output_value : std_logic_vector(31 downto 0) := x"00000000"; + signal rdy_cnt : unsigned (15 downto 0):= x"0000"; +begin + +-- process incoming string. It has the form M_03_2_X 123.456\r +PROC_PARSER : process begin + wait until rising_edge(CLK); + serialNumber <= serialNumber_tmp(6 downto 0); -- need temp value, because of size for multiplication + valueIntern <= valueIntern_tmp(30 downto 0); -- need temp value, because of size for multiplication + + if READY = '1' then -- only read when READY == 1 + rdy_cnt <= rdy_cnt + 1; + case currentState is + when idle => + -- set all values back to 0 + --serialNumber <= (others=>'0'); + sensorNumber <= (others=>'0'); + typ <= (others=>'0'); + valueIntern <= (others=>'0'); + sign <= '0'; + serialNumber_tmp <= (others=>'0'); + valueIntern_tmp <= (others=>'0'); + if INPUT = x"4D" then + -- Found char 'M'. Start parsing row and go to next state + currentState <= Mag_readInitSerialNumber; + elsif INPUT = x"54"then --T + currentState <= BME_read; + typ <= "00"; + elsif INPUT = x"50"then --P + currentState <= BME_read; + typ <= "01"; + elsif INPUT = x"48"then --H + currentState <= BME_read; + typ <= "10"; + end if; + when Mag_readInitSerialNumber => + if INPUT = x"5F" then + -- Found char '_'. + serialNumber <= (others=>'0'); + currentState <= readSerialNumber; + else + currentState <= idle; + end if; + when readSerialNumber => + if INPUT = x"5F" then + -- Found char '_'. Serial number is complete + currentState <= readSensorNumber; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + serialNumber_tmp <= std_logic_vector(unsigned(serialNumber) * 10 + unsigned(INPUT(3 downto 0))); + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + when readSensorNumber => + if INPUT = x"5F" then + -- Found char "_". Sensor number is complete. + currentState <= read_Mag_Typ; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + sensorNumber <= INPUT(1 downto 0); + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + when read_Mag_Typ => + if INPUT = x"20" then + -- Found char " ". Axis is complete. + currentState <= readValue; + elsif INPUT = x"54" then + -- Found char "T". + typ <= "00"; + elsif INPUT = x"58" then + -- Found char "X". + typ <= "01"; + elsif INPUT = x"59" then + -- Found char "Y". + typ <= "10"; + elsif INPUT = x"5A" then + -- Found char "Z". + typ <= "11"; + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + + when BME_read => + if INPUT = x"20" then + -- Found char " ". + currentState <= readValue; + end if; + sensorNumber <= "01"; + + when readValue => + if (INPUT = x"0D" or INPUT = x"0A") or (INPUT = x"20" and sensorNumber = "01")then + -- Found char "\r" or "\n". Value and complete line are complete. + currentState <= idle; -- back to idle + -- build complete value from sensor number, axis and value + output_value(31 downto 30) <= sensorNumber; + output_value(29 downto 28) <= typ; + if ((typ = x"01") and (sensorNumber = "01")) then + output_value(27 downto 0) <= std_logic_vector(valueIntern(27 downto 0)); + else + output_value(27) <= sign; + output_value(26 downto 0) <= std_logic_vector(valueIntern(26 downto 0)); + end if; + output_ID(26 downto 20) <= serialNumber; + output_ID(9 downto 8) <= sensorNumber; + output_ID(1 downto 0) <= typ; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + valueIntern_tmp <= valueIntern * 10 + unsigned(INPUT(3 downto 0)); + elsif INPUT = x"2E" then + -- Found char "." ignore this char. + elsif INPUT = x"2D" then + -- Found char "-". save sign to variable + sign <= '1'; + --elsif INPUT = x"20" then + -- currentState <= readValue; + else + -- all other chars are invalid. go back to idle. + currentState <= idle; + end if; + end case; + end if; +end process; + +SERIAL_NUMBER <= output_ID(26 downto 20); +SENSOR_NUMBER <= output_ID(9 downto 8); +TYP_NUMBER <= output_ID(1 downto 0); +VALUE(27 downto 0) <= output_value(27 downto 0); + +DEBUG(3 downto 0) <= x"0" when currentState = idle else + x"1" when currentState = Mag_readInitSerialNumber else + x"2" when currentState = readSerialNumber else + x"3" when currentState = readSensorNumber else + x"4" when currentState = read_Mag_Typ else + x"5" when currentState = readValue else + x"6" when currentState = BME_read else + x"F"; +DEBUG(11 downto 4) <= INPUT; +DEBUG(15 downto 12)<= x"0"; +DEBUG(31 downto 16)<= std_logic_vector(rdy_cnt); +end architecture behavioral; diff --git a/hub_cts/code/EnvBoardParserHandler.vhd b/hub_cts/code/EnvBoardParserHandler.vhd new file mode 100644 index 0000000..41a71fa --- /dev/null +++ b/hub_cts/code/EnvBoardParserHandler.vhd @@ -0,0 +1,112 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity envBoardParserHandler is + port( + INPUT : in std_logic_vector(7 downto 0); + CLK : in std_logic; + READY : in std_logic; + + SERIAL_NUMBER : out std_logic_vector(6 downto 0); + VALUE_M_T : out std_logic_vector(30 downto 0); + VALUE_M_X : out std_logic_vector(30 downto 0); + VALUE_M_Y : out std_logic_vector(30 downto 0); + VALUE_M_Z : out std_logic_vector(30 downto 0); + VALUE_BME_T : out std_logic_vector(30 downto 0); + VALUE_BME_P : out std_logic_vector(30 downto 0); + VALUE_BME_H : out std_logic_vector(30 downto 0); + VALUE_L_0 : out std_logic_vector(30 downto 0); + VALUE_L_1 : out std_logic_vector(30 downto 0); + ERROR_NO_DATA : out std_logic; + DEBUG : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of envBoardParserHandler is + -- signals for THE_MAGBOARD_PARSER + signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; + signal sensorNumber : std_logic_vector(1 downto 0) := "00"; + signal typ : std_logic_vector(1 downto 0) := "00"; + signal value : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_1111_1111"; + -- signals for output result from THE_MAGBOARD_PARSER + -- sensor0 + signal value_M_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0001"; + signal value_M_X_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0010"; + signal value_M_Y_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0011"; + signal value_M_Z_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0100"; + -- sensor1 + signal value_BME_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0101"; + signal value_BME_P_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0110"; + signal value_BME_H_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0111"; + -- sensor2 + signal value_L_0_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_1000"; + signal value_L_1_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_1001"; + + + -- signals for PROC_CHECK_ERROR + signal error : std_logic := '0'; + signal counter : unsigned(28 downto 0); + +begin + +-- do parsing in external file +THE_ENVBOARD_PARSER : entity work.envBoardParser + port map( + --in + INPUT => INPUT, + CLK => CLK, + READY => READY, + --out + SERIAL_NUMBER => serialNumber, + SENSOR_NUMBER => sensorNumber, + TYP_NUMBER => typ, + VALUE => value, + DEBUG => DEBUG + ); + +-- check if there is data to parse +PROC_CHECK_ERROR : process begin + wait until rising_edge(CLK); + if READY = '0' then + counter <= counter + 1; + else + error <= '0'; + counter <= (others => '0'); + end if; + if counter = 200000000 then + error <= '1'; + counter <= (others => '0'); + end if; +end process; + +--sort THE_MAGBOARD_PARSER values to signals, so they can be used in output + +value_M_T_i <= value when sensorNumber = "00" and typ = "00"; +value_M_X_i <= value when sensorNumber = "00" and typ = "01"; +value_M_Y_i <= value when sensorNumber = "00" and typ = "10"; +value_M_Z_i <= value when sensorNumber = "00" and typ = "11"; + +value_BME_T_i <= value when sensorNumber = "01" and typ = "00"; +value_BME_P_i <= value when sensorNumber = "01" and typ = "01"; +value_BME_H_i <= value when sensorNumber = "01" and typ = "10"; + +value_L_0_i <= value when sensorNumber = "10" and typ = "00"; +value_L_1_i <= value when sensorNumber = "10" and typ = "01"; + + +-- write signals to output pins. +SERIAL_NUMBER <= serialNumber; +VALUE_M_T <= std_logic_vector(value_M_T_i); +VALUE_M_X <= std_logic_vector(value_M_X_i); +VALUE_M_Y <= std_logic_vector(value_M_y_i); +VALUE_M_Z <= std_logic_vector(value_M_Z_i); +VALUE_BME_T <= std_logic_vector(value_BME_T_i); +VALUE_BME_P <= std_logic_vector(value_BME_P_i); +VALUE_BME_H <= std_logic_vector(value_BME_H_i); +VALUE_L_0 <= std_logic_vector(value_L_0_i); +VALUE_L_1 <= std_logic_vector(value_L_1_i); + +ERROR_NO_DATA <= error; + +end architecture behavioral; diff --git a/hub_cts/code/mbs_vulom_recv.vhd b/hub_cts/code/mbs_vulom_recv.vhd index 7eabe3f..11cf1d6 100644 --- a/hub_cts/code/mbs_vulom_recv.vhd +++ b/hub_cts/code/mbs_vulom_recv.vhd @@ -12,7 +12,7 @@ entity mbs_recv is generic ( INCL_RDO_TIMESTAMP : integer range c_NO to c_YES := c_NO; -- will yield an unexpected rdo length (2 words instead the signalled 1 word) -- if used as an ETM for the CTS - INCL_REGIO : integer range c_NO to c_YES := c_NO; + INCL_REGIO : integer range c_NO to c_YES := c_YES; USE_40MHz : integer range c_NO to c_YES := c_YES ); port( @@ -119,8 +119,7 @@ architecture mbs_recv_arch of mbs_recv is signal rdo_buf_rec_timestamp_i : std_logic_vector(31 downto 0); -- read-out buffer for the above signal rdo_buf_rec_lvl1_id_i : std_logic_vector(23 downto 0); -- read-out buffer for the above - - signal trig_async_cond,trig_async_cond_0 : std_logic; + begin HEADER_REG_OUT <= b"01"; -- we tell the CTS that we send one word of over DATA_OUT @@ -137,10 +136,8 @@ begin end process; first_bits_slow <= first_bits_fast when rising_edge(CLK); - trig_async_cond_0 <= '1' when (bitcnt = 37) else '0'; - trig_async_cond <= (trig_async_cond_0 and (not MBS_IN)) or trig_async_cond; - trg_async <= (not MBS_IN or trg_async) when trig_async_cond = '1' else '0'; + trg_async <= (not MBS_IN or trg_async) when first_bits_fast = '1' else '0'; trg_sync <= (not reg_MBS_IN or trg_sync) and first_bits_slow when rising_edge(CLK); TRG_ASYNC_OUT <= trg_async; diff --git a/hub_cts/code/trb3sc_tools_mRICH.vhd b/hub_cts/code/trb3sc_tools_mRICH.vhd new file mode 100644 index 0000000..b39d1f6 --- /dev/null +++ b/hub_cts/code/trb3sc_tools_mRICH.vhd @@ -0,0 +1,450 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_components.all; + use work.trb_net_std.all; + use work.trb3_components.all; + use work.config.all; + +entity trb3sc_tools is + port( + CLK : in std_logic; + RESET : in std_logic; + + --Flash & Reload + FLASH_CS : out std_logic; + FLASH_CLK : out std_logic; + FLASH_IN : in std_logic; + FLASH_OUT : out std_logic; + PROGRAMN : out std_logic; + REBOOT_IN : in std_logic; + + --SPI + SPI_CS_OUT : out std_logic_vector(15 downto 0); + SPI_MOSI_OUT: out std_logic_vector(15 downto 0); + SPI_MISO_IN : in std_logic_vector(15 downto 0) := (others => '0'); + SPI_CLK_OUT : out std_logic_vector(15 downto 0); + + --LCD + LCD_DATA_IN : in std_logic_vector(511 downto 0) := (others => '0'); + ADDITIONAL_REG : out std_logic_vector(31 downto 0); + --HDR_IO + HEADER_IO : inout std_logic_vector(10 downto 1); + + --ADC + ADC_CS : out std_logic := '0'; + ADC_MOSI : out std_logic := '0'; + ADC_MISO : in std_logic := '0'; + ADC_CLK : out std_logic := '0'; + + --Trigger & Monitor + MONITOR_INPUTS : in std_logic_vector(MONITOR_INPUT_NUM-1 downto 0) := (others => '0'); + TRIG_GEN_INPUTS : in std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0) := (others => '0'); + TRIG_GEN_OUTPUTS : out std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + --SED + SED_ERROR_OUT : out std_logic; + + --Slowcontrol + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + --Control master for default settings + BUS_MASTER_IN : in CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0'); + BUS_MASTER_OUT : out CTRLBUS_RX; + BUS_MASTER_ACTIVE : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture trb3sc_tools_arch of trb3sc_tools is + +signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, busadc_rx, bussed_rx, + busuart_rx, busflashset_rx, busmon_rx, bustrig_rx, busctrl_rx : CTRLBUS_RX; +signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx, + busuart_tx, busflashset_tx, busmon_tx, bustrig_tx, busctrl_tx : CTRLBUS_TX; + +signal spi_sdi, spi_sdo, spi_sck : std_logic; +signal spi_cs : std_logic_vector(15 downto 0); +signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic; +signal uart_rx, uart_tx : std_logic; + +signal flashset_active, debug_active : std_logic; +signal flash_cs_i, flash_clk_i, flash_out_i : std_logic; +signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; + +signal debug_rx, debug_tx : std_logic; +signal debug_status : std_logic_vector(31 downto 0); +signal additional_reg_i : std_logic_vector(31 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", + 5 => x"0180", 6 => x"0f00", 7 => x"0f80", 8 => x"0580", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, + 5 => 4, 6 => 7, 7 => 7, 8 => 0, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => CLK, + RESET => RESET, + + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + + BUS_RX(0) => busflash_rx, + BUS_RX(1) => busspi_rx, + BUS_RX(2) => busadc_rx, + BUS_RX(3) => bussed_rx, + BUS_RX(4) => busuart_rx, + BUS_RX(5) => busflashset_rx, + BUS_RX(6) => bustrig_rx, + BUS_RX(7) => busmon_rx, + BUS_RX(8) => busctrl_rx, + BUS_TX(0) => busflash_tx, + BUS_TX(1) => busspi_tx, + BUS_TX(2) => busadc_tx, + BUS_TX(3) => bussed_tx, + BUS_TX(4) => busuart_tx, + BUS_TX(5) => busflashset_tx, + BUS_TX(6) => bustrig_tx, + BUS_TX(7) => busmon_tx, + BUS_TX(8) => busctrl_tx, + STAT_DEBUG => open + ); + + + +--------------------------------------------------------------------------- +-- Flash & Reboot +--------------------------------------------------------------------------- + THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record + port map( + CLK_IN => CLK, + RESET_IN => RESET, + + BUS_RX => busflash_rx, + BUS_TX => busflash_tx, + + DO_REBOOT_IN => REBOOT_IN, + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => flash_cs_i, + SPI_SCK_OUT => flash_clk_i, + SPI_SDO_OUT => flash_out_i, + SPI_SDI_IN => FLASH_IN + ); + + +--------------------------------------------------------------------------- +-- Load Settings from Flash +--------------------------------------------------------------------------- +THE_FLASH_REGS : entity work.load_settings + port map( + CLK => CLK, + RST => RESET, + + -- the bus handler signals + BUS_RX => busflashset_rx, + BUS_TX => busflashset_tx, + + IS_ACTIVE => flashset_active, + + BUS_MASTER_TX => bus_flash_rx_out, + BUS_MASTER_RX => bus_flash_tx_in, + + SPI_MOSI => flash_out_s, + SPI_MISO => FLASH_IN, + SPI_SCK => flash_clk_s, + SPI_NCS => flash_cs_s + + ); + + BUS_MASTER_ACTIVE <= flashset_active or debug_active; + FLASH_CS <= flash_cs_i when flashset_active = '0' else flash_cs_s; + FLASH_CLK <= flash_clk_i when flashset_active = '0' else flash_clk_s; + FLASH_OUT <= flash_out_i when flashset_active = '0' else flash_out_s; + + bus_flash_tx_in <= BUS_MASTER_IN; + bus_debug_tx_in <= BUS_MASTER_IN; + + BUS_MASTER_OUT <= bus_debug_rx_out when debug_active = '1' else + bus_flash_rx_out; + + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => CLK, + ERROR_OUT => SED_ERROR_OUT, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx, + DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- ADC +--------------------------------------------------------------------------- + busadc_tx.unknown <= '1'; + busadc_tx.nack <= '0'; + busadc_tx.ack <= '0'; + busadc_tx.data <= (others => '0'); + + +--------------------------------------------------------------------------- +-- ADC +--------------------------------------------------------------------------- +gen_lcd : if INCLUDE_LCD = 1 generate + THE_LCD : entity work.lcd + port map( + CLK => CLK, + RESET => RESET, + + MOSI => lcd_mosi, + SCK => lcd_sck, + DC => lcd_dc, + CS => lcd_cs, + RST => lcd_rst, + + INPUT => LCD_DATA_IN, + DEBUG => open + ); +end generate; + +--------------------------------------------------------------------------- +-- SPI +--------------------------------------------------------------------------- + gen_SPI : if INCLUDE_SPI = 1 generate + THE_SPI : spi_ltc2600 + port map( + CLK_IN => CLK, + RESET_IN => RESET, + -- Slave bus + BUS_ADDR_IN => busspi_rx.addr(4 downto 0), + BUS_READ_IN => busspi_rx.read, + BUS_WRITE_IN => busspi_rx.write, + BUS_ACK_OUT => busspi_tx.ack, + BUS_BUSY_OUT => busspi_tx.nack, + BUS_DATA_IN => busspi_rx.data, + BUS_DATA_OUT => busspi_tx.data, + -- SPI connections + SPI_CS_OUT(15 downto 0) => spi_cs, + SPI_SDI_IN => spi_sdi, + SPI_SDO_OUT => spi_sdo, + SPI_SCK_OUT => spi_sck + ); + SPI_CS_OUT <= spi_cs; + SPI_CLK_OUT <= (others => spi_sck); + SPI_MOSI_OUT <= (others => spi_sdo); + spi_sdi <= (HEADER_IO(4) and not spi_cs(8)) or + (ADC_MISO and not spi_cs(7)) or + or_all(SPI_MISO_IN and not spi_cs and x"fe7f"); + + ADC_CLK <= not spi_sck; + ADC_CS <= spi_cs(7); + ADC_MOSI <= spi_sdo; + + busspi_tx.unknown <= '0'; + end generate; + + gen_no_spi : if INCLUDE_SPI = 0 generate + busspi_tx.unknown <= busspi_rx.write or busspi_rx.read; + busspi_tx.ack <= '0'; busspi_tx.nack <= '0'; + busspi_tx.data <= (others => '0'); + end generate; + +--------------------------------------------------------------------------- +-- UART +--------------------------------------------------------------------------- + gen_uart : if INCLUDE_UART = 1 generate + THE_UART : entity work.uart + generic map( + OUTPUTS => 1 + ) + port map( + CLK => CLK, + RESET => RESET, + UART_RX(0) => uart_rx, + UART_TX(0) => uart_tx, + BUS_RX => busuart_rx, + BUS_TX => busuart_tx + ); + end generate; + gen_no_uart : if INCLUDE_UART = 0 generate + busuart_tx.unknown <= busuart_rx.write or busuart_rx.read; + busuart_tx.ack <= '0'; busuart_tx.nack <= '0'; + busuart_tx.data <= (others => '0'); + end generate; + +--------------------------------------------------------------------------- +-- Debug Connection +--------------------------------------------------------------------------- +gen_debug : if INCLUDE_DEBUG_INTERFACE = 1 generate + THE_DEBUG : entity work.debuguart + port map( + CLK => CLK, + RESET => RESET, + + RX_IN => debug_rx, + TX_OUT => debug_tx, + + DEBUG_ACTIVE => debug_active, + + BUS_DEBUG_TX => bus_debug_tx_in, + BUS_DEBUG_RX => bus_debug_rx_out, + + STATUS => debug_status + + ); +end generate; +gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate + bus_debug_rx_out.write <= '0'; + bus_debug_rx_out.read <= '0'; + bus_debug_rx_out.timeout <= '0'; + bus_debug_rx_out.addr <= (others => '0'); + bus_debug_rx_out.data <= (others => '0'); + debug_tx <= 'Z'; + debug_active <= '0'; +end generate; + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- +gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : entity work.input_to_trigger_logic_record + generic map( + INPUTS => TRIG_GEN_INPUT_NUM, + OUTPUTS => TRIG_GEN_OUTPUT_NUM + ) + port map( + CLK => CLK, + + INPUT => TRIG_GEN_INPUTS, + OUTPUT => TRIG_GEN_OUTPUTS, + + BUS_RX => bustrig_rx, + BUS_TX => bustrig_tx + ); + +end generate; + +gen_noTRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate + bustrig_tx.unknown <= bustrig_rx.write or bustrig_rx.read; + bustrig_tx.ack <= '0'; bustrig_tx.nack <= '0'; + bustrig_tx.data <= (others => '0'); +end generate; + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- +gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => MONITOR_INPUT_NUM, + SINGLE_FIFO_ONLY => c_YES + ) + port map( + CLK => CLK, + + INPUT => MONITOR_INPUTS, + + DATA_IN => busmon_rx.data, + DATA_OUT => busmon_tx.data, + WRITE_IN => busmon_rx.write, + READ_IN => busmon_rx.read, + ACK_OUT => busmon_tx.ack, + NACK_OUT => busmon_tx.nack, + ADDR_IN => busmon_rx.addr + ); + busmon_tx.unknown <= '0'; +end generate; + +gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate + busmon_tx.unknown <= busmon_rx.write or busmon_rx.read; + busmon_tx.ack <= '0'; busmon_tx.nack <= '0'; + busmon_tx.data <= (others => '0'); +end generate; + +--------------------------------------------------------------------------- +-- Additional control register +--------------------------------------------------------------------------- +proc_add_reg : process begin + wait until rising_edge(CLK); + busctrl_tx.ack <= '0'; + busctrl_tx.nack <= '0'; + busctrl_tx.unknown <= '0'; + + if busctrl_rx.read = '1' then + busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i; + busctrl_tx.ack <= '1'; + elsif busctrl_rx.write = '1' then + additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0); + busctrl_tx.ack <= '1'; + end if; +end process; + + ADDITIONAL_REG <= additional_reg_i; + +--------------------------------------------------------------------------- +-- HEADER_IO +--------------------------------------------------------------------------- +-- 1 UART TX +-- 2 UART RX +-- 3 SPI MOSI +-- 4 SPI MISO +-- 5 SPI CLK +-- 6 SPI CS +-- 7 lcd_dc +-- 8 lcd_rst +-- 9 Debug RX +-- 10 Debug TX +-- 11 3.3V +-- 12 3.3V +-- 13 GND +-- 14 GND + +HEADER_IO(1) <= uart_tx; +uart_rx <= HEADER_IO(2); + +gen_lcdio : if INCLUDE_LCD = 1 generate + HEADER_IO(3) <= lcd_mosi; + HEADER_IO(5) <= lcd_sck; + HEADER_IO(6) <= lcd_cs; +end generate; +gen_nolcdio : if INCLUDE_LCD = 0 generate + HEADER_IO(3) <= spi_sdo; + -- HEADER_IO(4) <= ; + HEADER_IO(5) <= spi_sck; + HEADER_IO(6) <= spi_cs(8); +end generate; + + +HEADER_IO(7) <= lcd_dc; +HEADER_IO(8) <= lcd_rst; + +debug_rx <= '0'; + +debug_rx <= HEADER_IO(9); +HEADER_IO(10) <= debug_tx; + +-- HEADER_IO( 9) : ONEWIRE-Temperature chain +-- HEADER_IO(10): RX-UART from Sensorboard + +DEBUG_OUT <= debug_status; + + +end architecture; diff --git a/hub_cts/code/uart_env.vhd b/hub_cts/code/uart_env.vhd new file mode 100644 index 0000000..17e962f --- /dev/null +++ b/hub_cts/code/uart_env.vhd @@ -0,0 +1,247 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart_env is + generic( + OUTPUTS : integer := 1; + BAUD : integer := 19200 + ); + port( + CLK : in std_logic; + RESET : in std_logic; -- reset all values + UART_RX : in std_logic_vector(OUTPUTS-1 downto 0); -- incoming data which needs to be processed + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); -- send data to board + + BUS_RX : in CTRLBUS_RX; -- what user is sending to FPGA + BUS_TX : out CTRLBUS_TX -- what FPGA is sending to user + ); +end entity; + + +architecture uart_arch of uart_env is + +type parserValue_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(30 downto 0); +type serialNumber_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(6 downto 0); +type rxData_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(7 downto 0); + +signal rx_data : rxData_array; +signal rx_ready : std_logic_vector(OUTPUTS - 1 downto 0); +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS - 1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/BAUD; + +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; + +signal rx_debug : std_logic_vector(3 downto 0); +signal tx_debug : std_logic_vector(3 downto 0); + + +-- signals for output result from THE_PARSER_HANDLER +signal parser_error : std_logic_vector(OUTPUTS- 1 downto 0); +signal serialNumbers : serialNumber_array; +-- sensor0 +signal value_M_T : parserValue_array; +signal value_M_X : parserValue_array; +signal value_M_y : parserValue_array; +signal value_M_Z : parserValue_array; +-- sensor1 +signal value_BME_T : parserValue_array; +signal value_BME_P : parserValue_array; +signal value_BME_H : parserValue_array; +-- sensor2 +signal value_L_0 : parserValue_array; +signal value_L_1 : parserValue_array; + +signal debug_i : std_logic_vector(31 downto 0); +--signal i,j : integer; + +begin + +GEN_THE_PARSER_HANDLER: +for i in 0 to OUTPUTS - 1 generate +THE_PARSER_HANDLER : entity work.envBoardParserHandler + port map( + --in + INPUT => rx_data(i), + CLK => CLK, + READY => rx_ready(i), + --out + SERIAL_NUMBER => serialNumbers(i), + VALUE_M_T => value_M_T(i), + VALUE_M_X => value_M_X(i), + VALUE_M_Y => value_M_y(i), + VALUE_M_Z => value_M_Z(i), + VALUE_BME_T => value_BME_T(i), + VALUE_BME_P => value_BME_P(i), + VALUE_BME_H => value_BME_H(i), + VALUE_L_0 => value_L_0(i), + VALUE_L_1 => value_L_1(i), + ERROR_NO_DATA => parser_error(i), + DEBUG => debug_i + ); +end generate GEN_THE_PARSER_HANDLER; + + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +GEN_THE_RX: +for i in 0 to OUTPUTS - 1 generate +-- transfer incoming signal (uart_sel_rx) in 8bit vector. +THE_RX : entity work.uart_rec + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + RX => UART_RX(i), -- pass signale to sub entity (blackbox) + DATA_OUT => rx_data(i), -- return value + DATA_WAITING => rx_ready(i), -- return value + DEBUG => rx_debug -- return value + ); +end generate GEN_THE_RX; + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => uart_sel_tx, + DEBUG => tx_debug + ); + + +PROC_REGS : process + variable i,j : integer := 0; +begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + + tx_fifo_write <= '0'; + --rx_fifo_read <= '0'; + --last_rx_read <= rx_fifo_read; + --last2_rx_read <= last_rx_read; + + --if last2_rx_read = '1' then + --BUS_TX.data(8 downto 0) <= rx_fifo_out; + --BUS_TX.ack <= '1'; + --els + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + + i := 1;--to_integer(unsigned(BUS_RX.addr(7 downto 4))); + j := to_integer(unsigned(BUS_RX.addr(3 downto 0))); + if i <= OUTPUTS then + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '1'; + --if i = 0 then + -- if j = 0 then + -- --clock + -- BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + -- elsif j <= OUTPUTS then + -- --serial number of boards and potential error + -- BUS_TX.data(6 downto 0) <= serialNumbers(j - 1); + -- BUS_TX.data(8) <= parser_error(j - 1); + -- else + -- BUS_TX.unknown <= '1'; BUS_TX.ack <= '0'; + -- end if; + --else + case BUS_RX.addr(3 downto 0) is + -- sensor Mag: T, X, Y, Z + when x"0" => BUS_TX.data(27 downto 0) <= value_M_T(i-1)(27 downto 0); + when x"1" => BUS_TX.data(27 downto 0) <= value_M_X(i-1)(27 downto 0); + when x"2" => BUS_TX.data(27 downto 0) <= value_M_y(i-1)(27 downto 0); + when x"3" => BUS_TX.data(27 downto 0) <= value_M_Z(i-1)(27 downto 0); + -- sensor BME: T, P, H + when x"4" => BUS_TX.data(27 downto 0) <= value_BME_T(i-1)(27 downto 0); + when x"5" => BUS_TX.data(27 downto 0) <= value_BME_P(i-1)(27 downto 0); + when x"6" => BUS_TX.data(27 downto 0) <= value_BME_H(i-1)(27 downto 0); + -- sensor Light: L0, L1 + when x"7" => BUS_TX.data(27 downto 0) <= value_L_0(i-1)(27 downto 0); + when x"8" => BUS_TX.data(27 downto 0) <= value_L_1(i-1)(27 downto 0); + when x"9" => BUS_TX.data <= debug_i; + when x"A" => BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + when x"B" => BUS_TX.data(6 downto 0) <= serialNumbers(0); + BUS_TX.data(7) <= '0'; + BUS_TX.data(8) <= parser_error(0); + BUS_TX.data(31 downto 9) <= (others => '0'); + when others => BUS_TX.unknown <= '1'; BUS_TX.ack <= '0'; + end case; + --end if; + else + BUS_TX.unknown <= '1'; + end if; + end if; +end process; + + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; +end process; + +proc_io : process begin + wait until rising_edge(CLK); + UART_TX(0) <= '1'; +end process; + + +end architecture; + diff --git a/hub_cts/config.vhd b/hub_cts/config.vhd index aecb74a..e101028 100644 --- a/hub_cts/config.vhd +++ b/hub_cts/config.vhd @@ -49,7 +49,7 @@ package config is -- 0: KEL on board -- 1: Canadian constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 6; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, diff --git a/hub_cts/config_compile_gsi.pl b/hub_cts/config_compile_gsi.pl index 5929040..95c9da1 100644 --- a/hub_cts/config_compile_gsi.pl +++ b/hub_cts/config_compile_gsi.pl @@ -1,10 +1,10 @@ TOPNAME => "trb3sc_hubcts", lm_license_file_for_synplify => "27000\@lxcad03.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/opt/lattice/diamond/3.4_x64/', -synplify_path => '/opt/synplicity/J-2014.09-SP2', +lattice_path => '/opt/lattice/diamond/3.9_x64/', +synplify_path => '/opt/synplicity/K-2015.09', #synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", -synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", +#synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", nodelist_file => 'nodes_gsi_template.txt', pinout_file => 'trb3sc_hub', diff --git a/hub_cts/trb3sc_hubcts.prj b/hub_cts/trb3sc_hubcts.prj index 436e2be..ced8cdf 100644 --- a/hub_cts/trb3sc_hubcts.prj +++ b/hub_cts/trb3sc_hubcts.prj @@ -113,7 +113,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" -add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "./code/trb3sc_tools_mRICH.vhd" add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" @@ -312,6 +312,12 @@ add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Calc_output.vhd" add_file -vhdl -lib work "../../dirich/combiner_calib/core/RAM_pseudo_DP_wReg_36x1k.vhd" +#Sensors for Detector Monitoring +add_file -vhdl -lib work "../richSensors/code/onewire_multi.vhd" +add_file -vhdl -lib work "../richSensors/code/onewire_record.vhd" +add_file -vhdl -lib work "./code/uart_env.vhd" +add_file -vhdl -lib work "./code/EnvBoardParser.vhd" +add_file -vhdl -lib work "./code/EnvBoardParserHandler.vhd" add_file -vhdl -lib work "./trb3sc_hubcts.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/hub_cts/trb3sc_hubcts.vhd b/hub_cts/trb3sc_hubcts.vhd index 38b875c..5622a87 100644 --- a/hub_cts/trb3sc_hubcts.vhd +++ b/hub_cts/trb3sc_hubcts.vhd @@ -125,9 +125,9 @@ architecture trb3sc_arch of trb3sc_hubcts is signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx, - bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx,bustdccal_rx : CTRLBUS_RX; + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx,bustdccal_rx, bus_mbs_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx, - bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,bustdccal_tx : CTRLBUS_TX; + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,bustdccal_tx, bus_mbs_tx : CTRLBUS_TX; signal sed_error_i : std_logic; signal bus_master_active : std_logic; @@ -234,6 +234,8 @@ architecture trb3sc_arch of trb3sc_hubcts is attribute syn_preserve of bustools_rx : signal is true; attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; + attribute syn_keep of bus_mbs_rx : signal is true; + attribute syn_preserve of bus_mbs_rx : signal is true; begin @@ -811,7 +813,7 @@ end generate; CLK => clk_sys, RESET_IN => reset_i, - MBS_IN => SPARE_IN(0),--CLK_EXT(3), + MBS_IN => SPARE_IN(1),--CLK_EXT(3), CLK_200 => clk_full_osc, TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1), @@ -827,13 +829,16 @@ end generate; FINISHED_OUT => cts_rdo_additional(0).data_finished, STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + REGIO_IN => bus_mbs_rx, + REGIO_OUT => bus_mbs_tx, + CONTROL_REG_IN => cts_ext_control, STATUS_REG_OUT => cts_ext_status, HEADER_REG_OUT => cts_ext_header, DEBUG => cts_ext_debug ); - end generate; + end generate; --------------------------------------------------------------------------- @@ -841,9 +846,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"e000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 12 , others => 0), + PORT_NUMBER => 11, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"e000", 10 => x"e400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 9 , 10 => 9, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -863,6 +868,7 @@ end generate; BUS_RX(7) => buscts_rx, BUS_RX(8) => bustdc_rx, BUS_RX(9) => bustdccal_rx, + BUS_RX(10)=> bus_mbs_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci1_tx, @@ -873,6 +879,7 @@ end generate; BUS_TX(7) => buscts_tx, BUS_TX(8) => bustdc_tx, BUS_TX(9) => bustdccal_tx, + BUS_TX(10)=> bus_mbs_tx, STAT_DEBUG => open ); @@ -1059,8 +1066,10 @@ end generate; end generate; gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) and ((ETM_CHOICE = ETM_CHOICE_MBS_VULOM) and (INCLUDE_ETM = c_YES)) generate - hit_in_i(1) <= async_ext_trig;--INP(NUM_TDC_CHANNELS-2+64 downto 64); - hit_in_i(2) <= SPARE_IN(0); + hit_in_i(1) <= SPARE_IN(0);--INP(NUM_TDC_CHANNELS-2+64 downto 64); + hit_in_i(2) <= async_ext_trig; + hit_in_i(3) <= cts_ext_trigger; + hit_in_i(4) <= SPARE_IN(1); end generate;