From: Jan Michel <michel@physik.uni-frankfurt.de>
Date: Thu, 15 Feb 2024 13:23:22 +0000 (+0100)
Subject: add Trb3 periph inputs to regular Input multiplexers
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=33a3d6378a39ffa6cec5591ce5393a9f2d4af91d;p=trb3.git

add Trb3 periph inputs to regular Input multiplexers
---

diff --git a/cts/config_straw.vhd b/cts/config_straw.vhd
index 5704988..20b2aac 100644
--- a/cts/config_straw.vhd
+++ b/cts/config_straw.vhd
@@ -13,8 +13,9 @@ package config is
    constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; 
    constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
 
---include TDC for all four trigger input lines
+   constant FPGA_TYPE : integer := 3;
 
+--include TDC for all four trigger input lines
    constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
    constant TDC_CHANNEL_NUMBER : integer := 5;
    constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 0;  --double edge type:  0, 1, 2,  3
@@ -49,12 +50,12 @@ package config is
 --CLK RJ 3&4 can be used as output multiplexers?    
     constant USE_CLKRJ_AS_OUTMUX : integer := c_NO;
     
-    constant TRIGGER_COIN_COUNT   : integer := 2;
+    constant TRIGGER_COIN_COUNT   : integer := 3;
     constant TRIGGER_PULSER_COUNT : integer := 1;
     constant TRIGGER_RAND_PULSER  : integer := 1;
-    constant TRIGGER_ADDON_COUNT  : integer := 8;
+    constant TRIGGER_ADDON_COUNT  : integer := 7;
     constant PERIPH_TRIGGER_COUNT : integer := 4;
-    constant ADDON_LINE_COUNT        : integer := 38;    
+    constant ADDON_LINE_COUNT        : integer := 54;    
     constant CTS_OUTPUT_MULTIPLEXERS : integer := 8;
     
 
diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd
index 1254555..b01c83d 100755
--- a/cts/source/cts_trigger.vhd
+++ b/cts/source/cts_trigger.vhd
@@ -252,7 +252,7 @@ begin
       port map (
          CLK_IN => CLK_IN,
          RST_IN => RESET_IN,
-         DATA_IN => trigger_inputs_i(min(EFFECTIVE_INPUT_COUNT,7) downto 0),
+         DATA_IN => trigger_inputs_i(min(EFFECTIVE_INPUT_COUNT,8)-1 downto 0),
          TRIGGER_OUT => coins_i(i),
          CONFIG_IN => coin_config_i(i)
       );
diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t
index ba8b0ae..6d0584c 100644
--- a/cts/trb3_central.p2t
+++ b/cts/trb3_central.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 15
--t 27
+-t 28
 -c 1
 -e 2
 #-g guidefile.ncd
diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index fd565be..8ae576e 100644
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -53,7 +53,7 @@ project -result_format "edif"
 project -result_file "workdir/trb3_central.edf"
 
 #implementation attributes
-
+set_option -vhdl2008 1
 set_option -vlog_std v2001
 set_option -project_relative_includes 1
 impl -active "workdir"
diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 6a1569d..a988beb 100644
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -458,11 +458,11 @@ architecture trb3_central_arch of trb3_central is
    signal cts_rdo_trg_information            : std_logic_vector(23 downto 0);
    signal cts_rdo_trg_number                 : std_logic_vector(15 downto 0);
       
-   constant CTS_ADDON_LINE_COUNT      : integer := 38;
+   --constant CTS_ADDON_LINE_COUNT      : integer := 38;
    constant CTS_OUTPUT_MULTIPLEXERS   : integer :=  8;
    constant CTS_OUTPUT_INPUTS         : integer := 16;
 
-   signal cts_addon_triggers_in       : std_logic_vector(CTS_ADDON_LINE_COUNT-1 downto 0);
+   signal cts_addon_triggers_in       : std_logic_vector(ADDON_LINE_COUNT-1 downto 0);
    signal cts_addon_activity_i,
          cts_addon_selected_i        : std_logic_vector(6 downto 0);
          
@@ -787,6 +787,10 @@ end generate;
     cts_addon_triggers_in(20)           <= or_all(jin2_corrected);
     cts_addon_triggers_in(21)           <= or_all(NIM_IN);
     cts_addon_triggers_in(37 downto 22) <= JTTL;
+    cts_addon_triggers_in(53 downto 38) <= FPGA4_COMM(10 downto 7)
+                                          & FPGA3_COMM(10 downto 7)
+                                          & FPGA2_COMM(10 downto 7)
+                                          & FPGA1_COMM(10 downto 7);
 
     LED_BANK(7 downto 6) <= cts_addon_activity_i(4 downto 3);
     LED_RJ_GREEN <= (