From: Tobias Weber Date: Wed, 10 Jan 2018 17:33:09 +0000 (+0100) Subject: work on trigger handler X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=33ced2820eac3c45e11073f502b776242a32d9f0;p=trb3.git work on trigger handler --- diff --git a/mupix/Mupix8/sources/ReadoutController.vhd b/mupix/Mupix8/sources/ReadoutController.vhd index c1e2016..fcc04f6 100644 --- a/mupix/Mupix8/sources/ReadoutController.vhd +++ b/mupix/Mupix8/sources/ReadoutController.vhd @@ -94,6 +94,7 @@ begin triggerwaitcounter <= (others => '0'); headercounter <= 0; if start = '1' then + busy <= '1'; if mode = "00" then if empty = '0' then readout_fsm <= read_single; @@ -102,13 +103,10 @@ begin data_valid <= '1'; readout_fsm <= idle; end if; - busy <= '1'; elsif mode = "01" then readout_fsm <= header; - busy <= '1'; elsif mode = "10" then readout_fsm <= header; - busy <= '1'; else readout_fsm <= idle; end if; diff --git a/mupix/Mupix8/sources/TriggerHandler.vhd b/mupix/Mupix8/sources/TriggerHandler.vhd index dd260c5..b32eac8 100644 --- a/mupix/Mupix8/sources/TriggerHandler.vhd +++ b/mupix/Mupix8/sources/TriggerHandler.vhd @@ -6,10 +6,9 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; ---use work.trb3_components.all; +--TODO: revisit trigger handling in trbnet manual +--TODO: what is the timing between timing trigger and LVL1_Trigger information? + entity TriggerHandler is port ( @@ -26,9 +25,7 @@ entity TriggerHandler is LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - + --Response from FEE FEE_DATA_OUT : out std_logic_vector(31 downto 0); FEE_DATA_WRITE_OUT : out std_logic; @@ -40,16 +37,11 @@ entity TriggerHandler is FEE_DATA_WRITE_0_IN : in std_logic; -- Trigger FeedBack - TRIGGER_BUSY_MUPIX_READ_IN : in std_logic; - TRIGGER_BUSY_FIFO_READ_IN : in std_logic; + TRIGGER_BUSY_BUFFER_READ_IN : in std_logic; -- OUT VALID_TRIGGER_OUT : out std_logic; - TRIGGER_TIMING_OUT : out std_logic; - TRIGGER_STATUS_OUT : out std_logic; - FAST_CLEAR_OUT : out std_logic;--clear event buffer - FLUSH_BUFFER_OUT : out std_logic; - + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -66,18 +58,13 @@ end entity TriggerHandler; architecture behavioral of TriggerHandler is --trigger - signal bypass_trigger : std_logic := '0'; - signal reset_trigger_state : std_logic := '0'; - signal reset_trigger_state_edge : std_logic_vector(1 downto 0) := "00"; - signal valid_trigger_int : std_logic := '0'; - signal timing_trigger_int : std_logic := '0'; - signal timing_trigger_edge : std_logic_vector(1 downto 0) := "00"; - signal status_trigger_int : std_logic := '0'; - signal fast_clear_int : std_logic := '0'; - signal flush_buffer_int : std_logic := '0'; - signal trigger_busy_int : std_logic := '0'; - signal mupix_readout_end_int : std_logic_vector(1 downto 0) := "00"; - signal fifo_readout_end_int : std_logic_vector(1 downto 0) := "00"; + signal bypass_trigger : std_logic := '0'; + signal reset_trigger_state : std_logic := '0'; + signal reset_trigger_state_edge : std_logic_vector(1 downto 0) := "00"; + signal valid_trigger_int : std_logic := '0'; + signal timing_trigger_edge : std_logic_vector(1 downto 0) := "00"; + signal trigger_busy_int : std_logic := '0'; + signal buffer_readout_end_int : std_logic_vector(1 downto 0) := "00"; --fee signal fee_data_int : std_logic_vector(31 downto 0) := (others => '0'); signal fee_data_write_int : std_logic := '0'; @@ -87,20 +74,20 @@ architecture behavioral of TriggerHandler is --event buffer --registers - signal reset_trigger_counters : std_logic := '0'; + signal reset_trigger_counters : std_logic := '0'; signal reset_trigger_counters_edge : std_logic_vector(1 downto 0) := (others => '0'); - signal trigger_rate_acc : unsigned(31 downto 0) := (others => '0'); - signal trigger_rate_tot : unsigned(31 downto 0) := (others => '0'); - signal trigger_rate_time_counter : unsigned(31 downto 0) := (others => '0'); - signal invalid_trigger_counter : unsigned(31 downto 0) := (others => '0'); - signal valid_trigger_counter : unsigned(31 downto 0) := (others => '0'); - signal invalid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); - signal valid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); - signal trigger_handler_state : std_logic_vector(7 downto 0) := (others => '0'); + signal trigger_rate_acc : unsigned(31 downto 0) := (others => '0'); + signal trigger_rate_tot : unsigned(31 downto 0) := (others => '0'); + signal trigger_rate_time_counter : unsigned(31 downto 0) := (others => '0'); + signal invalid_trigger_counter : unsigned(31 downto 0) := (others => '0'); + signal valid_trigger_counter : unsigned(31 downto 0) := (others => '0'); + signal invalid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); + signal valid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); + signal trigger_handler_state : std_logic_vector(7 downto 0) := (others => '0'); --trigger types - constant trigger_physics_type : std_logic_vector(3 downto 0) := x"1"; - constant trigger_status_type : std_logic_vector(3 downto 0) := x"e"; + constant c_trigger_physics_type : std_logic_vector(3 downto 0) := x"1"; + constant c_trigger_status_type : std_logic_vector(3 downto 0) := x"e"; --trigger handler type trigger_handler_type is (idle, @@ -108,7 +95,6 @@ architecture behavioral of TriggerHandler is no_timing_trigger, check_trigger_type, status_trigger, - write_data_to_eventbuffer, write_data_to_ipu, trigger_release_a, trigger_release_b, @@ -126,298 +112,276 @@ architecture behavioral of TriggerHandler is signal trigger_handler_fsm : trigger_handler_type := idle; signal trigger_type : trigger_type_type := t_unknown; - signal wr_header_int : std_logic := '0'; - signal wr_data_int : std_logic := '0'; - signal wr_status_int : std_logic := '0'; - signal wr_dummy_int : std_logic := '0'; + signal wr_header_int : std_logic := '0'; + signal wr_data_int : std_logic := '0'; + signal wr_status_int : std_logic := '0'; + signal wr_dummy_int : std_logic := '0'; begin - Signal_Edge_Detect: process (CLK_IN) is - begin -- process Mupix_Readout_End_Detect - if rising_edge(CLK_IN) then - mupix_readout_end_int <= mupix_readout_end_int(0) & TRIGGER_BUSY_MUPIX_READ_IN; - fifo_readout_end_int <= fifo_readout_end_int(0) & TRIGGER_BUSY_FIFO_READ_IN; - timing_trigger_edge <= timing_trigger_edge(0) & TIMING_TRIGGER_IN; - reset_trigger_state_edge <= reset_trigger_state_edge(1) & reset_trigger_state; - end if; - end process Signal_Edge_Detect; + Signal_Edge_Detect : process(CLK_IN) is + begin -- process Mupix_Readout_End_Detect + if rising_edge(CLK_IN) then + buffer_readout_end_int <= buffer_readout_end_int(0) & TRIGGER_BUSY_BUFFER_READ_IN; + timing_trigger_edge <= timing_trigger_edge(0) & TIMING_TRIGGER_IN; + reset_trigger_state_edge <= reset_trigger_state_edge(1) & reset_trigger_state; + end if; + end process Signal_Edge_Detect; ------------------------------------------------------------ --Handling of LVL1 triggers ------------------------------------------------------------ - trigger_handler_proc: process is - begin -- process trigger_handler_proc - wait until rising_edge(clk_in); - valid_trigger_int <= '0'; - timing_trigger_int <= '0'; - status_trigger_int <= '0'; - flush_buffer_int <= '0'; - fee_data_finished_int <= '0'; - fee_trg_release_int <= '0'; - fee_trg_statusbit_int <= (others => '0'); - fast_clear_int <= '0'; - trigger_busy_int <= '1'; - fast_clear_int <= '0'; - fee_trg_release_int <= '0'; - wr_header_int <= '0'; - wr_data_int <= '0'; - wr_status_int <= '0'; - wr_dummy_int <= '0'; - if LVL1_INVALID_TRG_IN = '1' or reset_trigger_state_edge = "01" then - fast_clear_int <= '1'; - fee_trg_release_int <= '1'; - trigger_handler_fsm <= idle; - else - case trigger_handler_fsm is - when idle => - trigger_busy_int <= '0'; - trigger_handler_state <= x"01"; - if LVL1_VALID_TIMING_TRG_IN = '1' then - wr_header_int <= '1'; - if bypass_trigger = '1' then - trigger_type <= t_ignore; - trigger_handler_fsm <= ignore; - else - trigger_type <= t_timing; - trigger_handler_fsm <= timing_trigger; - end if; - elsif(LVL1_VALID_NOTIMING_TRG_IN = '1') then - wr_header_int <= '1'; - if bypass_trigger = '1' then - trigger_type <= t_ignore; - trigger_handler_fsm <= ignore; - else - trigger_handler_fsm <= check_trigger_type; - end if; - end if; - - when check_trigger_type => - trigger_handler_state <= x"02"; - if(LVL1_TRG_DATA_VALID_IN = '1') then - if(LVL1_TRG_TYPE_IN = trigger_status_type) then - trigger_type <= t_status; - trigger_handler_fsm <= no_timing_trigger; - elsif(LVL1_TRG_TYPE_IN = trigger_physics_type) then - trigger_type <= t_physics; - trigger_handler_fsm <= no_timing_trigger; - else - --unknown trigger - trigger_type <= t_unknown; - trigger_handler_fsm <= no_timing_trigger; - end if; - else - trigger_handler_fsm <= check_trigger_type; - end if; - - when timing_trigger =>--starts mupix readout fsm - trigger_handler_state <= x"03"; - valid_trigger_int <= '1'; - timing_trigger_int <= '1'; - trigger_handler_fsm <= write_data_to_eventbuffer; - - when no_timing_trigger => - trigger_handler_state <= x"04"; - if trigger_type = t_physics then - trigger_handler_fsm <= timing_trigger; - elsif trigger_type = t_status then - trigger_handler_fsm <= status_trigger; - else - trigger_handler_fsm <= ignore; - end if; - - when ignore => - wr_dummy_int <= '1'; --write a dummy value to identify - --inactive FEE - trigger_handler_state <= x"05"; - trigger_handler_fsm <= wait_trigger_data_valid_b; - - when status_trigger => --dummy implementation - trigger_handler_state <= x"06"; - wr_status_int <= '1'; - trigger_handler_fsm <= wait_trigger_data_valid_b; - - when write_data_to_eventbuffer => - trigger_handler_state <= x"07"; - if mupix_readout_end_int = "10" then - trigger_handler_fsm <= write_data_to_ipu; - flush_buffer_int <= '1'; - else - trigger_handler_fsm <= write_data_to_eventbuffer; - end if; - - when write_data_to_ipu => - trigger_handler_state <= x"0A"; - wr_data_int <= '1'; - if fifo_readout_end_int = "10" then - wr_data_int <= '0'; - trigger_handler_fsm <= wait_trigger_data_valid_a; - else - trigger_handler_fsm <= write_data_to_ipu; - end if; - - when wait_trigger_data_valid_a => - trigger_handler_state <= x"0B"; - if LVL1_TRG_DATA_VALID_IN = '1' then - trigger_handler_fsm <= wait_trigger_data_valid_b; - end if; - - when wait_trigger_data_valid_b => - trigger_handler_state <= x"0C"; - trigger_handler_fsm <= trigger_release_a; - - when trigger_release_a => - trigger_handler_state <= x"0D"; - trigger_handler_fsm <= trigger_release_b; - - when trigger_release_b => - trigger_handler_state <= x"0E"; - fee_data_finished_int <= '1'; - trigger_handler_fsm <= trigger_release_c; - - when trigger_release_c => - trigger_handler_state <= x"0F"; - fee_trg_release_int <= '1'; - trigger_handler_fsm <= wait_trigger_release; - - when wait_trigger_release => - if(LVL1_TRG_DATA_VALID_IN = '1') then - trigger_handler_fsm <= wait_trigger_release; - else - trigger_handler_fsm <= idle; - end if; - end case; - end if; - end process trigger_handler_proc; + trigger_handler_proc : process is + begin -- process trigger_handler_proc + wait until rising_edge(clk_in); + valid_trigger_int <= '0'; + fee_data_finished_int <= '0'; + fee_trg_release_int <= '0'; + fee_trg_statusbit_int <= (others => '0'); + trigger_busy_int <= '1'; + fee_trg_release_int <= '0'; + wr_header_int <= '0'; + wr_data_int <= '0'; + wr_status_int <= '0'; + wr_dummy_int <= '0'; + if LVL1_INVALID_TRG_IN = '1' or reset_trigger_state_edge = "01" then + fee_trg_release_int <= '1'; + trigger_handler_fsm <= idle; + else + case trigger_handler_fsm is + when idle => + trigger_busy_int <= '0'; + trigger_handler_state <= x"01"; + if LVL1_VALID_TIMING_TRG_IN = '1' then + wr_header_int <= '1'; + if bypass_trigger = '1' then + trigger_type <= t_ignore; + trigger_handler_fsm <= ignore; + else + trigger_type <= t_timing; + trigger_handler_fsm <= timing_trigger; + end if; + elsif (LVL1_VALID_NOTIMING_TRG_IN = '1') then + wr_header_int <= '1'; + if bypass_trigger = '1' then + trigger_type <= t_ignore; + trigger_handler_fsm <= ignore; + else + trigger_handler_fsm <= check_trigger_type; + end if; + end if; + + when check_trigger_type => + trigger_handler_state <= x"02"; + if (LVL1_TRG_DATA_VALID_IN = '1') then + if (LVL1_TRG_TYPE_IN = c_trigger_status_type) then + trigger_type <= t_status; + trigger_handler_fsm <= no_timing_trigger; + elsif (LVL1_TRG_TYPE_IN = c_trigger_physics_type) then + trigger_type <= t_physics; + trigger_handler_fsm <= no_timing_trigger; + else + --unknown trigger + trigger_type <= t_unknown; + trigger_handler_fsm <= no_timing_trigger; + end if; + else + trigger_handler_fsm <= check_trigger_type; + end if; + + when timing_trigger => --starts mupix readout fsm + trigger_handler_state <= x"03"; + valid_trigger_int <= '1'; + trigger_handler_fsm <= write_data_to_ipu; + + when no_timing_trigger => + trigger_handler_state <= x"04"; + if trigger_type = t_physics then + trigger_handler_fsm <= timing_trigger; + elsif trigger_type = t_status then + trigger_handler_fsm <= status_trigger; + else + trigger_handler_fsm <= ignore; + end if; + + when ignore => + wr_dummy_int <= '1'; --write a dummy value to identify inactive FEE + trigger_handler_state <= x"05"; + trigger_handler_fsm <= wait_trigger_data_valid_b; + + when status_trigger => --dummy implementation + trigger_handler_state <= x"06"; + wr_status_int <= '1'; + trigger_handler_fsm <= wait_trigger_data_valid_b; + + when write_data_to_ipu => + trigger_handler_state <= x"0A"; + wr_data_int <= '1'; + if buffer_readout_end_int = "10" then + wr_data_int <= '0'; + trigger_handler_fsm <= wait_trigger_data_valid_a; + else + trigger_handler_fsm <= write_data_to_ipu; + end if; + + when wait_trigger_data_valid_a => + trigger_handler_state <= x"0B"; + if LVL1_TRG_DATA_VALID_IN = '1' then + trigger_handler_fsm <= wait_trigger_data_valid_b; + end if; + + when wait_trigger_data_valid_b => + trigger_handler_state <= x"0C"; + trigger_handler_fsm <= trigger_release_a; + + when trigger_release_a => + trigger_handler_state <= x"0D"; + trigger_handler_fsm <= trigger_release_b; + + when trigger_release_b => + trigger_handler_state <= x"0E"; + fee_data_finished_int <= '1'; + trigger_handler_fsm <= trigger_release_c; + + when trigger_release_c => + trigger_handler_state <= x"0F"; + fee_trg_release_int <= '1'; + trigger_handler_fsm <= wait_trigger_release; + + when wait_trigger_release => + if (LVL1_TRG_DATA_VALID_IN = '1') then + trigger_handler_fsm <= wait_trigger_release; + else + trigger_handler_fsm <= idle; + end if; + end case; + end if; + end process trigger_handler_proc; ------------------------------------------------------------ --Data Output Mux ------------------------------------------------------------ - Data_Out_Mux: process (clk_in) is - begin -- process Data_Out_Mux - if rising_edge(clk_in) then - if wr_header_int = '1' then - fee_data_write_int <= '1';--header see Hades DAQ user guide - fee_data_int <= "001" & "0" & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; - elsif wr_data_int = '1' then - fee_data_write_int <= FEE_DATA_WRITE_0_IN; - fee_data_int <= FEE_DATA_0_IN; - elsif wr_status_int = '1' then - fee_data_int <= x"deadbeef"; - fee_data_write_int <= '1'; - elsif wr_dummy_int = '1' then - fee_data_write_int <= '1' ; - fee_data_int <= x"fff00000"; - else - fee_data_write_int <= '0'; - fee_data_int <= (others => '1'); - end if; - end if; - end process Data_Out_Mux; + Data_Out_Mux : process(clk_in) is + begin -- process Data_Out_Mux + if rising_edge(clk_in) then + if wr_header_int = '1' then + fee_data_write_int <= '1'; --header see Hades DAQ user guide + fee_data_int <= "001" & "0" & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; + elsif wr_data_int = '1' then + fee_data_write_int <= FEE_DATA_WRITE_0_IN; + fee_data_int <= FEE_DATA_0_IN; + elsif wr_status_int = '1' then + fee_data_int <= x"deadbeef"; + fee_data_write_int <= '1'; + elsif wr_dummy_int = '1' then + fee_data_write_int <= '1'; + fee_data_int <= x"fff00000"; + else + fee_data_write_int <= '0'; + fee_data_int <= (others => '1'); + end if; + end if; + end process Data_Out_Mux; ------------------------------------------------------------ --Trigger statistics ------------------------------------------------------------ - Trigger_Statistics_Proc: process (clk_in) is - begin -- process Trigger_Statistics_Proc - if rising_edge(CLK_IN) then - reset_trigger_counters_edge <= reset_trigger_counters_edge(0) & reset_trigger_counters; - if reset_trigger_counters_edge = "01" then - trigger_rate_acc <= (others => '0'); - invalid_trigger_counter_t <= (others => '0'); - valid_trigger_counter_t <= (others => '0'); - trigger_rate_time_counter <= (others => '0'); - end if; - if trigger_rate_time_counter < x"5f5e100" then--1s at 10ns clock period - --if trigger_rate_time_counter < x"000007e" then - trigger_rate_time_counter <= trigger_rate_time_counter + 1; - if valid_trigger_int = '1' then - valid_trigger_counter_t <= valid_trigger_counter_t + 1; - elsif LVL1_INVALID_TRG_IN = '1' or (trigger_busy_int = '1' and timing_trigger_edge = "01") then - invalid_trigger_counter_t <= invalid_trigger_counter_t + 1; - end if; - else - valid_trigger_counter <= valid_trigger_counter + valid_trigger_counter_t; - invalid_trigger_counter <= invalid_trigger_counter + invalid_trigger_counter_t; - trigger_rate_acc <= valid_trigger_counter_t; - trigger_rate_tot <= valid_trigger_counter_t + invalid_trigger_counter_t; - trigger_rate_time_counter <= (others => '0'); - valid_trigger_counter_t <= (others => '0'); - invalid_trigger_counter_t <= (others => '0'); - end if; - end if; - end process Trigger_Statistics_Proc; + Trigger_Statistics_Proc : process(clk_in) is + begin -- process Trigger_Statistics_Proc + if rising_edge(CLK_IN) then + reset_trigger_counters_edge <= reset_trigger_counters_edge(0) & reset_trigger_counters; + if reset_trigger_counters_edge = "01" then + trigger_rate_acc <= (others => '0'); + invalid_trigger_counter_t <= (others => '0'); + valid_trigger_counter_t <= (others => '0'); + trigger_rate_time_counter <= (others => '0'); + end if; + if trigger_rate_time_counter < x"5f5e100" then --1s at 10ns clock period + --if trigger_rate_time_counter < x"000007e" then + trigger_rate_time_counter <= trigger_rate_time_counter + 1; + if valid_trigger_int = '1' then + valid_trigger_counter_t <= valid_trigger_counter_t + 1; + elsif LVL1_INVALID_TRG_IN = '1' or (trigger_busy_int = '1' and timing_trigger_edge = "01") then + invalid_trigger_counter_t <= invalid_trigger_counter_t + 1; + end if; + else + valid_trigger_counter <= valid_trigger_counter + valid_trigger_counter_t; + invalid_trigger_counter <= invalid_trigger_counter + invalid_trigger_counter_t; + trigger_rate_acc <= valid_trigger_counter_t; + trigger_rate_tot <= valid_trigger_counter_t + invalid_trigger_counter_t; + trigger_rate_time_counter <= (others => '0'); + valid_trigger_counter_t <= (others => '0'); + invalid_trigger_counter_t <= (others => '0'); + end if; + end if; + end process Trigger_Statistics_Proc; ------------------------------------------------------------ --TRB SLV-BUS Hanlder ------------------------------------------------------------ - --0x100: accepted trigger_rate - --0x101: total trigger_rate - --0x102: invalid triggers - --0x103: valid triggers - --0x104: trigger_handler_state - --0x105: reset counters - --0x106: reset trigger state machine - --0x107: bypass trigger signals flag + --0x200: accepted trigger_rate + --0x201: total trigger_rate + --0x202: invalid triggers + --0x203: valid triggers + --0x204: trigger_handler_state + --0x205: reset counters + --0x206: reset trigger state machine + --0x207: bypass trigger signals flag slv_bus_handler : process(CLK_IN) - begin - if rising_edge(CLK_IN) then - slv_data_out <= (others => '0'); - slv_ack_out <= '0'; - slv_no_more_data_out <= '0'; - slv_unknown_addr_out <= '0'; - - if slv_write_in = '1' then - case SLV_ADDR_IN is - when x"0105" => - reset_trigger_counters <= SLV_DATA_IN(0); - slv_ack_out <= '1'; - when x"0106" => - reset_trigger_state <= SLV_DATA_IN(0); - slv_ack_out <= '1'; - when x"0107"=> - bypass_trigger <= SLV_DATA_IN(0); - slv_ack_out <= '1'; - when others => - slv_unknown_addr_out <= '1'; - end case; - - elsif slv_read_in = '1' then - case slv_addr_in is - when x"0100" => - slv_data_out <= std_logic_vector(trigger_rate_acc); - slv_ack_out <= '1'; - when x"0101" => - slv_data_out <= std_logic_vector(trigger_rate_tot); - slv_ack_out <= '1'; - when x"0102" => - slv_data_out <= std_logic_vector(invalid_trigger_counter); - slv_ack_out <= '1'; - when x"0103" => - slv_data_out <= std_logic_vector(valid_trigger_counter); - slv_ack_out <= '1'; - when x"0104" => - slv_data_out <= x"000000" & trigger_handler_state; - slv_ack_out <= '1'; - when x"0107" => - slv_data_out(0) <= bypass_trigger; - slv_ack_out <= '1'; - when others => - slv_unknown_addr_out <= '1'; - end case; - - end if; - end if; - end process slv_bus_handler; + begin + if rising_edge(CLK_IN) then + slv_data_out <= (others => '0'); + slv_ack_out <= '0'; + slv_no_more_data_out <= '0'; + slv_unknown_addr_out <= '0'; + + if slv_write_in = '1' then + case SLV_ADDR_IN is + when x"0205" => + reset_trigger_counters <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when x"0206" => + reset_trigger_state <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when x"0207" => + bypass_trigger <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when others => + slv_unknown_addr_out <= '1'; + end case; + + elsif slv_read_in = '1' then + case slv_addr_in is + when x"0200" => + slv_data_out <= std_logic_vector(trigger_rate_acc); + slv_ack_out <= '1'; + when x"0201" => + slv_data_out <= std_logic_vector(trigger_rate_tot); + slv_ack_out <= '1'; + when x"0202" => + slv_data_out <= std_logic_vector(invalid_trigger_counter); + slv_ack_out <= '1'; + when x"0203" => + slv_data_out <= std_logic_vector(valid_trigger_counter); + slv_ack_out <= '1'; + when x"0204" => + slv_data_out <= x"000000" & trigger_handler_state; + slv_ack_out <= '1'; + when x"0207" => + slv_data_out(0) <= bypass_trigger; + slv_ack_out <= '1'; + when others => + slv_unknown_addr_out <= '1'; + end case; + + end if; + end if; + end process slv_bus_handler; --map output signals valid_trigger_out <= valid_trigger_int; - trigger_timing_out <= timing_trigger_int; - trigger_status_out <= status_trigger_int; - fast_clear_out <= fast_clear_int; - flush_buffer_out <= flush_buffer_int; fee_data_out <= fee_data_int; fee_data_write_out <= fee_data_write_int; fee_data_finished_out <= fee_data_finished_int;