From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Thu, 11 Jun 2015 11:17:39 +0000 (+0200)
Subject: Let's try with this ADC phase determination
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=33eec6ee8fef152c932e8c489907dedd0e4eada0;p=trb3.git

Let's try with this ADC phase determination
---

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index 6e875b2..2de252c 100644
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -404,15 +404,15 @@ begin
         );
     end generate;
     
-    ADC_CLK_TDC_OUT <= epoch_counter(10);
-    
     PROC_EPOCH_COUNTER : process is
     begin
       wait until rising_edge(adc_clk_left);
       epoch_counter <= epoch_counter + 1;
       trigger_in_i <= TRIGGER_IN;
+      ADC_CLK_TDC_OUT <= '0';
       if trigger_in_i = '1' then
         epoch_counter_save <= epoch_counter;
+        ADC_CLK_TDC_OUT <= '1';
       end if;
     end process PROC_EPOCH_COUNTER;