From: Jan Michel Date: Tue, 1 Oct 2013 16:00:53 +0000 (+0200) Subject: new cores for padiwa X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=345a3b421ced483e6c9441fc24a2c9ea148a9f0d;p=trb3.git new cores for padiwa --- diff --git a/wasa/cores/fifo_1kx8.ipx b/wasa/cores/fifo_1kx8.ipx new file mode 100644 index 0000000..f8ef24a --- /dev/null +++ b/wasa/cores/fifo_1kx8.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/wasa/cores/fifo_1kx8.lpc b/wasa/cores/fifo_1kx8.lpc new file mode 100644 index 0000000..a5e2b15 --- /dev/null +++ b/wasa/cores/fifo_1kx8.lpc @@ -0,0 +1,50 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-4000HC +PartName=LCMXO2-4000HC-6FTG256C +SpeedGrade=6 +Package=FTBGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_1kx8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/01/2013 +Time=14:08:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=1024 +RWidth=8 +WDepth=1024 +WWidth=8 +regout=1 +CtrlByRdEn=0 +ClockEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/wasa/cores/fifo_1kx8.vhd b/wasa/cores/fifo_1kx8.vhd new file mode 100644 index 0000000..d84aeaf --- /dev/null +++ b/wasa/cores/fifo_1kx8.vhd @@ -0,0 +1,123 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n fifo_1kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 8 -rwidth 8 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 10 -pf 508 -e + +-- Tue Oct 1 14:08:55 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO2; +use MACHXO2.components.all; +-- synopsys translate_on + +entity fifo_1kx8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_1kx8; + +architecture Structure of fifo_1kx8 is + + -- internal signal declarations + signal Empty_int: std_logic; + signal Full_int: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO8KB + generic (FULLPOINTER1 : in String; FULLPOINTER : in String; + AFPOINTER1 : in String; AFPOINTER : in String; + AEPOINTER1 : in String; AEPOINTER : in String; + ASYNC_RESET_RELEASE : in String; RESETMODE : in String; + GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + CSW0: in std_logic; CSW1: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; + FULLI: in std_logic; EMPTYI: in std_logic; + WE: in std_logic; RE: in std_logic; ORE: in std_logic; + CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic; + RPRST: in std_logic; DO0: out std_logic; + DO1: out std_logic; DO2: out std_logic; + DO3: out std_logic; DO4: out std_logic; + DO5: out std_logic; DO6: out std_logic; + DO7: out std_logic; DO8: out std_logic; + DO9: out std_logic; DO10: out std_logic; + DO11: out std_logic; DO12: out std_logic; + DO13: out std_logic; DO14: out std_logic; + DO15: out std_logic; DO16: out std_logic; + DO17: out std_logic; EF: out std_logic; + AEF: out std_logic; AFF: out std_logic; FF: out std_logic); + end component; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_1kx8_0_0: FIFO8KB + generic map (FULLPOINTER1=> "0b01111111111000", FULLPOINTER=> "0b10000000000000", + AFPOINTER1=> "0b00111111011000", AFPOINTER=> "0b00111111100000", + AEPOINTER1=> "0b00000001011000", AEPOINTER=> "0b00000001010000", + ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11", + DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo, + DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo, + DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, + DI17=>scuba_vlo, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + CSR0=>RdEn, CSR1=>scuba_vhi, FULLI=>Full_int, + EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, ORE=>scuba_vhi, + CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, + DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), + DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open, + DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, + DO15=>open, DO16=>open, DO17=>open, EF=>Empty_int, + AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library MACHXO2; +configuration Structure_CON of fifo_1kx8 is + for Structure + for all:VHI use entity MACHXO2.VHI(V); end for; + for all:VLO use entity MACHXO2.VLO(V); end for; + for all:FIFO8KB use entity MACHXO2.FIFO8KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/wasa/cores/pll_shifted_clocks.ipx b/wasa/cores/pll_shifted_clocks.ipx new file mode 100644 index 0000000..e872f6a --- /dev/null +++ b/wasa/cores/pll_shifted_clocks.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/wasa/cores/pll_shifted_clocks.lpc b/wasa/cores/pll_shifted_clocks.lpc new file mode 100644 index 0000000..4ad6b73 --- /dev/null +++ b/wasa/cores/pll_shifted_clocks.lpc @@ -0,0 +1,81 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-4000HC +PartName=LCMXO2-4000HC-6FTG256C +SpeedGrade=6 +Package=FTBGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=pll_shifted_clocks +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/01/2013 +Time=14:46:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +mode=Frequency +CLKI=133 +CLKI_DIV=1 +fb_mode=INT_OP +CLKFB_DIV=2 +FRACN_ENABLE=0 +FRACN_DIV=0 +DynamicPhase=STATIC +ClkEnable=0 +Standby=0 +PLLRst=0 +PLLMRst=0 +ClkOS2Rst=0 +ClkOS3Rst=0 +LockSig=0 +LockStk=0 +WBProt=0 +OPBypass=0 +OPUseDiv=0 +CLKOP_DIV=2 +FREQ_PIN_CLKOP=266 +OP_Tol=10.0 +CLKOP_AFREQ=266.000000 +CLKOP_PHASEADJ=0 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +EnCLKOS=1 +OSBypass=0 +OSUseDiv=0 +CLKOS_DIV=2 +FREQ_PIN_CLKOS=266 +OS_Tol=10.0 +CLKOS_AFREQ=266.000000 +CLKOS_PHASEADJ=45 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +EnCLKOS2=1 +OS2Bypass=0 +OS2UseDiv=0 +CLKOS2_DIV=2 +FREQ_PIN_CLKOS2=266 +OS2_Tol=10.0 +CLKOS2_AFREQ=266.000000 +CLKOS2_PHASEADJ=90 +EnCLKOS3=1 +OS3Bypass=0 +OS3UseDiv=0 +CLKOS3_DIV=2 +FREQ_PIN_CLKOS3=266 +OS3_Tol=10.0 +CLKOS3_AFREQ=266.000000 +CLKOS3_PHASEADJ=135 diff --git a/wasa/cores/pll_shifted_clocks.vhd b/wasa/cores/pll_shifted_clocks.vhd new file mode 100644 index 0000000..043f2b9 --- /dev/null +++ b/wasa/cores/pll_shifted_clocks.vhd @@ -0,0 +1,174 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 -e + +-- Tue Oct 1 14:46:56 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO2; +use MACHXO2.components.all; +-- synopsys translate_on + +entity pll_shifted_clocks is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic; + CLKOS3: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_shifted_clocks : entity is true; +end pll_shifted_clocks; + +architecture Structure of pll_shifted_clocks is + + -- internal signal declarations + signal LOCK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EHXPLLJ + generic (INTFB_WAKE : in String; DDRST_ENA : in String; + DCRST_ENA : in String; MRST_ENA : in String; + PLLRST_ENA : in String; DPHASE_SOURCE : in String; + OUTDIVIDER_MUXD2 : in String; + OUTDIVIDER_MUXC2 : in String; + OUTDIVIDER_MUXB2 : in String; + OUTDIVIDER_MUXA2 : in String; + PREDIVIDER_MUXD1 : in Integer; + PREDIVIDER_MUXC1 : in Integer; + PREDIVIDER_MUXB1 : in Integer; + PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String; + PLL_LOCK_MODE : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer; + FRACN_ENABLE : in String; FEEDBK_PATH : in String; + CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer; + CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer; + CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer; + CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer; + VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String; + VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String; + CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String; + CLKOS_ENABLE : in String; CLKOP_ENABLE : in String; + CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer; + CLKOS_DIV : in Integer; CLKOP_DIV : in Integer; + CLKFB_DIV : in Integer; CLKI_DIV : in Integer); + port (CLKI: in std_logic; CLKFB: in std_logic; + PHASESEL1: in std_logic; PHASESEL0: in std_logic; + PHASEDIR: in std_logic; PHASESTEP: in std_logic; + LOADREG: in std_logic; STDBY: in std_logic; + PLLWAKESYNC: in std_logic; RST: in std_logic; + RESETM: in std_logic; RESETC: in std_logic; + RESETD: in std_logic; ENCLKOP: in std_logic; + ENCLKOS: in std_logic; ENCLKOS2: in std_logic; + ENCLKOS3: in std_logic; PLLCLK: in std_logic; + PLLRST: in std_logic; PLLSTB: in std_logic; + PLLWE: in std_logic; PLLADDR4: in std_logic; + PLLADDR3: in std_logic; PLLADDR2: in std_logic; + PLLADDR1: in std_logic; PLLADDR0: in std_logic; + PLLDATI7: in std_logic; PLLDATI6: in std_logic; + PLLDATI5: in std_logic; PLLDATI4: in std_logic; + PLLDATI3: in std_logic; PLLDATI2: in std_logic; + PLLDATI1: in std_logic; PLLDATI0: in std_logic; + CLKOP: out std_logic; CLKOS: out std_logic; + CLKOS2: out std_logic; CLKOS3: out std_logic; + LOCK: out std_logic; INTLOCK: out std_logic; + REFCLK: out std_logic; CLKINTFB: out std_logic; + DPHSRC: out std_logic; PLLACK: out std_logic; + PLLDATO7: out std_logic; PLLDATO6: out std_logic; + PLLDATO5: out std_logic; PLLDATO4: out std_logic; + PLLDATO3: out std_logic; PLLDATO2: out std_logic; + PLLDATO1: out std_logic; PLLDATO0: out std_logic); + end component; + attribute STDBY_ENABLE : string; + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute STDBY_ENABLE of PLLInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "266.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "266.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "266.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "266.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "10"; + attribute LPF_RESISTOR of PLLInst_0 : label is "24"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLJ + generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED", + MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + DPHASE_SOURCE=> "DISABLED", PLL_USE_WB=> "DISABLED", + CLKOS3_FPHASE=> 6, CLKOS3_CPHASE=> 1, CLKOS2_FPHASE=> 4, + CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 2, CLKOS_CPHASE=> 1, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0, + FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD", + PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED", + OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED", + CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB", + PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED", + CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2, CLKOS2_DIV=> 2, + CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1, + FEEDBK_PATH=> "INT_DIVA") + port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo, + PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo, + RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo, + ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, + PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo, + PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo, + PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo, + PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo, + PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo, + PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo, + PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo, + PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK, + INTLOCK=>open, REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open, + PLLACK=>open, PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open, + PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open, + PLLDATO1=>open, PLLDATO0=>open); + + CLKOS3 <= CLKOS3_t; + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library MACHXO2; +configuration Structure_CON of pll_shifted_clocks is + for Structure + for all:VLO use entity MACHXO2.VLO(V); end for; + for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on