From: Jan Michel Date: Mon, 21 Nov 2016 13:40:48 +0000 (+0100) Subject: Update input statistics to be able to use external trigger X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3477e11fc9a51184330058703cb8fe2631afc39d;p=trb3.git Update input statistics to be able to use external trigger Add monitoring FPGA design, w/o read-out --- diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd index 99ebf73..37ae757 100644 --- a/base/code/input_statistics.vhd +++ b/base/code/input_statistics.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; entity input_statistics is generic( INPUTS : integer range 1 to 96 := 16; + LARGE_FIFO : integer := 0; SINGLE_FIFO_ONLY : integer := 0 ); port( @@ -34,7 +35,10 @@ signal inp_inv : std_logic_vector(INPUTS-1 downto 0); signal inp_stretch : std_logic_vector(INPUTS-1 downto 0); signal inp_reg_95 : std_logic_vector(95 downto 0); -signal trigger_fifo : std_logic; +signal trigger_fifo, trigger_fifo_buf : std_logic; +signal trigger_fifo_real, trigger_fifo_external : std_logic := '0'; +signal trigger_fifo_channel : integer range 0 to 31; +signal trigger_fifo_channel_enable : std_logic; signal reset_cnt : std_logic; signal timer_rst : std_logic; @@ -57,11 +61,11 @@ signal cnt : cnt_t; type dout_t is array(0 to LAST_FIFO_NUM) of std_logic_vector(17 downto 0); signal fifo_dout : dout_t; -type fifo_count_t is array(0 to LAST_FIFO_NUM) of std_logic_vector(10 downto 0); +type fifo_count_t is array(0 to LAST_FIFO_NUM) of std_logic_vector(10+LARGE_FIFO*3 downto 0); signal fifo_count : fifo_count_t; signal timer : unsigned(31 downto 0); -signal word_cnt : unsigned(11 downto 0); +signal word_cnt : unsigned(15 downto 0); type state_t is (IDLE,RUN,CHECK); signal state : state_t; @@ -99,6 +103,8 @@ begin when x"f" => trigger_fifo <= DATA_IN(0); reset_cnt <= DATA_IN(1); fifo_in_sel <= to_integer(unsigned(DATA_IN(20 downto 16))); + trigger_fifo_channel_enable <= DATA_IN(31); + trigger_fifo_channel <= to_integer(unsigned(DATA_IN(28 downto 24))); when others => NACK_OUT <= '1'; ACK_OUT <= '0'; end case; else @@ -123,6 +129,8 @@ begin when x"f" => DATA_OUT <= (others => '0'); DATA_OUT(20 downto 16) <= std_logic_vector(to_unsigned(fifo_in_sel,5)); DATA_OUT(14 downto 8) <= std_logic_vector(to_unsigned(INPUTS,7)); DATA_OUT(15 downto 15) <= std_logic_vector(to_unsigned(SINGLE_FIFO_ONLY,1)); + DATA_OUT(28 downto 24) <= std_logic_vector(to_unsigned(trigger_fifo_channel,5)); + DATA_OUT(31) <= trigger_fifo_channel_enable; when others => DATA_OUT <= (others => '0'); end case; elsif ADDR_IN(6 downto 5) = "01" and ((tmp < INPUTS and SINGLE_FIFO_ONLY = c_NO) or (tmp = 0 and SINGLE_FIFO_ONLY = c_YES)) then @@ -171,12 +179,31 @@ gen_counters : for i in 0 to INPUTS-1 generate end generate; +gen_external_trigger : process begin + wait until rising_edge(CLK); + trigger_fifo_external <= '0'; + if trigger_fifo = '1' then + trigger_fifo_buf <= '1'; + end if; + + if trigger_fifo_buf = '1' then + if trigger_fifo_channel_enable = '0' or + (inp_reg(trigger_fifo_channel) = not invert(trigger_fifo_channel) and + inp_reg_last(trigger_fifo_channel) = invert(trigger_fifo_channel)) then + trigger_fifo_external <= '1'; + trigger_fifo_buf <= '0'; + end if; + end if; +end process; + +trigger_fifo_real <= trigger_fifo_external; + proc_ctrl : process begin wait until rising_edge(CLK); fifo_write <= '0'; case state is when IDLE => - if trigger_fifo = '1' then + if trigger_fifo_real = '1' then state <= RUN; word_cnt <= (others => '0'); end if; @@ -190,7 +217,7 @@ proc_ctrl : process begin end if; when CHECK => - if word_cnt = x"400" then + if (word_cnt = x"0400" and LARGE_FIFO = 0) or (word_cnt = x"2000" and LARGE_FIFO = 1) then state <= IDLE; else state <= RUN; @@ -201,51 +228,72 @@ proc_ctrl : process begin end if; end process; +gen_small_fifo : if LARGE_FIFO = 0 generate + gen_all_fifo : if SINGLE_FIFO_ONLY = c_NO generate + gen_fifos : for i in 0 to INPUTS-1 generate + THE_FIFO : entity work.fifo_18x1k_oreg + port map ( + Data => std_logic_vector(cnt(i)(17 downto 0)), + Clock => CLK, + WrEn => fifo_write, + RdEn => fifo_read(i), + Reset => trigger_fifo_real, + AmFullThresh => "1000000000", + Q => fifo_dout(i), + WCNT => fifo_count(i), + Empty => fifo_empty(i), + Full => open, + AlmostFull => open + ); + end generate; + end generate; -gen_all_fifo : if SINGLE_FIFO_ONLY = c_NO generate - gen_fifos : for i in 0 to INPUTS-1 generate + gen_single_fifo : if SINGLE_FIFO_ONLY = c_YES generate THE_FIFO : entity work.fifo_18x1k_oreg port map ( - Data => std_logic_vector(cnt(i)(17 downto 0)), + Data => fifo_cnt_in, Clock => CLK, WrEn => fifo_write, - RdEn => fifo_read(i), - Reset => trigger_fifo, + RdEn => fifo_read(0), + Reset => trigger_fifo_real, AmFullThresh => "1000000000", - Q => fifo_dout(i), - WCNT => fifo_count(i), - Empty => fifo_empty(i), + Q => fifo_dout(0), + WCNT => fifo_count(0), + Empty => fifo_empty(0), Full => open, AlmostFull => open ); + + fifo_cnt_in <= std_logic_vector(cnt(fifo_in_sel)(17 downto 0)) when rising_edge(CLK); + end generate; end generate; - -gen_single_fifo : if SINGLE_FIFO_ONLY = c_YES generate - THE_FIFO : entity work.fifo_18x1k_oreg - port map ( - Data => fifo_cnt_in, - Clock => CLK, - WrEn => fifo_write, - RdEn => fifo_read(0), - Reset => trigger_fifo, - AmFullThresh => "1000000000", - Q => fifo_dout(0), - WCNT => fifo_count(0), - Empty => fifo_empty(0), - Full => open, - AlmostFull => open - ); - - fifo_cnt_in <= std_logic_vector(cnt(fifo_in_sel)(17 downto 0)) when rising_edge(CLK); +gen_big_fifo : if LARGE_FIFO = 1 generate + gen_all_fifo : if SINGLE_FIFO_ONLY = c_NO generate + gen_fifos : for i in 0 to INPUTS-1 generate + THE_FIFO : entity work.fifo_18x8k_oreg + port map ( + Data => std_logic_vector(cnt(i)(17 downto 0)), + Clock => CLK, + WrEn => fifo_write, + RdEn => fifo_read(i), + Reset => trigger_fifo_real, + AmFullThresh => "1000000000000", + Q => fifo_dout(i), + WCNT => fifo_count(i), + Empty => fifo_empty(i), + Full => open, + AlmostFull => open + ); + end generate; + end generate; end generate; -status_reg(10 downto 0) <= fifo_count(0); -status_reg(11) <= fifo_write; -status_reg(15 downto 12)<= (others => '0'); -status_reg(27 downto 16)<= std_logic_vector(word_cnt); -status_reg(31 downto 28)<= (others => '0'); +status_reg(10+LARGE_FIFO*3 downto 0) <= fifo_count(0); +status_reg(15) <= fifo_write; +status_reg(31 downto 16)<= std_logic_vector(word_cnt); +-- status_reg(31 downto 28)<= (others => '0'); end architecture; \ No newline at end of file diff --git a/monitor/compile.pl b/monitor/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/monitor/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/monitor/config.vhd b/monitor/config.vhd new file mode 100644 index 0000000..0de69d2 --- /dev/null +++ b/monitor/config.vhd @@ -0,0 +1,100 @@ +library ieee; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 9; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 32; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 36; + constant USE_SINGLE_FIFO : integer := c_NO; -- single fifo for statistics + + --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F308"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"41"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + others => x"00"); + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91004000"; + constant CLOCK_FREQUENCY_ARR : intlist_t := (100, 125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200, 125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + +function generateIncludedFeatures return std_logic_vector; + + + +end; + +package body config is +--compute correct configuration mode + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2 + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1)); + return t; +end function; + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + + constant INCLUDED_FEATURES : std_logic_vector := generateIncludedFeatures; +end package body; diff --git a/monitor/config_compile_frankfurt.pl b/monitor/config_compile_frankfurt.pl new file mode 100644 index 0000000..5fee652 --- /dev/null +++ b/monitor/config_compile_frankfurt.pl @@ -0,0 +1,24 @@ +TOPNAME => "trb3_periph_monitor", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb07.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.8_x64', +synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodes_frankfurt.txt', +pinout_file => 'trb3_periph_padiwa', + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + +Familyname => 'LatticeECP3', +Devicename => 'LFE3-150EA', +Package => 'FPBGA672', +Speedgrade => '8', \ No newline at end of file diff --git a/monitor/config_compile_gsi.pl b/monitor/config_compile_gsi.pl new file mode 100644 index 0000000..b716440 --- /dev/null +++ b/monitor/config_compile_gsi.pl @@ -0,0 +1,18 @@ +TOPNAME => "trb3_blank", +project_path => "blank", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.6_x64', +synplify_path => '/opt/synplicity/K-2015.09', +#synplify_command => "/opt/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => '../nodes_lxhadeb07.txt', + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, diff --git a/monitor/par.p2t b/monitor/par.p2t new file mode 100644 index 0000000..a7b741d --- /dev/null +++ b/monitor/par.p2t @@ -0,0 +1,69 @@ +-w +-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 12 +-t 1 +-c 1 +-e 2 +-i 15 +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + + +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help diff --git a/monitor/trb3_periph_monitor.lpf b/monitor/trb3_periph_monitor.lpf new file mode 100644 index 0000000..bb534d0 --- /dev/null +++ b/monitor/trb3_periph_monitor.lpf @@ -0,0 +1,38 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; + +################################################################# +# Locate Serdes and media interfaces +################################################################# + +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + + + +################################################################# +# Clocks +################################################################# +USE PRIMARY NET "CLK_PCLK_RIGHT_c"; diff --git a/monitor/trb3_periph_monitor.prj b/monitor/trb3_periph_monitor.prj new file mode 100644 index 0000000..05a6aa7 --- /dev/null +++ b/monitor/trb3_periph_monitor.prj @@ -0,0 +1,162 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph_monitor" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 + +# Lattice XP +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph_monitor.edf" + +#implementation attributes +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +# design plan options +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" + +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3/base/code/trb3_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../base/code/input_statistics.vhd" +add_file -vhdl -lib work "../base/code/sedcheck.vhd" + + +add_file -vhdl -lib work "trb3_periph_monitor.vhd" + diff --git a/monitor/trb3_periph_monitor.vhd b/monitor/trb3_periph_monitor.vhd new file mode 100644 index 0000000..fa60f15 --- /dev/null +++ b/monitor/trb3_periph_monitor.vhd @@ -0,0 +1,399 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.config.all; +use work.version.all; + + +entity trb3_periph_monitor is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Bit 10-7 trigger to CTS + --Connection to AddOn + INP : in std_logic_vector(63 downto 0); + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --DAC + OUT_SDO : out std_logic_vector(4 downto 1); + IN_SDI : in std_logic_vector(4 downto 1); + OUT_SCK : out std_logic_vector(4 downto 1); + OUT_CS : out std_logic_vector(4 downto 1); + + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + --Test Connectors + TEST_LINE : inout std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + + + +end entity; + + +architecture arch of trb3_periph_monitor is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + + signal timing_trg_received_i : std_logic; + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + --Slow Control channel + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal ctrlbus_rx, busrdo_rx, bustools_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, busrdo_tx, bustools_tx, bus_master_in : CTRLBUS_TX; + signal bus_master_active : std_logic; + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal lcd_out : std_logic_vector(4 downto 0); + signal feature_outputs_i : std_logic_vector(15 downto 0); + signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0); + signal uart_rx, uart_tx, debug_rx, debug_tx : std_logic; + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal sed_error_i : std_logic; + signal serdes_i : std_logic_vector(3 downto 0); + attribute nopad : string; + attribute nopad of serdes_i : signal is "true"; + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + RESET => '0', + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => int2med(0).data, + MED_PACKET_NUM_IN => int2med(0).packet_num, + MED_DATAREADY_IN => int2med(0).dataready, + MED_READ_OUT => med2int(0).tx_read, + MED_DATA_OUT => med2int(0).data, + MED_PACKET_NUM_OUT => med2int(0).packet_num, + MED_DATAREADY_OUT => med2int(0).dataready, + MED_READ_IN => '1', + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => serdes_i(0), + SD_RXD_N_IN => serdes_i(1), + SD_TXD_P_OUT => serdes_i(2), + SD_TXD_N_OUT => serdes_i(3), + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med2int(0).stat_op, + CTRL_OP => int2med(0).ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + ); + + + timing_trg_received_i <= TRIGGER_LEFT; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => busrdo_rx, --TDC config + BUS_TX(0) => bustools_tx, + BUS_TX(1) => busrdo_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3_tools + port map( + CLK => clk_100_i, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_DOUT, + FLASH_OUT => FLASH_DIN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + SPI_CLR_OUT => spi_clr, + --LCD + LCD_DATA_IN => lcd_data, + UART_RX_IN => uart_rx, + UART_TX_OUT => uart_tx, + DEBUG_RX_IN => debug_rx, + DEBUG_TX_OUT => debug_tx, + + --Trigger & Monitor + MONITOR_INPUTS(31 downto 0) => INP(31 downto 0), + MONITOR_INPUTS(35 downto 32) => trig_gen_out_i, + TRIG_GEN_INPUTS => INP(31 downto 0), + TRIG_GEN_OUTPUTS => trig_gen_out_i, + LCD_OUT => lcd_out, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Feature I/O +--------------------------------------------------------------------------- + + FPGA5_COMM(10 downto 7) <= trig_gen_out_i; + FPGA5_COMM(6 downto 3) <= (others => 'Z'); + FPGA5_COMM(1) <= 'Z'; + + feature_outputs_i(0) <= uart_rx; + feature_outputs_i(1) <= uart_tx; + feature_outputs_i(2) <= spi_cs(4); + feature_outputs_i(3) <= spi_mosi(4); + feature_outputs_i(4) <= spi_clk(4); + spi_miso(4) <= TEST_LINE(5); + feature_outputs_i(7) <= lcd_out(4); --lcd_cs + feature_outputs_i(8) <= lcd_out(0); --lcd_rst + feature_outputs_i(9) <= lcd_out(3); --lcd_dc + feature_outputs_i(10) <= lcd_out(2); --lcd_mosi + feature_outputs_i(11) <= lcd_out(1); --lcd_sck + --12 is LCD MISO, but not used + feature_outputs_i(14) <= debug_rx; + feature_outputs_i(15) <= debug_tx; + + OUT_CS <= spi_cs(3 downto 0); + OUT_SCK <= spi_clk(3 downto 0); + OUT_SDO <= spi_mosi(3 downto 0); + spi_miso(3 downto 0) <= IN_SDI; + + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); + lcd_data(511 downto 80) <= (others => '0'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med2int(0).stat_op(9); + LED_ORANGE <= not med2int(0).stat_op(10); + LED_RED <= '1'; + LED_YELLOW <= not med2int(0).stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Additional Features +--------------------------------------------------------------------------- + TEST_LINE <= feature_outputs_i; + +------------------------------------------------------------------------------- +-- Your logic +------------------------------------------------------------------------------- +-- THE_Logic : entity work.XXXXX +-- port map ( +-- RESET => reset_i, +-- CLK => clk_100_i, +-- REFERENCE_TIME => timing_trg_received_i, -- Reference time input +-- --Inputs from AddOn and trigger signal to CTS (4 lines) +-- SIGNAL_IN => INP, +-- TRIGGER_OUT => trig_gen_out_i, +-- -- Trigger signals from handler & readout data +-- BUSRDO_RX => readout_rx, +-- BUSRDO_TX => readout_tx(0), +-- -- Slow control bus +-- BUS_RX => busrdo_rx, +-- BUS_TX => busrdo_tx +-- +-- ); +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; + + +end architecture;