From: Tobias Weber Date: Fri, 15 Dec 2017 11:04:28 +0000 (+0100) Subject: compiling version of mupix 8 slow control firmware X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=34e3b912d99b5cb663e797efdd88c84d4213ffc5;p=trb3.git compiling version of mupix 8 slow control firmware --- diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf new file mode 100644 index 0000000..0a223ab --- /dev/null +++ b/base/trb3_periph_mupix8.lpf @@ -0,0 +1,173 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + #SYSCONFIG MCCLK_FREQ = 2.5; + + #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Clock I/O +################################################################# +#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; + + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +#LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; + + + + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +#IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +################################################################# +# Flash ROM and Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +#LOCATE COMP "SUPPL" SITE "C14"; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; + +################################################################# +#MuPix 8 +################################################################# +LOCATE COMP "led_addon_0" SITE "P1"; +LOCATE COMP "led_addon_1" SITE "P2"; +LOCATE COMP "led_addon_2" SITE "T2"; +LOCATE COMP "led_addon_3" SITE "U3"; +DEFINE PORT GROUP "LED_ADDON_GROUP" "led_addon*"; +IOBUF GROUP "LED_ADDON_GROUP" IO_TYPE=LVCMOS25 DRIVE=12; + +LOCATE COMP "hitbus" SITE "J23"; +IOBUF PORT "hitbus" IO_TYPE=LVDS25; + +LOCATE COMP "testpulse" SITE "V6"; +IOBUF PORT "testpulse" IO_TYPE=LVDS25; + +LOCATE COMP "ctrl_ld" SITE "R1"; +LOCATE COMP "ctrl_rb" SITE "K23"; +LOCATE COMP "ctrl_din" SITE "Y19"; +LOCATE COMP "ctrl_clk1" SITE "AB24"; +LOCATE COMP "ctrl_clk2" SITE "AD24"; +DEFINE PORT GROUP "CTRL_GROUP" "ctrl*"; +IOBUF GROUP "CTRL_GROUP" IO_TYPE=LVDS25; + +LOCATE COMP "ctrl_dout" SITE "W8"; +IOBUF PORT "ctrl_dout" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "spi_clk" SITE "K3"; +LOCATE COMP "spi_din" SITE "Y5"; +LOCATE COMP "spi_ld_tmp_dac" SITE "AB1"; +LOCATE COMP "spi_ld_adc" SITE "N5"; +LOCATE COMP "spi_ld_thres" SITE "F2"; +DEFINE PORT GROUP "SPI_GROUP" "spi*"; +IOBUF GROUP "SPI_GROUP" IO_TYPE=LVDS25; + +LOCATE COMP "spi_dout_adc" SITE "K8"; +IOBUF PORT "spi_dout_adc" IO_TYPE=LVDS25 DIFFRESISTOR=100; +LOCATE COMP "spi_dout_dac" SITE "H5"; +IOBUF PORT "spi_dout_dac" IO_TYPE=LVDS25 DIFFRESISTOR=100; +LOCATE COMP "spi_dac4_dout" SITE "G26"; +IOBUF PORT "spi_dac4_dout" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + +########################################################### +##Relax some timing constraints +########################################################### +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/reset" TO CELL "THE_RESET_HANDLER/final_reset[0]" 10 ns; diff --git a/mupix/Mupix8/compile_GSI.pl b/mupix/Mupix8/compile_GSI.pl new file mode 100755 index 0000000..cc991be --- /dev/null +++ b/mupix/Mupix8/compile_GSI.pl @@ -0,0 +1,260 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; +use Term::ANSIColor qw(:constants); +use Cwd; + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $lattice_path = '/opt/lattice/diamond/3.6_x64/'; +my $lattice_bin_path = "$lattice_path/bin/lin64"; +my $synplify_path = '/opt/synplicity/K-2015.09'; +my $lm_license_file_for_synplify = "27000\@lxcad03.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +my $synplify_locale_workaround = "C"; +my $cwd = getcwd(); +################################################################################### + + +my $all = 1; +my $syn = 0; +my $map = 0; +my $timing = 0; +my $bitgen = 0; +my $pargen = 0; +my $help = ""; +my $result = GetOptions ("h|help" => \$help, + "a|all" => \$all, + "s|syn" => \$syn, + "m|map" => \$map, + "t|tim" => \$timing, + "b|bit" => \$bitgen, + "p|par" => \$pargen); + + +if ($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to run the whole process.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-m --map\tRun mapping part of the compile script.\n"; + print "-p --par\tRun place and route.\n"; + print "-t --tim\tCreate timing reports.\n"; + print "-b --bit\tCreate bitfile.\n"; + print "\n"; + exit; +} + +if ($syn != 0 || $map != 0 || $timing != 0 || $bitgen != 0 || $pargen != 0) { + $all=0; +} + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; +open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env ; env'|" or + die "Can't fork: $!"; +while (<$SOURCE>) { + if (/^(.*)=(.*)/) { + $ENV{$1} = ${2} ; + } +} +close $SOURCE; + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'LC_ALL'}=$synplify_locale_workaround; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; +} +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); +print GREEN, "Compiling $TOPNAME project in $cwd/$WORKDIR...\n\n", RESET; + +print GREEN, "Generating constraints file...\n\n", RESET; +#create full lpf file +system("cp ../../base/$TOPNAME"."_mupix8.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); + +chdir "workdir"; +if($syn == 1 || $all == 1){ + print GREEN, "Starting synthesis process...\n\n", RESET; + $c="$synplify_path/bin/synplify_premier_dp -batch ../$TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); + + + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a){ + if(/\@E:/){ + print "\n"; + $c="cat $TOPNAME.srr | egrep --color \"\@E:\""; + system($c); + print "\n\n"; + print RED, "ERROR in the log file $TOPNAME.srr Exiting...\n\n", RESET; + exit 129; + } + } +} + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if($map == 1 || $all == 1){ + print GREEN, "Starting mapping process...\n\n", RESET; + + $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq| edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq| ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + my $tpmap = $TOPNAME . "_map" ; + + $c=qq| map -hier -td_pack -retime EFFORT=6 -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|; + execute($c); + + $fh = new FileHandle("<$TOPNAME"."_mrp.html"); + @a = <$fh>; + $fh -> close; + my $i=1; + my $print=0; + foreach (@a) { + if (/WARNING/|$print) { + if ((grep /WARNING - map: There are semantic errors in the preference file/, $_) & ($i == 1)) { + last; + } + elsif (grep /WARNING - map: There are semantic errors in the preference file/, $_) { + print RED, "There are errors in the constraints file. Better have a look...\n\n", RESET; + sleep(5); # ERROR -> sleep is effective before the print + last; + } + elsif ($i == 1) { + print RED,"\n\n", RESET; + print RED,"#################################################\n", RESET; + print RED,"CONSTRAINTS ERRORS\n", RESET; + print RED,"#################################################\n\n", RESET; + } + $print=1; + if (grep /WARNING.*UGROUP/, $_) { + print RED, $_, RESET; + } elsif (grep /FC|hitBuf|ff_en/, $_) { + print YELLOW, $_, RESET; + } else { + print $_; + } + $i++; + } + } +} + +if($pargen == 1 || $all == 1){ + print GREEN, "Starting placement and route process...\n\n", RESET; + system("rm $TOPNAME.ncd"); + + # dont forget to create a nodelist.txt for multipar / mpartrce + my $tpmap = $TOPNAME . "_map" ; + $c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "$tpmap.ncd" "$TOPNAME.ncd"|; + execute($c); + #my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; + system($c); +} + +if($timing == 1 || $all == 1){ + print GREEN, "Running timing analysis \n\n", RESET; + + # TWR Timing Report + $c=qq| trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq| trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + # IOR IO Timing Report + $c=qq| iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq| ltxt2ptxt $TOPNAME.ncd|; + execute($c); +} + +if($bitgen == 1 || $all == 1){ + print GREEN, "Creating Bit File \n\n", RESET; + $c=qq| bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + execute($c); +} + +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; +execute($c); + +chdir ".."; +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 6343fd6..b60abbb 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -12,7 +12,7 @@ use work.trb3_components.all; use work.StdTypes.all; -entity MupixBoard is +entity MupixBoard8 is port( --Clock signal clk : in std_logic; @@ -35,28 +35,8 @@ entity MupixBoard is spi_ld_tmp_dac : out std_logic; --load temperature dac spi_cs_adc : out std_logic; --load adc spi_ld_thres : out std_logic; --load threshold and injection dac - --slow data signals hitbus : in std_logic; --hitbus signal - hit : in std_logic; --hit signal (replacement for priout?) - ldcol : out std_logic; --load column - rdcol : out std_logic; --read column - pull_down : out std_logic; --pull down - ldpix : out std_logic; --load pixel - --fast data signals - clkref : out std_logic; --reference clock - clkext : out std_logic; --external clock (difference to first one?) - syncres : out std_logic; --synchronous reset of mupix 8 counters and time stamps - trigger : in std_logic; --external trigger - --data - data1_P : in std_logic; --data 1 - data1_N : in std_logic; - data2_P : in std_logic; --data 2 - data2_N : in std_logic; - data3_P : in std_logic; --data 3 - data3_N : in std_logic; - data4_P : in std_logic; --this channel is muxed version of other three - data4_N : in std_logic; - + --resets timestampreset_in : in std_logic; --time stamp reset eventcounterreset_in : in std_logic; --event number reset @@ -93,10 +73,10 @@ entity MupixBoard is REGIO_NO_MORE_DATA_OUT : out std_logic; REGIO_UNKNOWN_ADDR_OUT : out std_logic ); -end MupixBoard; +end MupixBoard8; -architecture Behavioral of MupixBoard is +architecture Behavioral of MupixBoard8 is component MupixBoardInterface port( @@ -133,6 +113,13 @@ architecture Behavioral of MupixBoard is signal trigger_sync_fast : std_logic; --sampled with 200 MHz clock signal hit_sync : std_logic; + signal testpulse_i : std_logic; + signal spi_clk_i : std_logic; + signal spi_din_i : std_logic; + signal spi_ld_tmp_dac_i : std_logic; + signal spi_cs_adc_i : std_logic; + signal spi_ld_thres_i : std_logic; + component HitbusHistogram generic( HistogramRange : integer; @@ -281,8 +268,8 @@ begin -- Behavioral spi_dout_dac => spi_dout_dac, dac4_dout => dac4_dout, hitbus => hitbus, - hit => hit, - trigger => trigger, + hit => '0', + trigger => '0', ctrl_dout_sync => ctrl_dout_sync, spi_dout_adc_sync => spi_dout_adc_sync, spi_dout_dac_sync => spi_dout_dac_sync, @@ -333,10 +320,11 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) ); - ctrl_din <= mupixslctrl_i.sin; - ctrl_clk1 <= mupixslctrl_i.clk1; - ctrl_clk2 <= mupixslctrl_i.clk2; - ctrl_ld <= mupixslctrl_i.load; + --need to invert signals due to addon board layout + ctrl_din <= not mupixslctrl_i.sin; + ctrl_clk1 <= not mupixslctrl_i.clk1; + ctrl_clk2 <= not mupixslctrl_i.clk2; + ctrl_ld <= not mupixslctrl_i.load; boardcontrol_1 : component MupixBoardDAC @@ -346,12 +334,12 @@ begin -- Behavioral spi_dout_dac => spi_dout_dac_sync, dac4_dout => dac4_dout_sync, spi_dout_adc => spi_dout_adc_sync, - spi_clk => spi_clk, - spi_din => spi_din, - spi_ld_tmp_dac => spi_ld_tmp_dac, - spi_ld_thres => spi_ld_thres, - spi_cs_adc => spi_cs_adc, - injection_pulse => testpulse, + spi_clk => spi_clk_i, + spi_din => spi_din_i, + spi_ld_tmp_dac => spi_ld_tmp_dac_i, + spi_ld_thres => spi_ld_thres_i, + spi_cs_adc => spi_cs_adc_i, + injection_pulse => testpulse_i, SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32), @@ -361,5 +349,13 @@ begin -- Behavioral SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) ); + + --need to invert signals due to addon board layout + spi_clk <= not spi_clk_i; + spi_din <= not spi_din_i; + spi_ld_tmp_dac <= not spi_ld_tmp_dac_i; + spi_ld_thres <= not spi_ld_thres_i; + spi_cs_adc <= not spi_cs_adc_i; + testpulse <= not testpulse_i; end Behavioral; diff --git a/mupix/Mupix8/sources/MupixBoardInterface.vhd b/mupix/Mupix8/sources/MupixBoardInterface.vhd index 9d2c70f..7b3f793 100644 --- a/mupix/Mupix8/sources/MupixBoardInterface.vhd +++ b/mupix/Mupix8/sources/MupixBoardInterface.vhd @@ -37,6 +37,11 @@ end entity MupixBoardInterface; architecture rtl of MupixBoardInterface is + signal spi_dout_adc_i : std_logic; + signal spi_dout_dac_i : std_logic; + signal dac4_dout_i : std_logic; + signal hitbus_i : std_logic; + component InputSynchronizer generic(depth : integer); port( @@ -55,19 +60,19 @@ begin sync_spi_dout_adc : component InputSynchronizer generic map(depth => 2) - port map(clk_in, reset, spi_dout_adc, spi_dout_adc_sync); + port map(clk_in, reset, spi_dout_adc, spi_dout_adc_i); sync_spi_dout_dac : component InputSynchronizer generic map(depth => 2) - port map(clk_in, reset, spi_dout_dac, spi_dout_dac_sync); + port map(clk_in, reset, spi_dout_dac, spi_dout_dac_i); sync_dac4_dout : component InputSynchronizer generic map(depth => 2) - port map(clk_in, reset, dac4_dout, dac4_dout_sync); + port map(clk_in, reset, dac4_dout, dac4_dout_i); sync_hitbus : component InputSynchronizer generic map(depth => 2) - port map(clk_in, reset, hitbus, hitbus_sync); + port map(clk_in, reset, hitbus, hitbus_i); sync_trigger : component InputSynchronizer generic map(depth => 2) @@ -84,5 +89,12 @@ begin sync_fast_trigger : component InputSynchronizer generic map(depth => 2) port map(fast_clk_in, reset, trigger, trigger_sync_fast); + + --need to invert some input signals due to addon board layout + spi_dout_adc_sync <= not spi_dout_adc_i; + spi_dout_dac_sync <= not spi_dout_dac_i; + dac4_dout_sync <= not dac4_dout_i; + hitbus_sync <= not hitbus_i; + end architecture rtl; diff --git a/mupix/Mupix8/sources/ResetHandler.vhd b/mupix/Mupix8/sources/ResetHandler.vhd new file mode 100644 index 0000000..9a8bcc5 --- /dev/null +++ b/mupix/Mupix8/sources/ResetHandler.vhd @@ -0,0 +1,110 @@ +------------------------------------------------------------ +--Module to Broadcast a Reset Signal to several frontends +--entities on an peripherial FPGA. +--T. Weber, University Mainz +------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +--use work.trb3_components.all; +--use work.version.all; + +entity resethandler is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TimestampReset_OUT : out std_logic; + EventCounterReset_OUT : out std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); +end entity resethandler; + +architecture behavioral of resethandler is + + signal timestampreset_i : std_logic := '0'; + signal eventcounterreset_i : std_logic := '0'; + signal timestampreset_edge : std_logic_vector(1 downto 0) := (others => '0'); + signal eventcounterreset_edge : std_logic_vector(1 downto 0) := (others => '0'); + +begin -- architecture behavioral + + + timestamp_edge_detect : process (CLK_IN) is + begin -- process timestamp_edge_detect + if rising_edge(CLK_IN) then + timestampreset_edge <= timestampreset_edge(0) & timestampreset_i; + if timestampreset_edge = "01" then + TimestampReset_OUT <= '1'; + else + TimestampReset_OUT <= '0'; + end if; + end if; + end process timestamp_edge_detect; + + eventcounter_edge_detect : process (CLK_IN) is + begin -- process eventcounter_edge_detect + if rising_edge(CLK_IN) then + eventcounterreset_edge <= eventcounterreset_edge(0) & eventcounterreset_i; + if eventcounterreset_edge = "01" then + EventCounterReset_OUT <= '1'; + else + EventCounterReset_OUT <= '0'; + end if; + end if; + end process eventcounter_edge_detect; + + ------------------------------------------------------------ + --TRB SLV-BUS Hanlder + ------------------------------------------------------------ + --0x0001: reset timestamps + --0x0002: reset eventcounter + slv_bus_handler : process (CLK_IN) is + begin -- process slv_bus_handler + if rising_edge(CLK_IN) then + slv_data_out <= (others => '0'); + slv_ack_out <= '0'; + slv_no_more_data_out <= '0'; + slv_unknown_addr_out <= '0'; + + if SLV_WRITE_IN = '1' then + case SLV_ADDR_IN is + when x"0001" => + timestampreset_i <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when x"0002" => + eventcounterreset_i <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when others => + slv_unknown_addr_out <= '1'; + end case; + end if; + + if SLV_READ_IN = '1' then + case SLV_ADDR_IN is + when x"0001" => + slv_data_out(0) <= timestampreset_i; + slv_ack_out <= '1'; + when x"0002" => + slv_data_out(0) <= eventcounterreset_i; + slv_ack_out <= '1'; + when others => + slv_unknown_addr_out <= '1'; + end case; + end if; + end if; + end process slv_bus_handler; + + +end architecture behavioral; diff --git a/mupix/Mupix8/trb3_periph.p2t b/mupix/Mupix8/trb3_periph.p2t new file mode 100644 index 0000000..995161f --- /dev/null +++ b/mupix/Mupix8/trb3_periph.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 11 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/mupix/Mupix8/trb3_periph.p3t b/mupix/Mupix8/trb3_periph.p3t new file mode 100644 index 0000000..bf0053f --- /dev/null +++ b/mupix/Mupix8/trb3_periph.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "trb3_periph.log" +-o "trb3_periph.csv" +-pr "trb3_periph.prf" diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj new file mode 100644 index 0000000..971e3c1 --- /dev/null +++ b/mupix/Mupix8/trb3_periph.prj @@ -0,0 +1,165 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../../base/trb3_components.vhd" + +#trbnet components +add_file -vhdl -lib work "../../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../../trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "../../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +#ip cores for mupix design +add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd" + +#MuPix Files +add_file -vhdl -lib "work" "trb3_periph.vhd" + +add_file -vhdl -lib "work" "sources/StdTypes.vhd" +add_file -vhdl -lib "work" "sources/MupixBoard.vhd" +add_file -vhdl -lib "work" "sources/InputSynchronizer.vhd" +add_file -vhdl -lib "work" "sources/MupixBoardInterface.vhd" +add_file -vhdl -lib "work" "sources/BlockMemory.vhd" +add_file -vhdl -lib "work" "sources/Histogram.vhd" +add_file -vhdl -lib "work" "sources/SignalDelay.vhd" +add_file -vhdl -lib "work" "sources/HitbusHistogram.vhd" +add_file -vhdl -lib "work" "sources/ADS1018SPI.vhd" +add_file -vhdl -lib "work" "sources/LTC1658SPI.vhd" +add_file -vhdl -lib "work" "sources/TestpulseGenerator.vhd" +add_file -vhdl -lib "work" "sources/MupixBoardDAC.vhd" +add_file -vhdl -lib "work" "sources/CRC.vhd" +add_file -vhdl -lib "work" "sources/PixelControl.vhd" +add_file -vhdl -lib "work" "sources/FIFO.vhd" +add_file -vhdl -lib "work" "sources/ResetHandler.vhd" diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd index ffe53db..b01a1e8 100644 --- a/mupix/Mupix8/trb3_periph.vhd +++ b/mupix/Mupix8/trb3_periph.vhd @@ -21,9 +21,9 @@ entity trb3_periph is port( --Clocks CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + --CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left! + --CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out @@ -44,6 +44,7 @@ entity trb3_periph is --------------------------------------------------------------------------- led_line : out std_logic_vector(3 downto 0); --leds on TRB addon board spare_line : in std_logic_vector(5 downto 0); --spare lines + led_addon : out std_logic_vector(3 downto 0); --slow control signals testpulse : out std_logic; --generate injection pulse ctrl_din : out std_logic; --serial data to mupix @@ -54,31 +55,18 @@ entity trb3_periph is ctrl_rb : out std_logic; --slow control readback?? spi_dout_adc : in std_logic; --adc serial data from board spi_dout_dac : in std_logic; --dac serial data from board - spi_ld : out std_logic; --serial data load + spi_ld_thres : out std_logic; --serial data load spi_clk : out std_logic; --serial clock spi_din : out std_logic; --serial data out spi_ld_tmp_dac : out std_logic; --load temperature dac ?? spi_ld_adc : out std_logic; --load adc ?? - dac4_dout : in std_logic; --serial data in from dac 4?? - --slow data signals - hitbus : in std_logic; --hitbus signal - hit : in std_logic; --hit signal (replacement for priout?) - ldcol : out std_logic; --load column - rdcol : out std_logic; --read column - pull_down : out std_logic; --pull down - ldpix : out std_logic; --load pixel - --fast data signals - clkref : out std_logic; --reference clock - clkext : out std_logic; --external clock (difference to first one?) - syncres : out std_logic; --sync something - trigger : in std_logic; --external trigger + spi_dac4_dout : in std_logic; --serial data in from dac 4?? + hitbus : in std_logic; --fast data comes in via serdes addon (see above) --------------------------------------------------------------------------- -- END SensorBoard MuPix --------------------------------------------------------------------------- - not_connected : out std_logic_vector(25 downto 0); - --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -92,7 +80,7 @@ entity trb3_periph is LED_ORANGE : out std_logic; LED_RED : out std_logic; LED_YELLOW : out std_logic; - SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --SUPPL : in std_logic; --terminated diff pair, PCLK, Pads --Test Connectors TEST_LINE : out std_logic_vector(15 downto 0) ); @@ -126,6 +114,86 @@ end entity; architecture trb3_periph_arch of trb3_periph is + + + component MupixBoard8 is + port( + --Clock signal + clk : in std_logic; + fast_clk : in std_logic; + reset : in std_logic; + + --slow control signals + testpulse : out std_logic; --generate injection pulse + ctrl_din : out std_logic; --serial data to mupix + ctrl_clk1 : out std_logic; --slow control clk1 + ctrl_clk2 : out std_logic; --slow control clk2 + ctrl_ld : out std_logic; --slow control load latched data + ctrl_dout : in std_logic; --serial data from mupix + ctrl_rb : out std_logic; --slow control readback?? + spi_dout_adc : in std_logic; --adc serial data from board + spi_dout_dac : in std_logic; --dac serial data from board + dac4_dout : in std_logic; --serial data in from threshold dac + spi_clk : out std_logic; --serial clock + spi_din : out std_logic; --serial data out + spi_ld_tmp_dac : out std_logic; --load temperature dac + spi_cs_adc : out std_logic; --load adc + spi_ld_thres : out std_logic; --load threshold and injection dac + hitbus : in std_logic; --hitbus signal + + --resets + timestampreset_in : in std_logic; --time stamp reset + eventcounterreset_in : in std_logic; --event number reset + + --TRB trigger connections + TIMING_TRG_IN : in std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + + --TRB data connections + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + + --TRB slow control connections + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); + REGIO_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic); + end component; + + component resethandler is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TimestampReset_OUT : out std_logic; + EventCounterReset_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component resethandler; + --Constants constant REGIO_NUM_STAT_REGS : integer := 5; constant REGIO_NUM_CTRL_REGS : integer := 3; @@ -277,6 +345,7 @@ begin --tie not connected outputs to 0 --not_connected(25 downto 18) <= (others => '0'); --not_connected(16 downto 0) <= (others => '0'); + led_addon <= (others => '0'); --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- @@ -482,8 +551,8 @@ begin THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", - 1 => x"d100", + PORT_ADDRESSES => (0 => x"d000", --spi master + 1 => x"d100", --spi memory 2 => x"8000", --Mupix 0 3 => x"c000", --Reset others => x"0000"), @@ -635,7 +704,7 @@ begin ----------------------------------------------------------------------------- -- MuPix Frontend-Board ----------------------------------------------------------------------------- - MuPix3_Board_0 : MuPix3_Board + MupixBoard8_0 : MupixBoard8 port map ( clk => clk_100_i, fast_clk => clk_200_i, @@ -643,6 +712,24 @@ begin timestampreset_in => reset_timestamps_i, eventcounterreset_in => reset_eventcounters_i, + + --slow control signals + testpulse => testpulse, + ctrl_din => ctrl_din, + ctrl_clk1 => ctrl_clk1, + ctrl_clk2 => ctrl_clk2, + ctrl_ld => ctrl_ld, + ctrl_dout => ctrl_dout, + ctrl_rb => ctrl_rb, + spi_dout_adc => spi_dout_adc, + spi_dout_dac => spi_dout_dac, + dac4_dout => spi_dac4_dout, + spi_clk => spi_clk, + spi_din => spi_din, + spi_ld_tmp_dac => spi_ld_tmp_dac, + spi_cs_adc => spi_ld_adc, + spi_ld_thres => spi_ld_thres, + hitbus => hitbus, TIMING_TRG_IN => TRIGGER_RIGHT, LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, diff --git a/mupix/Mupix8/trb3_periph_constraints.lpf b/mupix/Mupix8/trb3_periph_constraints.lpf new file mode 100644 index 0000000..db33e6d --- /dev/null +++ b/mupix/Mupix8/trb3_periph_constraints.lpf @@ -0,0 +1,46 @@ +# BLOCK RESETPATHS ; +# BLOCK ASYNCPATHS ; +# BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + + #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + + + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + + +################################################################# +# Relax some of the timing constraints +################################################################# +#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +#MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns; + + +################################################################# +# Constraints for MuPix inputs +################################################################# + +# look at .par and .twr.setup file for clocks +# and .mrp or errors +