From: Jan Michel Date: Fri, 12 May 2023 13:49:35 +0000 (+0200) Subject: update ADA design to contain fee test signals X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=34f3f2a2f52875ba02e64e58ad448c7cd83cc2a0;p=trb3.git update ADA design to contain fee test signals --- diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd index 0ceb7e6..eb79f65 100644 --- a/ADA_Addon/config.vhd +++ b/ADA_Addon/config.vhd @@ -59,6 +59,8 @@ package config is constant INIT_ADDRESS : std_logic_vector := x"F305"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"47"; --47: TOF + constant USE_TEST_SIGNALS : integer := c_YES; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/ADA_Addon/config_compile_frankfurt.pl b/ADA_Addon/config_compile_frankfurt.pl index 2b17a74..df3c598 100644 --- a/ADA_Addon/config_compile_frankfurt.pl +++ b/ADA_Addon/config_compile_frankfurt.pl @@ -2,8 +2,8 @@ TOPNAME => "trb3_periph_ADA", project_path => "ADA_Addon", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', -synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', # synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/ADA_Addon/par.p2t b/ADA_Addon/par.p2t index 246acd7..72492ea 100644 --- a/ADA_Addon/par.p2t +++ b/ADA_Addon/par.p2t @@ -14,7 +14,7 @@ -l 5 -i 6 -n 1 --t 5 +-t 9 -s 1 -c 0 -e 0 diff --git a/ADA_Addon/trb3_periph_ADA.prj b/ADA_Addon/trb3_periph_ADA.prj index 6cfeea3..4d88f56 100644 --- a/ADA_Addon/trb3_periph_ADA.prj +++ b/ADA_Addon/trb3_periph_ADA.prj @@ -183,15 +183,17 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_coin.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_delay.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_edgedetect.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_enable.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_inverter.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_logic.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_merge.vhd" -add_file -vhdl -lib work "../../triggerlogic/trigger_stretch.vhd" -add_file -vhdl -lib work "../../triggerlogic/cores/delay_shift_reg.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_coin.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_delay.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_edgedetect.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_enable.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_inverter.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_logic.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_merge.vhd" +#add_file -vhdl -lib work "../../triggerlogic/trigger_stretch.vhd" +#add_file -vhdl -lib work "../../triggerlogic/cores/delay_shift_reg.vhd" + +add_file -vhdl -lib work "../../trb3sc/code/fee_signals.vhd" if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} { diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf index c58374e..c2a2791 100644 --- a/base/trb3_periph_ada.lpf +++ b/base/trb3_periph_ada.lpf @@ -288,6 +288,7 @@ LOCATE COMP "DAC_OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94 # LOCATE COMP "DQUL_19" SITE "K6"; #"DQUL_19" DQSUL1_C #87 # LOCATE COMP "DQUL_20" SITE "H5"; #"DQUL_20" DQUL1_6 #89 # LOCATE COMP "DQUL_21" SITE "J5"; #"DQUL_21" DQUL1_7 #91 +# LOCATE COMP "DQUL_20" SITE "H5"; #"DQUL_20" DQUL1_6 #89 # LOCATE COMP "DQUL_22" SITE "K8"; #"DQUL_22" DQUL1_8 #93 # LOCATE COMP "DQUL_23" SITE "J7"; #"DQUL_23" DQUL1_9 #95 @@ -368,6 +369,26 @@ IOBUF GROUP "OUT_group" IO_TYPE=LVDS25; # Additional Lines to AddOn ################################################################# +# LOCATE COMP "DQUL_34" SITE "L5"; #"DQUL_34" DQUL2_8 #70 +# LOCATE COMP "DQUL_14" SITE "F2"; #"DQUL_14" DQUL1_2 #77 +# LOCATE COMP "DQUL_22" SITE "K8"; #"DQUL_22" DQUL1_8 #93 +# LOCATE COMP "DQUL_20" SITE "H5"; #"DQUL_20" DQUL1_6 #89 +LOCATE COMP "ADDON_TEST_1" SITE "L5"; #"DQUL_34" DQUL2_8 #70 +LOCATE COMP "ADDON_TEST_2" SITE "F2"; #"DQUL_14" DQUL1_2 #77 +LOCATE COMP "ADDON_TEST_3" SITE "K8"; #"DQUL_22" DQUL1_8 #93 +LOCATE COMP "ADDON_TEST_4" SITE "H5"; #"DQUL_20" DQUL1_6 #89 +DEFINE PORT GROUP "ADDON_TEST_group" "ADDON_TEST*"; +IOBUF GROUP "ADDON_TEST_group" IO_TYPE=LVDS25; + +# LOCATE COMP "DQUL_44" SITE "L2"; #"DQUL_44" DQUL3_6 #65 +# LOCATE COMP "DQUL_32" SITE "E1"; #"DQUL_32" DQUL2_6 #66 +LOCATE COMP "ADDON_TEMP_1" SITE "L2"; #"DQUL_44" DQUL3_6 #65 +LOCATE COMP "ADDON_TEMP_2" SITE "E1"; #"DQUL_32" DQUL2_6 #66 +DEFINE PORT GROUP "ADDON_TEMP_group" "ADDON_TEMP*"; +IOBUF GROUP "ADDON_TEMP_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + + #Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 #all lines are input only #line 4/5 go to PLL input