From: Cahit <c.ugur@gsi.de>
Date: Mon, 21 Mar 2016 13:47:26 +0000 (+0100)
Subject: corrected merge
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=35450ddd78b8ec3a230e7c9a13dd798d89a20a10;p=dirich.git

corrected merge
---

35450ddd78b8ec3a230e7c9a13dd798d89a20a10
diff --cc dirich/dirich.vhd
index ddad189,1573031..94ff711
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@@ -262,43 -260,50 +265,50 @@@ THE_ENDPOINT : entity work.trb_net16_en
        RESET       => reset_i,
        
        --Flash & Reload
--      FLASH_CS    => FLASH_CS,
-       FLASH_CLK   => FLASH_CLK,
 -      FLASH_CLK   => flash_clk_i,
--      FLASH_IN    => FLASH_OUT,
--      FLASH_OUT   => FLASH_IN,
--      PROGRAMN    => PROGRAMN,
--      REBOOT_IN   => common_ctrl_reg(15),
++      FLASH_CS          => FLASH_CS,
++      FLASH_CLK         => flash_clk_i,
++      FLASH_IN          => FLASH_OUT,
++      FLASH_OUT         => FLASH_IN,
++      PROGRAMN          => PROGRAMN,
++      REBOOT_IN         => common_ctrl_reg(15),
        --SPI
--      SPI_CS_OUT  => open,  
--      SPI_MOSI_OUT=> open,
--      SPI_MISO_IN => open,
--      SPI_CLK_OUT => open,
++      SPI_CS_OUT        => open,
++      SPI_MOSI_OUT      => open,
++      SPI_MISO_IN       => open,
++      SPI_CLK_OUT       => open,
        --Header
--      HEADER_IO   => hdr_io,
- --      LED_DISABLE => led_off,
++      HEADER_IO         => hdr_io,
+       ADDITIONAL_REG(0) => led_off,
        --LCD
--      LCD_DATA_IN => lcd_data,
++      LCD_DATA_IN       => lcd_data,
        --ADC
--      ADC_CS      => ADC_CS,
--      ADC_MOSI    => ADC_DIN,
--      ADC_MISO    => ADC_DOUT,
--      ADC_CLK     => ADC_SCLK,
++      ADC_CS            => ADC_CS,
++      ADC_MOSI          => ADC_DIN,
++      ADC_MISO          => ADC_DOUT,
++      ADC_CLK           => ADC_SCLK,
        --Trigger & Monitor 
--      MONITOR_INPUTS   => INPUT,
--      TRIG_GEN_INPUTS  => INPUT,
--      TRIG_GEN_OUTPUTS => SIG(4 downto 3),
++      MONITOR_INPUTS    => INPUT,
++      TRIG_GEN_INPUTS   => INPUT,
++      TRIG_GEN_OUTPUTS  => SIG(4 downto 3),
        --SED
--      SED_ERROR_OUT => sed_error_i,
++      SED_ERROR_OUT     => sed_error_i,
        --Slowcontrol
--      BUS_RX     => bustools_rx,
--      BUS_TX     => bustools_tx,
++      BUS_RX            => bustools_rx,
++      BUS_TX            => bustools_tx,
        --Control master for default settings
--      BUS_MASTER_IN  => bus_master_in,
--      BUS_MASTER_OUT => bus_master_out,
--      BUS_MASTER_ACTIVE => bus_master_active,      
--      DEBUG_OUT  => debug_tools
++      BUS_MASTER_IN     => bus_master_in,
++      BUS_MASTER_OUT    => bus_master_out,
++      BUS_MASTER_ACTIVE => bus_master_active,
++      DEBUG_OUT         => debug_tools
        );
  
+       
+ THE_FLASH_CLOCK : usrmclk
+   port map(
+     USRMCLKI  => flash_clk_i,
+     USRMCLKTS => '0'
+     );
+       
  ---------------------------------------------------------------------------
  -- PWM / Thresh
  ---------------------------------------------------------------------------  
diff --cc pinout/basic_constraints.lpf
index fdbb754,a725c59..a3054a9
--- a/pinout/basic_constraints.lpf
+++ b/pinout/basic_constraints.lpf
@@@ -3,21 -3,8 +3,11 @@@ BLOCK RESETPATHS 
  BLOCK ASYNCPATHS ;
  BLOCK RD_DURING_WR_PATHS ;
  
 +#################################################################
 +# Basic Settings
 +#################################################################
  
- SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
- BANK 0 VCCIO 2.5 V;
- BANK 1 VCCIO 2.5 V;
- BANK 2 VCCIO 2.5 V;
- BANK 3 VCCIO 2.5 V;
- BANK 6 VCCIO 2.5 V;
- BANK 7 VCCIO 2.5 V;
- BANK 8 VCCIO 3.3 V;
- 
- 
- FREQUENCY PORT CLOCK_IN        240 MHz;
+ FREQUENCY PORT CLOCK_IN        200 MHz;
  FREQUENCY PORT CLOCK_CAL       33 MHz;