From: Jan Michel Date: Sun, 6 Sep 2015 23:31:58 +0000 (+0200) Subject: new hades full handler, timing constraints all fulfilled X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=35e4e4e3e64aa93cc6dd6b3a96d2380331b5bfcb;p=adcm.git new hades full handler, timing constraints all fulfilled --- diff --git a/Makefile b/Makefile index 92959c8..3827320 100644 --- a/Makefile +++ b/Makefile @@ -91,7 +91,7 @@ workdir/$(TARGET).ngd: workdir/$(TARGET).edf edfupdate -t $(TARGET).tcy -w $(TARGET).ngo -m $(TARGET).ngo \ $(TARGET).ngx cd workdir && \ - ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -dt $(TARGET).ngo \ + ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -p $(lattice_path)/ispfpga/or5s00/data -dt $(TARGET).ngo \ $(TARGET).ngd # VHDL / Verilog Compiler @@ -109,10 +109,10 @@ workdir/$(TARGET).edf: @echo "--------------- VHDL Compiler ----------------------------------------" @echo "----------------------------------------------------------------------" - #$(SYNPLIFY)/bin/synplify_premier_dp -batch $TOPNAME.prj || \ - # (grep "@E" workdir/$(TARGET).srr && exit 2) - synpwrap -prj $(TARGET).prj || \ + $(SYNPLIFY)/bin/synplify_premier_dp -batch $(TARGET).prj || \ (grep "@E" workdir/$(TARGET).srr && exit 2) + #synpwrap -prj $(TARGET).prj || \ + #(grep "@E" workdir/$(TARGET).srr && exit 2) # ------------------------------------------------------------------------------------ @@ -159,14 +159,17 @@ report: @echo "----------------------------------------------------------------------" @echo "-------------- Timing Report -----------------------------------------" @echo "----------------------------------------------------------------------" + # IOR IO Timing Report cd workdir && \ iotiming -s $(TARGET).ncd $(TARGET).prf + + # TWR Timing Report (setup) cd workdir && \ trce -c -v 15 -o $(TARGET).twr.setup $(TARGET).ncd $(TARGET).prf + + # TWR Timing Report (hold) cd workdir && \ trce -hld -c -v 5 -o $(TARGET).twr.hold $(TARGET).ncd $(TARGET).prf - cd workdir && \ - ltxt2ptxt $(TARGET).ncd # Error Check .PHONY: error @@ -186,20 +189,5 @@ error: @grep "Error:" ./workdir/$(TARGET).twr.hold || exit 0 @echo -e "\nCircuit Loops:" - @grep "potential circuit loops" ./workdir/* || exit 0 - -# ------------------------------------------------------------------------------------ -# Extract dependencies from project file -#.PHONY: $(TARGET).dep -#$(TARGET).dep: -# @echo "" -# @echo "----------------------------------------------------------------------" -# @echo "--------------- Extract Dependencies from Project File ---------------" -# @echo "----------------------------------------------------------------------" -# grep 'add_file' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ -# | xargs echo "workdir/$(TARGET).edf:" > $(TARGET).dep -# grep 'map_dep' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ -# | xargs echo "workdir/$(TARGET)_map.ncd:" >> $(TARGET).dep -# -#-include $(TARGET).dep + @grep "potential circuit loops" ./workdir/* 2>/dev/null || exit 0 diff --git a/adcmv3.lpf b/adcmv3.lpf index f0f5fea..3798a01 100755 --- a/adcmv3.lpf +++ b/adcmv3.lpf @@ -151,8 +151,8 @@ LOCATE COMP "ENA_LVDS_0" SITE "AG15" ; # IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ; # Backplane sense wires: sector number # small assembly bug: switch is 180degree rotated, so number are mirrored -LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15" -IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +#LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15" +#IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13" IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12" @@ -416,8 +416,8 @@ LOCATE COMP "ENB_LVDS_0" SITE "D12" ; # LOCATE COMP "FPGA_BP_12" SITE "C14" ; # IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ; # Backplane sense wires: backplane number -LOCATE COMP "BP_MODULE_3" SITE "A14" ; -IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +#LOCATE COMP "BP_MODULE_3" SITE "A14" ; +#IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_MODULE_2" SITE "F13" ; IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_MODULE_1" SITE "E12" ; diff --git a/adcmv3.prj b/adcmv3.prj index 393b5c1..e1e9928 100755 --- a/adcmv3.prj +++ b/adcmv3.prj @@ -8,6 +8,7 @@ add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "design/adcmv3_components.vhd" +#add_file -constraint "adcmv3.sdc" # ADCMv3 design files add_file -vhdl -lib work "design/adcmv3.vhd" diff --git a/adcmv3_constraints.lpf b/adcmv3_constraints.lpf index 95e543d..47f1fba 100755 --- a/adcmv3_constraints.lpf +++ b/adcmv3_constraints.lpf @@ -1,18 +1,29 @@ +# Clock +# Extern CLK100M +# -> DLL_100M -> sysclk_c +# -> PLL_40M -> clk_apv -> APVxy_CLK (0A,0B,1A.1B) +# -> clk_adc -> ADCx_CLK (0,1) +# Extern ADC0_LCLK (bitclock ADC0) +# Extern ADC1_LCLK (bitclock ADC1) + +BLOCK PATH FROM CLKNET "CLK100M*" TO CLKNET "sysclk*"; +BLOCK PATH FROM CLKNET "sysclk*" TO CLKNET "clk_apv*"; +BLOCK PATH FROM CLKNET "clk_apv*" TO CLKNET "sysclk*"; + ###################################################################### # PLL 100MHz -> 40MHz ###################################################################### FREQUENCY NET "CLK100M_c" 100.000000 MHz ; FREQUENCY NET "sysclk_c" 100.000000 MHz ; -LOCATE COMP "THE_40M_PLL/PLLDINST_0" SITE "PLL_R103C3" ; +LOCATE COMP "THE_40M_PLL/PLLDInst_0" SITE "PLL_R103C3" ; FREQUENCY NET "clk_adc" 40.000000 MHz ; FREQUENCY NET "clk_apv_c" 40.000000 MHz ; ###################################################################### # DLL 100MHz -> 100MHz ###################################################################### -LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ; -FREQUENCY NET "sysclk" 100.000000 MHz ; +LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ; #?????????? ###################################################################### # CTS 40MHz clock @@ -22,17 +33,15 @@ FREQUENCY NET "cts_clk40m" 40.000000 MHz ; ###################################################################### # TRBnet SerDes clock constraints ###################################################################### -FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txfullclk" 200.000000 MHz ; -FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txhalfclk" 100.000000 MHz ; +# FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2.THE_SERDES/ff_txfullclk" 200.000000 MHz ; #????????? +# FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2.THE_SERDES/ff_txhalfclk" 100.000000 MHz ; #????????? -REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 ; -LOCATE UGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/MEDIA_INTERFACE_group" REGION "MEDIA_INTERFACE_REGION" ; +# REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 ; +# LOCATE UGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/MEDIA_INTERFACE_group" REGION "MEDIA_INTERFACE_REGION" #?????? ###################################################################### # PLL ADC0: 40MHz ###################################################################### -LOCATE COMP "THE_ADC0_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R67C1" ; - PERIOD PORT "ADC0_LCLK" 4.1666 ns ; USE PRIMARY PURE NET "ADC0_LCLK_c" ; USE EDGE NET "ADC0_LCLK_c" ; @@ -41,10 +50,6 @@ USE EDGE NET "ADC0_LCLK_c" ; DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*" "ADC0_ADCLK*" ; INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ; -# Reconstructed clock -FREQUENCY NET "THE_ADC0_HANDLER/clk40m" 40.000000 MHz ; -USE PRIMARY DCS NET "THE_ADC0_HANDLER/clk40m" ; - # 240MHz ADC0 regions (namely ser2par for DDR data stream) REGION "ADC0_REGION" "R59C2" 46 4 ; LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ; @@ -55,8 +60,6 @@ LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_R ###################################################################### # PLL ADC1: 40MHz ###################################################################### -LOCATE COMP "THE_ADC1_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R49C1" ; - PERIOD PORT "ADC1_LCLK" 4.1666 ns ; USE PRIMARY PURE NET "ADC1_LCLK_c" ; USE EDGE NET "ADC1_LCLK_c" ; @@ -65,10 +68,6 @@ USE EDGE NET "ADC1_LCLK_c" ; DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*" "ADC1_ADCLK*" ; INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ; -# Reconstructed clock -FREQUENCY NET "THE_ADC1_HANDLER/clk40m" 40.000000 MHz ; -USE PRIMARY DCS NET "THE_ADC1_HANDLER/clk40m" ; - # 240MHz ADC1 regions (namely ser2par for DDR data stream) REGION "ADC1_REGION" "R9C2" 49 4 ; LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ; @@ -81,6 +80,3 @@ LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_R # SerDes ###################################################################### LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ; - - - diff --git a/design/adcmv3.vhd b/design/adcmv3.vhd index 518cc63..6d52b73 100755 --- a/design/adcmv3.vhd +++ b/design/adcmv3.vhd @@ -159,8 +159,8 @@ signal regio_unknown_addr : std_logic; signal regio_timeout : std_logic; -- common status / control registers from RegIO -signal common_stat_reg : std_logic_vector(8*32-1 downto 0); -signal common_ctrl_reg : std_logic_vector(3*32-1 downto 0); +signal common_stat_reg : std_logic_vector(std_COMSTATREG * 32-1 downto 0); +signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG * 32-1 downto 0); -- user defined "quick'n'dirty" registers signal simple_status : std_logic_vector(127 downto 0); diff --git a/design/adcmv3_testfifo.vhd b/design/adcmv3_testfifo.vhd deleted file mode 100644 index 2c5f8f6..0000000 --- a/design/adcmv3_testfifo.vhd +++ /dev/null @@ -1,1450 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; ---use ieee.std_logic_unsigned.all; - -library work; -use work.trb_net_std.all; -use work.adcmv3_components.all; - -library ecp2m; -use ecp2m.components.all; - -entity adcmv3 is -port( - CLK100M : in std_logic; -- OK -- 100MHz LVDS clock - -- trigger inputs - EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers - -- APV stuff - APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock - APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock - APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out - APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out - APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active - APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA - APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL - ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers - APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock - APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock - APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out - APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out - APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active - APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA - APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL - ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers - -- ADC0 stuff - ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL - ADC0_RST : out std_logic; -- OK -- ADC reset signal - ADC0_PD : out std_logic; -- OK -- ADC powerdown signal - ADC0_CS : out std_logic; -- OK -- ADC /CS signal - ADC0_SDI : out std_logic; -- OK -- ADC serial data in - ADC0_SCK : out std_logic; -- OK -- ADC serial clock - ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock - ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock - ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams - -- ADC1 stuff - ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL - ADC1_RST : out std_logic; -- OK -- ADC reset signal - ADC1_PD : out std_logic; -- OK -- ADC powerdown signal - ADC1_CS : out std_logic; -- OK -- ADC /CS signal - ADC1_SDI : out std_logic; -- OK -- ADC serial data in - ADC1_SCK : out std_logic; -- OK -- ADC serial clock - ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock - ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock - ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams - -- uC connections - UC_RESET : in std_logic; -- OK -- uC reset, high active - UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot - -- SerDes pins - HDINN2 : in std_logic; -- highspeed INPUT - HDINP2 : in std_logic; -- - HDOUTN2 : out std_logic; -- highspeed OUTPUT - HDOUTP2 : out std_logic; -- - SD_PRESENT : in std_logic; -- OK -- Present signal from SFP - SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP - SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable - ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM - -- Backplane sense wires - BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane - BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane - BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane - BP_LED : out std_logic; -- OK -- backplane LED - -- LEDs - FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS - FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2) - FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1) - FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0) - FPGA_LED_PLL : out std_logic; -- OK -- PLL locked - FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED - -- 1Wire chips on APV FEs - APV0_1W : inout std_logic_vector(7 downto 0); - APV1_1W : inout std_logic_vector(7 downto 0); - -- SPI FlashROM connections - U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM - U_SPI_SCK : out std_logic; -- OK -- clock - U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM - U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM - -- Debug connections --- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header -); -end; - -architecture adcmv3 of adcmv3 is - --- Signals --- Clock related signals -signal clk100m_locked : std_logic; -- not needed at the moment -signal sysclk : std_logic; -- clean 100MHz for distribution - -signal adc0_ce : std_logic; -signal adc0_valid : std_logic; -signal adc0_swap : std_logic; -signal adc0_reset : std_logic; -signal adc0_powerdown : std_logic; -signal adc1_ce : std_logic; -signal adc1_valid : std_logic; -signal adc1_swap : std_logic; -signal adc1_reset : std_logic; -signal adc1_powerdown : std_logic; - -signal clk_adc : std_logic; -- 40MHz for ADC operation -signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!) -signal clk40m_locked : std_logic; -signal clk40m_reset : std_logic; - -signal async_reset : std_logic; - --- APV related signals -signal apv_sda_out : std_logic; -- APV SDA -signal apv_sda_in : std_logic; -signal apv_scl_out : std_logic; -- APV SCL -signal apv_scl_in : std_logic; -signal apv_trg : std_logic; -- real APV trigger signal -signal apv_sync : std_logic; -- artificial signal -signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame -signal apv0_reset : std_logic; -signal apv1_reset : std_logic; -signal frontend_reset : std_logic; -signal apv_reset : std_logic; -signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] -signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] - --- Control signals -signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register -signal status_pll : std_logic_vector(15 downto 0); -- PLL status register -signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register -signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register - -signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header -signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header -signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting -signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting - -signal maximum_trg : std_logic_vector(3 downto 0); - -signal raw_buf_full : std_logic; -signal eds_buf_full : std_logic; -signal eds_buf_level : std_logic_vector(4 downto 0); - --- regIO data bus -signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); -signal regio_read_enable : std_logic; -signal regio_write_enable : std_logic; -signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); -signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); -signal regio_dataready : std_logic; -signal regio_no_more_data : std_logic; -signal regio_write_ack : std_logic; -signal regio_unknown_addr : std_logic; -signal regio_timeout : std_logic; - --- common status / control registers from RegIO -signal common_stat_reg : std_logic_vector(63 downto 0); -signal common_ctrl_reg : std_logic_vector(63 downto 0); - --- user defined "quick'n'dirty" registers -signal simple_status : std_logic_vector(127 downto 0); -signal simple_control : std_logic_vector(63 downto 0); - --- debug signals -signal test_reg : std_logic_vector(31 downto 0); -signal trbrich_debug : std_logic_vector(63 downto 0); -signal trgctrl_debug : std_logic_vector(63 downto 0); -signal slave_debug : std_logic_vector(63 downto 0); -signal fifo_debug : std_logic_vector(63 downto 0); -signal raw_buf_debug : std_logic_vector(63 downto 0); - --- EDS / BUFFER signals (raw buf -> ped corr) -signal eds_data : std_logic_vector(39 downto 0); -signal eds_avail : std_logic; -signal eds_done : std_logic; -signal buf_addr : std_logic_vector(6 downto 0); -signal buf_done : std_logic; -signal buf_tick : std_logic_vector(15 downto 0); -signal buf_start : std_logic_vector(15 downto 0); -signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging! - -type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0); -signal buf_data : reg_38bit_t; - -signal thr_addr : std_logic_vector(6 downto 0); -type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); -signal thr_data : reg_18bit_t; -signal ped_data : reg_18bit_t; - --- FIFO / DHDR signals (ped corr -> ipu stage) -signal dhdr_data : std_logic_vector(31 downto 0); -signal dhdr_length : std_logic_vector(15 downto 0); -signal dhdr_store : std_logic; -signal dhdr_buf_full : std_logic; - -signal fifo_start : std_logic; -signal fifo_done : std_logic; -signal fifo_we : std_logic_vector(15 downto 0); -signal fifo_space_req : std_logic_vector(11 downto 0); -type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0); -signal fifo_data : reg_40bit_t; -type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0); -signal fifo_status : reg_32bit_t; - -signal ipu_handler_status : std_logic_vector(31 downto 0); -signal lvl1_release_status : std_logic_vector(31 downto 0); - --- APV control / status signals -type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); -signal adc_ctrl_reg : reg_16bit_t; -signal adc_stat_reg : reg_16bit_t; - -signal debug : std_logic_vector(42 downto 0); -signal debug_q : std_logic_vector(42 downto 0); -signal debug_qq : std_logic_vector(42 downto 0); -signal debug_clk : std_logic; - --- LVL1 application interface -signal lvl1_trg_type : std_logic_vector(3 downto 0); -signal lvl1_trg_received : std_logic; -signal lvl1_trg_number : std_logic_vector(15 downto 0); -signal lvl1_trg_code : std_logic_vector(7 downto 0); -signal lvl1_trg_information : std_logic_vector(23 downto 0); -signal lvl1_error_pattern : std_logic_vector(31 downto 0); -signal lvl1_trg_release : std_logic; -signal lvl1_trg_missing : std_logic; -signal lvl1_int_trg_number : std_logic_vector(15 downto 0); -signal lvl1_int_trg_update : std_logic; -signal timing_trg_found : std_logic; - --- IPU application interface -signal ipu_number : std_logic_vector(15 downto 0); -signal ipu_information : std_logic_vector(7 downto 0); -signal ipu_start_readout : std_logic; -signal ipu_data : std_logic_vector(31 downto 0); -signal ipu_dataready : std_logic; -signal ipu_readout_finished : std_logic; -signal ipu_read : std_logic; -signal ipu_length : std_logic_vector(15 downto 0); -signal ipu_error_pattern : std_logic_vector(31 downto 0); -signal ipu_last_num : std_logic_vector(31 downto 0); - -signal local_lvl1_counter : std_logic_vector(15 downto 0); -signal local_lvl2_counter : std_logic_vector(15 downto 0); - --- ADC signals -type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0); -signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain -signal adc_data : reg_12bit_t; -- common APV clock domain - -signal adc1_testdata : std_logic_vector(11 downto 0); -signal adc0_testdata : std_logic_vector(11 downto 0); -signal adc1_select : std_logic_vector(2 downto 0); -signal adc0_select : std_logic_vector(2 downto 0); - --- input synchronizing -signal bp_sector_q : std_logic_vector(3 downto 0); -signal bp_sector_qq : std_logic_vector(3 downto 0); -signal bp_module_q : std_logic_vector(3 downto 0); -signal bp_module_qq : std_logic_vector(3 downto 0); - -signal lsm_state_bits : std_logic_vector(3 downto 0); -signal reset_by_trb : std_logic; -signal global_sync_reset : std_logic; - -signal adc0_iodelay : std_logic_vector(3 downto 0); -signal adc1_iodelay : std_logic_vector(3 downto 0); - -signal cts_clk40m : std_logic; -signal cts_clk40m_locked : std_logic; -signal test_reg40m : std_logic; - -signal serious_error_flag : std_logic; -signal error_flag : std_logic; -signal warning_flag : std_logic; -signal note_flag : std_logic; - -signal broken_buf : std_logic_vector(15 downto 0); -signal next_not_configured : std_logic; -signal not_configured : std_logic; - -signal apv_error : std_logic_vector(15 downto 0); -signal next_fe_error : std_logic; -signal fe_error : std_logic; - -signal test_data_in : unsigned(17 downto 0); -signal test_data_out : std_logic_vector(17 downto 0); -signal test_data_wren : std_logic; -signal test_data_rden : std_logic; -signal test_data_empty : std_logic; -signal test_data_full : std_logic; - -component lattice_ecp2m_fifo_16bit_dualport is -port( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic -); -end component lattice_ecp2m_fifo_16bit_dualport; - -begin - - ----------------------------------------- --- TEST TEST TEST TEST TEST ----------------------------------------- -THE_TEST_COUNTER: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - if( global_sync_reset = '1' ) then - test_data_in <= (others => '0'); - else - test_data_in <= test_data_in + 1; - end if; - end if; -end process THE_TEST_COUNTER; - -THE_TEST_FIFO: lattice_ecp2m_fifo_16bit_dualport -port map( - Data => std_logic_vector(test_data_in), - WrClock => sysclk, - RdClock => sysclk, - WrEn => test_data_wren, - RdEn => test_data_rden, - Reset => global_sync_reset, - RPReset => '0', - Q => test_data_out, - Empty => test_data_empty, - Full => test_data_full -); - -test_data_rden <= not test_data_empty; -test_data_wren <= std_logic(test_data_in(3)); - - -simple_status(63 downto 54) <= (others => '0'); -simple_status(53) <= test_data_wren; -simple_status(52) <= test_data_rden; -simple_status(51) <= test_data_full; -simple_status(50) <= test_data_empty; -simple_status(49 downto 32) <= test_data_out; ----------------------------------------- --- TEST TEST TEST TEST TEST ----------------------------------------- - ----------------------------------------- --- Async reset assignment -- ----------------------------------------- -async_reset <= uc_reset; -- uC reset pin - - ----------------------------------------- --- Reset handler / spike surpression -- ----------------------------------------- -THE_RESET_HANDLER: reset_handler -generic map ( - RESET_DELAY => x"00ff" -) -port map ( - CLEAR_IN => async_reset, - CLEAR_N_IN => '1', -- unused - CLK_IN => clk100m, - SYSCLK_IN => sysclk, - PLL_LOCKED_IN => clk100m_locked, - RESET_IN => common_ctrl_reg(3), - TRB_RESET_IN => reset_by_trb, - CLEAR_OUT => open, - RESET_OUT => global_sync_reset, - DEBUG_OUT => open -); - - ----------------------------------------- --- Reboot handler (pulse triggered) -- ----------------------------------------- -THE_REBOOT_HANDLER: reboot_handler -port map( - RESET_IN => reset_by_trb, - CLK_IN => sysclk, - START_IN => common_ctrl_reg(15), - REBOOT_OUT => uc_reboot, - DEBUG_OUT => open -); - - ----------------------------------------- --- 100MHz PLL -> 40MHz / 100MHz -- ----------------------------------------- --- 100MHz PLL, generating 40MHz and phase shifted 40MHz -THE_40M_PLL: PLL_40M -port map( - CLK => clk100m, - RESET => clk40m_reset, - DPAMODE => '1', -- dynamic control - DPHASE0 => ctrl_pll(0), - DPHASE1 => ctrl_pll(1), - DPHASE2 => ctrl_pll(2), - DPHASE3 => ctrl_pll(3), - CLKOP => clk_apv, -- fixed phase, used for logic - CLKOS => clk_adc, -- phase adjustable, for ODDRXC only - LOCK => clk40m_locked -); -clk40m_reset <= ctrl_pll(7); - --- 100MHz DLL, used for clock injection delay removal -THE_100M_DLL: dll_100m -port map( - CLK => clk100m, - RESETN => '1', - ALUHOLD => '0', - CLKOP => sysclk, - CLKOS => open, - LOCK => clk100m_locked -); - --- 40MHz PLL, takes central clock distributed by CTS -THE_SYNC_PLL: sync_pll_40m -port map( - CLK => ext_in(3), - RESET => ctrl_pll(4), - CLKOP => cts_clk40m, - LOCK => cts_clk40m_locked -); - -THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked ) -begin - if( cts_clk40m_locked = '0' ) then - test_reg40m <= '0'; - else - if( rising_edge(cts_clk40m) ) then - test_reg40m <= not test_reg40m; - end if; - end if; -end process THE_TEST_REG; - ----------------------------------------- --- TRB endpoint -- ----------------------------------------- -THE_RICH_TRB: rich_trb -port map( - CLK100M_IN => clk100m, -- SerDes exclusive clock - SYSCLK_IN => sysclk, -- fabric clock - RESET_IN => global_sync_reset, - SD_RXD_P_IN => hdinp2, - SD_RXD_N_IN => hdinn2, - SD_TXD_P_OUT => hdoutp2, - SD_TXD_N_OUT => hdoutn2, - SD_PRESENT_IN => sd_present, - SD_TXDIS_OUT => sd_txdis, - SD_LOS_IN => sd_los, - ONEWIRE_INOUT => adcm_onewire, - -- common regIO status / control registers - COMMON_STAT_REG_IN => common_stat_reg, - COMMON_CTRL_REG_OUT => common_ctrl_reg, - -- status register input to regIO / control register output from regIO - CONTROL_OUT => simple_control, - STATUS_IN => simple_status, - -- LVL1 signals - LVL1_TRG_TYPE_OUT => lvl1_trg_type, - LVL1_TRG_RECEIVED_OUT => lvl1_trg_received, - LVL1_TRG_NUMBER_OUT => lvl1_trg_number, - LVL1_TRG_CODE_OUT => lvl1_trg_code, - LVL1_TRG_INFORMATION_OUT => lvl1_trg_information, - LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, - LVL1_TRG_RELEASE_IN => lvl1_trg_release, - LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter - LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter - TIMING_TRG_FOUND_IN => timing_trg_found, - -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) - IPU_NUMBER_OUT => ipu_number, - IPU_INFORMATION_OUT => ipu_information, - IPU_START_READOUT_OUT => ipu_start_readout, - IPU_DATA_IN => ipu_data, - IPU_DATAREADY_IN => ipu_dataready, - IPU_READOUT_FINISHED_IN => ipu_readout_finished, - IPU_READ_OUT => ipu_read, - IPU_LENGTH_IN => ipu_length, - IPU_ERROR_PATTERN_IN => ipu_error_pattern, - -- regIO bus - REGIO_ADDR_OUT => regio_addr, - REGIO_READ_ENABLE_OUT => regio_read_enable, - REGIO_WRITE_ENABLE_OUT => regio_write_enable, - REGIO_DATA_OUT => regio_data_wr, - REGIO_DATA_IN => regio_data_rd, - REGIO_DATAREADY_IN => regio_dataready, - REGIO_NO_MORE_DATA_IN => regio_no_more_data, - REGIO_WRITE_ACK_IN => regio_write_ack, - REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr, - REGIO_TIMEOUT_OUT => regio_timeout, - -- status LEDs - LED_LINK_STAT => fpga_led_link, - LED_LINK_TXD => fpga_led_txd, - LED_LINK_RXD => fpga_led_rxd, - LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits - RESET_OUT => reset_by_trb, - DEBUG => trbrich_debug --open -); - --- common control register bit definitions --- [31:24] --- --- [23:16] fake timing trigger --- [15] reboot FPGA --- [14:11] --- --- [10] reset sequence counter --- [9:4] --- --- [3] master reset, reset the whole endpoint --- [2] empty IPU chain, reset IPU logic --- [1] reset trigger logic --- [0] reset frontends - --- LVL1 error pattern, to be sent back to CTS with each trigger -lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved -lvl1_error_pattern(23) <= fe_error; -- frontend error -lvl1_error_pattern(22) <= not_configured; -- not configured -lvl1_error_pattern(21) <= '0'; -- buffers almost full -lvl1_error_pattern(20) <= '0'; -- buffers half full -lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved -lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan) -lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan) -lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits - - ----------------------------------------------- --- mixed status and control bit definitions -- ----------------------------------------------- - --- Common status register --- CSR1 -common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter -common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter --- CSR0 -common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor -common_stat_reg(19 downto 13) <= (others => '0'); -common_stat_reg(12) <= '0'; -- IPU: single broken event -common_stat_reg(11) <= '0'; -- IPU: severe problem -common_stat_reg(10) <= '0'; -- IPU: partially not found -common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found -common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing -common_stat_reg(7) <= fe_error; -- LVL1: frontend error -common_stat_reg(6) <= not_configured; -- LVL1: not configured -common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented) -common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved) -common_stat_reg(3) <= note_flag; -- note flag -common_stat_reg(2) <= warning_flag; -- warning flag -common_stat_reg(1) <= error_flag; -- error flag -common_stat_reg(0) <= serious_error_flag; -- serious error flag - -serious_error_flag <= lvl1_trg_missing or fe_error or not_configured; -error_flag <= ipu_error_pattern(20); -warning_flag <= '0'; -note_flag <= '0'; - --- Control register bit padding -ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0"; -ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0"; -ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0"; -ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0"; - --- LVDS driver enable -ena_lvds(0) <= adc_on(4) or lvds_on(4); -ena_lvds(1) <= adc_on(3) or lvds_on(3); -ena_lvds(2) <= adc_on(5) or lvds_on(5); -ena_lvds(3) <= adc_on(2) or lvds_on(2); -ena_lvds(4) <= adc_on(6) or lvds_on(6); -ena_lvds(5) <= adc_on(1) or lvds_on(1); -ena_lvds(6) <= adc_on(7) or lvds_on(7); -ena_lvds(7) <= adc_on(0) or lvds_on(0); - -enb_lvds(0) <= adc_on(13) or lvds_on(13); -enb_lvds(1) <= adc_on(10) or lvds_on(10); -enb_lvds(2) <= adc_on(12) or lvds_on(12); -enb_lvds(3) <= adc_on(11) or lvds_on(11); -enb_lvds(4) <= adc_on(15) or lvds_on(15); -enb_lvds(5) <= adc_on(8) or lvds_on(8); -enb_lvds(6) <= adc_on(14) or lvds_on(14); -enb_lvds(7) <= adc_on(9) or lvds_on(9); - -bp_led <= cts_clk40m_locked; -- LED is against GND! - - ----------------------------------------- --- internal slave bus -> slow control -- ----------------------------------------- -THE_SLAVE_BUS: slave_bus -port map( - CLK_IN => sysclk, - RESET_IN => global_sync_reset, - -- RegIO signals - REGIO_ADDR_IN => regio_addr, - REGIO_DATA_IN => regio_data_wr, - REGIO_DATA_OUT => regio_data_rd, - REGIO_READ_ENABLE_IN => regio_read_enable, - REGIO_WRITE_ENABLE_IN => regio_write_enable, - REGIO_TIMEOUT_IN => regio_timeout, - REGIO_DATAREADY_OUT => regio_dataready, - REGIO_WRITE_ACK_OUT => regio_write_ack, - REGIO_NO_MORE_DATA_OUT => regio_no_more_data, - REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr, - -- I2C connections - SDA_IN => apv_sda_in, - SDA_OUT => apv_sda_out, - SCL_IN => apv_scl_in, - SCL_OUT => apv_scl_out, - -- 1Wire connections - ONEWIRE_START_IN => '0', -- not used yet - ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0), - ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0), - BP_ONEWIRE_INOUT => bp_onewire, - -- SPI connections - SPI_CS_OUT => u_spi_cs, - SPI_SCK_OUT => u_spi_sck, - SPI_SDI_IN => u_spi_sdo, - SPI_SDO_OUT => u_spi_sdi, - -- ADC 0 SPI connections - SPI_ADC0_CS_OUT => adc0_cs, - SPI_ADC0_SCK_OUT => adc0_sck, - SPI_ADC0_SDO_OUT => adc0_sdi, - ADC0_PLL_LOCKED_IN => adc0_valid, - ADC0_PD_OUT => adc0_powerdown, - ADC0_RST_OUT => adc0_reset, - ADC0_DEL_OUT => adc0_iodelay, - ADC0_CLK_IN => clk_apv, - ADC0_DATA_IN => adc0_testdata, - ADC0_SEL_OUT => adc0_select, - APV0_RST_OUT => apv0_reset, - -- ADC 0 SPI connections - SPI_ADC1_CS_OUT => adc1_cs, - SPI_ADC1_SCK_OUT => adc1_sck, - SPI_ADC1_SDO_OUT => adc1_sdi, - ADC1_PLL_LOCKED_IN => adc1_valid, - ADC1_PD_OUT => adc1_powerdown, - ADC1_RST_OUT => adc1_reset, - ADC1_DEL_OUT => adc1_iodelay, - ADC1_CLK_IN => clk_apv, - ADC1_DATA_IN => adc1_testdata, - ADC1_SEL_OUT => adc1_select, - APV1_RST_OUT => apv1_reset, - -- backplane identifier - BACKPLANE_IN => bp_module_qq(2 downto 0), - -- pedestal interface - PED_ADDR_IN => buf_addr, - PED_DATA_0_OUT => ped_data(0), - PED_DATA_1_OUT => ped_data(1), - PED_DATA_2_OUT => ped_data(2), - PED_DATA_3_OUT => ped_data(3), - PED_DATA_4_OUT => ped_data(4), - PED_DATA_5_OUT => ped_data(5), - PED_DATA_6_OUT => ped_data(6), - PED_DATA_7_OUT => ped_data(7), - PED_DATA_8_OUT => ped_data(8), - PED_DATA_9_OUT => ped_data(9), - PED_DATA_10_OUT => ped_data(10), - PED_DATA_11_OUT => ped_data(11), - PED_DATA_12_OUT => ped_data(12), - PED_DATA_13_OUT => ped_data(13), - PED_DATA_14_OUT => ped_data(14), - PED_DATA_15_OUT => ped_data(15), - -- threshold interface - THR_ADDR_IN => thr_addr, - THR_DATA_0_OUT => thr_data(0), - THR_DATA_1_OUT => thr_data(1), - THR_DATA_2_OUT => thr_data(2), - THR_DATA_3_OUT => thr_data(3), - THR_DATA_4_OUT => thr_data(4), - THR_DATA_5_OUT => thr_data(5), - THR_DATA_6_OUT => thr_data(6), - THR_DATA_7_OUT => thr_data(7), - THR_DATA_8_OUT => thr_data(8), - THR_DATA_9_OUT => thr_data(9), - THR_DATA_10_OUT => thr_data(10), - THR_DATA_11_OUT => thr_data(11), - THR_DATA_12_OUT => thr_data(12), - THR_DATA_13_OUT => thr_data(13), - THR_DATA_14_OUT => thr_data(14), - THR_DATA_15_OUT => thr_data(15), - -- APV control / status - CTRL_0_OUT => adc_ctrl_reg(0), - CTRL_1_OUT => adc_ctrl_reg(1), - CTRL_2_OUT => adc_ctrl_reg(2), - CTRL_3_OUT => adc_ctrl_reg(3), - CTRL_4_OUT => adc_ctrl_reg(4), - CTRL_5_OUT => adc_ctrl_reg(5), - CTRL_6_OUT => adc_ctrl_reg(6), - CTRL_7_OUT => adc_ctrl_reg(7), - CTRL_8_OUT => adc_ctrl_reg(8), - CTRL_9_OUT => adc_ctrl_reg(9), - CTRL_10_OUT => adc_ctrl_reg(10), - CTRL_11_OUT => adc_ctrl_reg(11), - CTRL_12_OUT => adc_ctrl_reg(12), - CTRL_13_OUT => adc_ctrl_reg(13), - CTRL_14_OUT => adc_ctrl_reg(14), - CTRL_15_OUT => adc_ctrl_reg(15), - STAT_0_IN => adc_stat_reg(0), - STAT_1_IN => adc_stat_reg(1), - STAT_2_IN => adc_stat_reg(2), - STAT_3_IN => adc_stat_reg(3), - STAT_4_IN => adc_stat_reg(4), - STAT_5_IN => adc_stat_reg(5), - STAT_6_IN => adc_stat_reg(6), - STAT_7_IN => adc_stat_reg(7), - STAT_8_IN => adc_stat_reg(8), - STAT_9_IN => adc_stat_reg(9), - STAT_10_IN => adc_stat_reg(10), - STAT_11_IN => adc_stat_reg(11), - STAT_12_IN => adc_stat_reg(12), - STAT_13_IN => adc_stat_reg(13), - STAT_14_IN => adc_stat_reg(14), - STAT_15_IN => adc_stat_reg(15), - -- FIFO status - FIFO_STATUS_0_IN => fifo_status(0), - FIFO_STATUS_1_IN => fifo_status(1), - FIFO_STATUS_2_IN => fifo_status(2), - FIFO_STATUS_3_IN => fifo_status(3), - FIFO_STATUS_4_IN => fifo_status(4), - FIFO_STATUS_5_IN => fifo_status(5), - FIFO_STATUS_6_IN => fifo_status(6), - FIFO_STATUS_7_IN => fifo_status(7), - FIFO_STATUS_8_IN => fifo_status(8), - FIFO_STATUS_9_IN => fifo_status(9), - FIFO_STATUS_10_IN => fifo_status(10), - FIFO_STATUS_11_IN => fifo_status(11), - FIFO_STATUS_12_IN => fifo_status(12), - FIFO_STATUS_13_IN => fifo_status(13), - FIFO_STATUS_14_IN => fifo_status(14), - FIFO_STATUS_15_IN => fifo_status(15), - IPU_STATUS_IN => ipu_handler_status, - RELEASE_STATUS_IN => lvl1_release_status, - -- some control signals - CTRL_LVL_OUT => ctrl_lvl, - CTRL_TRG_OUT => ctrl_trg, - CTRL_PLL_OUT => ctrl_pll, - STATUS_PLL_IN => status_pll, - -- temporary stuff - TEST_REG_IN => test_reg, -- short cut - TEST_REG_OUT => test_reg, - -- Debug - DEBUG_OUT => slave_debug, --open - STAT => open -); - --- PLL status register -status_pll(15) <= clk100m_locked; -status_pll(14) <= clk40m_locked; -status_pll(13) <= adc1_valid; -status_pll(12) <= adc0_valid; -status_pll(11) <= adc1_swap; -status_pll(10) <= adc0_swap; -status_pll(9) <= test_reg40m; --'0'; -status_pll(8) <= cts_clk40m_locked; -status_pll(7) <= '0'; -- make it human readable -status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only -status_pll(3) <= '0'; -- make it human readable -status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only - --- Common status register, do not use. -simple_status(127 downto 104) <= (others => '0'); -simple_status(103 downto 96) <= trgctrl_debug(39 downto 32); -simple_status(95 downto 64) <= trgctrl_debug(31 downto 0); ---simple_status(63 downto 32) <= (others => '0'); -simple_status(31 downto 16) <= local_lvl2_counter; -simple_status(15 downto 0) <= local_lvl1_counter; - --- all APVs are reset together, including the common FE reset -THE_APV_PULSE_STRETCH: pulse_stretch -port map( - CLK_IN => sysclk, - RESET_IN => global_sync_reset, - START_IN => common_ctrl_reg(0), - PULSE_OUT => frontend_reset, - DEBUG_OUT => open -); - -apv_reset <= apv0_reset or apv1_reset or frontend_reset; - --- APV status registers --- "ADC on" bits --- "LVDS ON" bits -GEN_ADC_LVDS_ON: for i in 0 to 15 generate - adc_on(i) <= adc_ctrl_reg(i)(0); - lvds_on(i) <= adc_ctrl_reg(i)(1); - adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4)); - broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit - apv_error(i) <= buf_data(i)(26); -- APV error frame bit -end generate GEN_ADC_LVDS_ON; - -next_not_configured <= '1' when (broken_buf /= x"0000") else '0'; -next_fe_error <= '1' when (apv_error /= x"0000") else '0'; - ----------------------------------------- --- IPU endpoint for data transport -- ----------------------------------------- -THE_IPU_STAGE: ipu_fifo_stage -port map( - CLK_IN => sysclk, - RESET_IN => global_sync_reset, - -- Slow control signals - SECTOR_IN => bp_sector_qq(2 downto 0), - MODULE_IN => bp_module_qq(2 downto 0), - -- IPU channel connections - IPU_NUMBER_IN => ipu_number, - IPU_INFORMATION_IN => ipu_information, - IPU_START_READOUT_IN => ipu_start_readout, - IPU_DATA_OUT => ipu_data, - IPU_DATAREADY_OUT => ipu_dataready, - IPU_READOUT_FINISHED_OUT => ipu_readout_finished, - IPU_READ_IN => ipu_read, - IPU_LENGTH_OUT => ipu_length, - IPU_ERROR_PATTERN_OUT => ipu_error_pattern, - IPU_LAST_NUM_OUT => ipu_last_num, - LVL2_COUNTER_OUT => local_lvl2_counter, - -- DHDR buffer input - DHDR_DATA_IN => dhdr_data, - DHDR_LENGTH_IN => dhdr_length, - DHDR_STORE_IN => dhdr_store, - DHDR_BUF_FULL_OUT => dhdr_buf_full, - -- processed data input - FIFO_SPACE_REQ_IN => fifo_space_req, - FIFO_START_IN => fifo_start, - FIFO_0_DATA_IN => fifo_data(0), - FIFO_1_DATA_IN => fifo_data(1), - FIFO_2_DATA_IN => fifo_data(2), - FIFO_3_DATA_IN => fifo_data(3), - FIFO_4_DATA_IN => fifo_data(4), - FIFO_5_DATA_IN => fifo_data(5), - FIFO_6_DATA_IN => fifo_data(6), - FIFO_7_DATA_IN => fifo_data(7), - FIFO_8_DATA_IN => fifo_data(8), - FIFO_9_DATA_IN => fifo_data(9), - FIFO_10_DATA_IN => fifo_data(10), - FIFO_11_DATA_IN => fifo_data(11), - FIFO_12_DATA_IN => fifo_data(12), - FIFO_13_DATA_IN => fifo_data(13), - FIFO_14_DATA_IN => fifo_data(14), - FIFO_15_DATA_IN => fifo_data(15), - FIFO_WE_IN => fifo_we, - FIFO_DONE_IN => fifo_done, - FIFO_0_STATUS_OUT => fifo_status(0), - FIFO_1_STATUS_OUT => fifo_status(1), - FIFO_2_STATUS_OUT => fifo_status(2), - FIFO_3_STATUS_OUT => fifo_status(3), - FIFO_4_STATUS_OUT => fifo_status(4), - FIFO_5_STATUS_OUT => fifo_status(5), - FIFO_6_STATUS_OUT => fifo_status(6), - FIFO_7_STATUS_OUT => fifo_status(7), - FIFO_8_STATUS_OUT => fifo_status(8), - FIFO_9_STATUS_OUT => fifo_status(9), - FIFO_10_STATUS_OUT => fifo_status(10), - FIFO_11_STATUS_OUT => fifo_status(11), - FIFO_12_STATUS_OUT => fifo_status(12), - FIFO_13_STATUS_OUT => fifo_status(13), - FIFO_14_STATUS_OUT => fifo_status(14), - FIFO_15_STATUS_OUT => fifo_status(15), - IPU_STATUS_OUT => ipu_handler_status, - RELEASE_STATUS_OUT => lvl1_release_status, - -- Debug signals - DBG_BSM_OUT => open, - DBG_OUT => fifo_debug --open -); - - ----------------------------------------- --- Data processing unit -- ----------------------------------------- -THE_PED_CORR_STAGE: ped_corr_ctrl -port map( - CLK_IN => sysclk, - RESET_IN => global_sync_reset, - VERBOSE_IN => common_ctrl_reg(31), -- QUICKHACK - EDS_DATA_IN => eds_data, - EDS_AVAIL_IN => eds_avail, - EDS_DONE_OUT => eds_done, - -- DHDR information -- to next stage - DHDR_DATA_OUT => dhdr_data, - DHDR_LENGTH_OUT => dhdr_length, - DHDR_STORE_OUT => dhdr_store, - DHDR_BUF_FULL_IN => dhdr_buf_full, - FIFO_SPACE_REQ_OUT => fifo_space_req, - -- data buffers -- from raw_buf_stage - BUF_ADDR_OUT => buf_addr, - BUF_DONE_OUT => buf_done, - BUF_TICK_IN => buf_tick, - BUF_START_IN => buf_start, - -- raw data - BUF_0_DATA_IN => buf_data(0), - BUF_1_DATA_IN => buf_data(1), - BUF_2_DATA_IN => buf_data(2), - BUF_3_DATA_IN => buf_data(3), - BUF_4_DATA_IN => buf_data(4), - BUF_5_DATA_IN => buf_data(5), - BUF_6_DATA_IN => buf_data(6), - BUF_7_DATA_IN => buf_data(7), - BUF_8_DATA_IN => buf_data(8), - BUF_9_DATA_IN => buf_data(9), - BUF_10_DATA_IN => buf_data(10), - BUF_11_DATA_IN => buf_data(11), - BUF_12_DATA_IN => buf_data(12), - BUF_13_DATA_IN => buf_data(13), - BUF_14_DATA_IN => buf_data(14), - BUF_15_DATA_IN => buf_data(15), - -- Pedestal data - PED_ADDR_OUT => open, -- BUGBUGBUG - PED_0_DATA_IN => ped_data(0), - PED_1_DATA_IN => ped_data(1), - PED_2_DATA_IN => ped_data(2), - PED_3_DATA_IN => ped_data(3), - PED_4_DATA_IN => ped_data(4), - PED_5_DATA_IN => ped_data(5), - PED_6_DATA_IN => ped_data(6), - PED_7_DATA_IN => ped_data(7), - PED_8_DATA_IN => ped_data(8), - PED_9_DATA_IN => ped_data(9), - PED_10_DATA_IN => ped_data(10), - PED_11_DATA_IN => ped_data(11), - PED_12_DATA_IN => ped_data(12), - PED_13_DATA_IN => ped_data(13), - PED_14_DATA_IN => ped_data(14), - PED_15_DATA_IN => ped_data(15), - -- Threshold data - THR_ADDR_OUT => thr_addr, - THR_0_DATA_IN => thr_data(0), - THR_1_DATA_IN => thr_data(1), - THR_2_DATA_IN => thr_data(2), - THR_3_DATA_IN => thr_data(3), - THR_4_DATA_IN => thr_data(4), - THR_5_DATA_IN => thr_data(5), - THR_6_DATA_IN => thr_data(6), - THR_7_DATA_IN => thr_data(7), - THR_8_DATA_IN => thr_data(8), - THR_9_DATA_IN => thr_data(9), - THR_10_DATA_IN => thr_data(10), - THR_11_DATA_IN => thr_data(11), - THR_12_DATA_IN => thr_data(12), - THR_13_DATA_IN => thr_data(13), - THR_14_DATA_IN => thr_data(14), - THR_15_DATA_IN => thr_data(15), - -- processed data - FIFO_START_OUT => fifo_start, - FIFO_0_DATA_OUT => fifo_data(0), - FIFO_1_DATA_OUT => fifo_data(1), - FIFO_2_DATA_OUT => fifo_data(2), - FIFO_3_DATA_OUT => fifo_data(3), - FIFO_4_DATA_OUT => fifo_data(4), - FIFO_5_DATA_OUT => fifo_data(5), - FIFO_6_DATA_OUT => fifo_data(6), - FIFO_7_DATA_OUT => fifo_data(7), - FIFO_8_DATA_OUT => fifo_data(8), - FIFO_9_DATA_OUT => fifo_data(9), - FIFO_10_DATA_OUT => fifo_data(10), - FIFO_11_DATA_OUT => fifo_data(11), - FIFO_12_DATA_OUT => fifo_data(12), - FIFO_13_DATA_OUT => fifo_data(13), - FIFO_14_DATA_OUT => fifo_data(14), - FIFO_15_DATA_OUT => fifo_data(15), - FIFO_WE_OUT => fifo_we, - FIFO_DONE_OUT => fifo_done, - -- Debug signals - DBG_BSM_OUT => open, - DBG_OUT => open -); - - ------------------------------------------- --- Raw data processing and storage unit -- ------------------------------------------- -THE_RAW_BUF_STAGE: raw_buf_stage -port map( - CLK_IN => sysclk, - CLK_APV_IN => clk_apv, - RESET_IN => reset_by_trb, - -- trigger related signals - APV_RESET_IN => apv_reset, -- (100MHz clock) - APV_SYNC_IN => apv_sync, -- (40MHz APV clock) - APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock) - -- ADC0 signals - ADC0_VALID_IN => adc0_valid, - ADC0_0_DATA_IN => adc_data(0), - ADC0_1_DATA_IN => adc_data(1), - ADC0_2_DATA_IN => adc_data(2), - ADC0_3_DATA_IN => adc_data(3), - ADC0_4_DATA_IN => adc_data(4), - ADC0_5_DATA_IN => adc_data(5), - ADC0_6_DATA_IN => adc_data(6), - ADC0_7_DATA_IN => adc_data(7), - -- ADC1 signals - ADC1_VALID_IN => adc1_valid, - ADC1_0_DATA_IN => adc_data(8), - ADC1_1_DATA_IN => adc_data(9), - ADC1_2_DATA_IN => adc_data(10), - ADC1_3_DATA_IN => adc_data(11), - ADC1_4_DATA_IN => adc_data(12), - ADC1_5_DATA_IN => adc_data(13), - ADC1_6_DATA_IN => adc_data(14), - ADC1_7_DATA_IN => adc_data(15), - -- Slow control registers - MAX_TRG_NUM_IN => maximum_trg, -- automatically determined - BIT_LOW_IN => ctrl_bitlow, -- from slow control - BIT_HIGH_IN => ctrl_bithigh, -- from slow control - FL_LOW_IN => ctrl_flatlow, -- from slow control - FL_HIGH_IN => ctrl_flathigh, -- from slow control - APV_ON_IN => adc_on, - -- 100MHZ synchronous interface - -- APV raw buffers - BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW - BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl - BUF_DONE_IN => buf_done, -- from ped_corr_ctrl - BUF_TICK_OUT => buf_tick, - BUF_START_OUT => buf_start, - BUF_READY_OUT => buf_ready, - BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl - BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl - BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl - BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl - BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl - BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl - BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl - BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl - BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl - BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl - BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl - BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl - BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl - BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl - BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl - BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl - -- Debug signals - DEBUG_OUT => raw_buf_debug --open -); - - ----------------------------------------- --- ADC1 data handler -- ----------------------------------------- -THE_ADC1_HANDLER: adc_data_handler -port map( - RESET_IN => reset_by_trb, - ADC_LCLK_IN => adc1_lclk, - ADC_ADCLK_IN => adc1_adclk, - ADC_CHNL_IN => adc1_out, - PLL_CTRL_IN => adc1_iodelay, - ADC_DATA7_OUT => adc_raw_data(15), - ADC_DATA6_OUT => adc_raw_data(14), - ADC_DATA5_OUT => adc_raw_data(13), - ADC_DATA4_OUT => adc_raw_data(12), - ADC_DATA3_OUT => adc_raw_data(11), - ADC_DATA2_OUT => adc_raw_data(10), - ADC_DATA1_OUT => adc_raw_data(9), - ADC_DATA0_OUT => adc_raw_data(8), - ADC_CE_OUT => adc1_ce, - ADC_VALID_OUT => adc1_valid, - ADC_SWAP_OUT => adc1_swap, - DEBUG_OUT => open -); - - ----------------------------------------- --- ADC1 clock domain crossover -- ----------------------------------------- -THE_ADC1_CROSSOVER: adc_crossover -port map( - CLK_APV_IN => clk_apv, - RESET_IN => global_sync_reset, - -- ADC clock domain signals - ADC_CLK_IN => adc1_lclk, - ADC_CE_IN => adc1_ce, - ADC_DATA_VALID_IN => adc1_valid, - ADC_DATA_7_IN => adc_raw_data(15), - ADC_DATA_6_IN => adc_raw_data(14), - ADC_DATA_5_IN => adc_raw_data(13), - ADC_DATA_4_IN => adc_raw_data(12), - ADC_DATA_3_IN => adc_raw_data(11), - ADC_DATA_2_IN => adc_raw_data(10), - ADC_DATA_1_IN => adc_raw_data(9), - ADC_DATA_0_IN => adc_raw_data(8), - LEVEL_WR_OUT => open, - -- APV clock domain signals - APV_DATA_7_OUT => adc_data(15), - APV_DATA_6_OUT => adc_data(14), - APV_DATA_5_OUT => adc_data(13), - APV_DATA_4_OUT => adc_data(12), - APV_DATA_3_OUT => adc_data(11), - APV_DATA_2_OUT => adc_data(10), - APV_DATA_1_OUT => adc_data(9), - APV_DATA_0_OUT => adc_data(8), - APV_DATA_VALID_OUT => open, - LEVEL_RD_OUT => open, - -- Debug signals - DEBUG_OUT => open -); - - ----------------------------------------- --- ADC1 test data multiplexer -- ----------------------------------------- -THE_ADC_1_SELECT: adc_channel_select -port map( - RESET_IN => reset_by_trb, - ADC_CLK_IN => clk_apv, - ADC_SEL_IN => adc1_select, - ADC_7_IN => adc_data(15), - ADC_6_IN => adc_data(14), - ADC_5_IN => adc_data(13), - ADC_4_IN => adc_data(12), - ADC_3_IN => adc_data(11), - ADC_2_IN => adc_data(10), - ADC_1_IN => adc_data(9), - ADC_0_IN => adc_data(8), - ADC_CH_OUT => adc1_testdata, - DEBUG_OUT => open -); - - ----------------------------------------- --- ADC0 data handler -- ----------------------------------------- -THE_ADC0_HANDLER: adc_data_handler -port map( - RESET_IN => reset_by_trb, - ADC_LCLK_IN => adc0_lclk, - ADC_ADCLK_IN => adc0_adclk, - ADC_CHNL_IN => adc0_out, - PLL_CTRL_IN => adc0_iodelay, - ADC_DATA7_OUT => adc_raw_data(7), - ADC_DATA6_OUT => adc_raw_data(6), - ADC_DATA5_OUT => adc_raw_data(5), - ADC_DATA4_OUT => adc_raw_data(4), - ADC_DATA3_OUT => adc_raw_data(3), - ADC_DATA2_OUT => adc_raw_data(2), - ADC_DATA1_OUT => adc_raw_data(1), - ADC_DATA0_OUT => adc_raw_data(0), - ADC_CE_OUT => adc0_ce, - ADC_VALID_OUT => adc0_valid, - ADC_SWAP_OUT => adc0_swap, - DEBUG_OUT => open -); - - ----------------------------------------- --- ADC0 clock domain crossover -- ----------------------------------------- -THE_ADC0_CROSSOVER: adc_crossover -port map( - CLK_APV_IN => clk_apv, - RESET_IN => global_sync_reset, - -- ADC clock domain signals - ADC_CLK_IN => adc0_lclk, - ADC_CE_IN => adc0_ce, - ADC_DATA_VALID_IN => adc0_valid, - ADC_DATA_7_IN => adc_raw_data(7), - ADC_DATA_6_IN => adc_raw_data(6), - ADC_DATA_5_IN => adc_raw_data(5), - ADC_DATA_4_IN => adc_raw_data(4), - ADC_DATA_3_IN => adc_raw_data(3), - ADC_DATA_2_IN => adc_raw_data(2), - ADC_DATA_1_IN => adc_raw_data(1), - ADC_DATA_0_IN => adc_raw_data(0), - LEVEL_WR_OUT => open, - -- APV clock domain signals - APV_DATA_7_OUT => adc_data(7), - APV_DATA_6_OUT => adc_data(6), - APV_DATA_5_OUT => adc_data(5), - APV_DATA_4_OUT => adc_data(4), - APV_DATA_3_OUT => adc_data(3), - APV_DATA_2_OUT => adc_data(2), - APV_DATA_1_OUT => adc_data(1), - APV_DATA_0_OUT => adc_data(0), - APV_DATA_VALID_OUT => open, - LEVEL_RD_OUT => open, - -- Debug signals - DEBUG_OUT => open -); - - ----------------------------------------- --- ADC0 test data multiplexer -- ----------------------------------------- -THE_ADC_0_SELECT: adc_channel_select -port map( - RESET_IN => reset_by_trb, - ADC_CLK_IN => clk_apv, - ADC_SEL_IN => adc0_select, - ADC_7_IN => adc_data(7), - ADC_6_IN => adc_data(6), - ADC_5_IN => adc_data(5), - ADC_4_IN => adc_data(4), - ADC_3_IN => adc_data(3), - ADC_2_IN => adc_data(2), - ADC_1_IN => adc_data(1), - ADC_0_IN => adc_data(0), - ADC_CH_OUT => adc0_testdata, - DEBUG_OUT => open -); - - ----------------------------------------- --- Trigger handler (APV specific) -- ----------------------------------------- -THE_APV_TRGCTRL: apv_trgctrl -port map( - CLK_IN => sysclk, - RESET_IN => global_sync_reset, - CLK_APV_IN => clk_apv, - -- Triggers - SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse - TIME_TRG_IN => ext_in, -- external trigger inputs - TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers - STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers. - TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint - SECTOR_IN => bp_sector_qq(2 downto 0), - -- slow control settings - TRG_MAX_OUT => maximum_trg, - TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control - TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control - TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control - TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control - TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control - TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control - TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control - TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control - TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control - -- TRB LVL1 signals - TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint - TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint - TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint - TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint - TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint - TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger - TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint - TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter - TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter - TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value - -- EDS signals - EDS_DATA_OUT => eds_data, -- to ped_corr_stage - EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage - EDS_DONE_IN => eds_done, -- from ped_corr_stage - EDS_FULL_OUT => eds_buf_full, - EDS_LEVEL_OUT => eds_buf_level, - FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock) - -- APV signals - APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock) - APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock) - DEBUG_OUT => trgctrl_debug -); - - ----------------------------------------- --- ADC signals -- ----------------------------------------- -adc1_rst <= adc1_reset; -adc1_pd <= adc1_powerdown; - -THE_ADC1CLK_OUT: ODDRXC -port map( - DA => '1', - DB => '0', - CLK => clk_adc, - RST => '0', - Q => adc1_clk -); - -adc0_rst <= adc0_reset; -adc0_pd <= adc0_powerdown; - -THE_ADC0CLK_OUT: ODDRXC -port map( - DA => '1', - DB => '0', - CLK => clk_adc, - RST => '0', - Q => adc0_clk -); - - ----------------------------------------- --- APV signals -- ----------------------------------------- --- SDA line output -apv0_sda <= '0' when (apv_sda_out = '0') else 'Z'; -apv1_sda <= '0' when (apv_sda_out = '0') else 'Z'; --- SDA line input (wired OR negative logic) -apv_sda_in <= apv0_sda and apv1_sda; - --- SCL line output -apv0_scl <= '0' when (apv_scl_out = '0') else 'Z'; -apv1_scl <= '0' when (apv_scl_out = '0') else 'Z'; --- SCL line input (wired OR negative logic) -apv_scl_in <= apv0_scl and apv1_scl; - --- Reset signal with correct polarity -apv0_rst <= not apv_reset; -apv1_rst <= not apv_reset; - --- CLK and TRG signal --- CLK is shifted to meet timing constraints of APV -THE_APV0ACLK_OUT: ODDRXC -port map( - DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv0a_clk -); - -THE_APV0BCLK_OUT: ODDRXC -port map( - DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv0b_clk -); - -THE_APV1ACLK_OUT: ODDRXC -port map( - DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv1a_clk -); - -THE_APV1BCLK_OUT: ODDRXC -port map( - DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv1b_clk -); - -THE_APV0ATRG_OUT: ODDRXC -port map( - DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv0a_trg -); -THE_APV0BTRG_OUT: ODDRXC -port map( - DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv0b_trg -); -THE_APV1ATRG_OUT: ODDRXC -port map( - DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv1a_trg -); -THE_APV1BTRG_OUT: ODDRXC -port map( - DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv1b_trg -); - - ----------------------------------------- --- DIP switch input registers -- ----------------------------------------- --- switch "OFF" => '1', switch "ON" => '0'; so invert it -THE_SYNC_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - bp_module_qq <= bp_module_q; - bp_module_q <= not bp_module; - bp_sector_qq <= bp_sector_q; - bp_sector_q <= not bp_sector; - not_configured <= next_not_configured; -- status bit - fe_error <= next_fe_error; -- status bit - end if; -end process THE_SYNC_PROC; - - ----------------------------------------- --- LED drivers -- ----------------------------------------- -fpga_led_adc(1) <= not adc1_valid; -fpga_led_adc(0) <= not adc0_valid; -fpga_led(6) <= not lsm_state_bits(0); -- LED "0" -fpga_led(5) <= not lsm_state_bits(1); -- LED "1" -fpga_led(4) <= not lsm_state_bits(2); -- LED "2" -fpga_led(3) <= not lsm_state_bits(3); -- LED "3" -fpga_led_pll <= not clk40m_locked; - - ----------------------------------------- --- FPGA debug header driver -- ----------------------------------------- - --- NOT USED, USE EPIC EDITOR INSTEAD! - ------------------------------------------------------------------- --- ORIGINAL STUFF ------------------------------------------------------------------- ---debug(42 downto 39) <= (others => '0'); ----- IPU signals ---debug(38 downto 35) <= ipu_number(3 downto 0); ---debug(34) <= ipu_start_readout; ---debug(33) <= ipu_dataready; ---debug(32) <= ipu_read; ---debug(31) <= ipu_readout_finished; ----- FIFO signals ---debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage) ---debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0) ---debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs ---debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU ---debug(26) <= dhdr_buf_full; -- ipu_stage -> ----- EventDataSheet / buffer signals ---debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed ---debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks ---debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last ---debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start ---debug(21 downto 17) <= buf_data(0)(34 downto 30); ---debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full ---debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry ---debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available ---debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full ---debug(12 downto 8) <= eds_buf_level; ----- timing trigger signals ---debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived ---debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived ---debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found ---debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy ---debug(3 downto 0) <= lvl1_trg_number(3 downto 0); - - ----------------------------------------- --- "unused" pins -- ----------------------------------------- - -end adcmv3; diff --git a/design/rich_trb.vhd b/design/rich_trb.vhd index 960127c..c71d950 100755 --- a/design/rich_trb.vhd +++ b/design/rich_trb.vhd @@ -24,8 +24,8 @@ port( SD_LOS_IN : in std_logic; ONEWIRE_INOUT : inout std_logic; -- common regIO status / control registers - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG * 32 - 1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG * 32-1 downto 0); -- common control register, bit definitions like in WIKI -- status register input to regIO / control register output from regIO CONTROL_OUT : out std_logic_vector(63 downto 0); STATUS_IN : in std_logic_vector(127 downto 0); @@ -182,121 +182,240 @@ debug_x(6 downto 0) <= med_stat_debug(30 downto 24); -- Full featured HADES endpoint ------------------------------------------------------------------------------------ THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full -generic map( - USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), - INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? - REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), - REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), - BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts - REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] - REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] - --standard values for output registers - REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000", - --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS => "0000000000000001", - --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & - x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & - x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & - x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", - REGIO_USE_DAT_PORT => c_YES, - REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register! - REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", - REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - REGIO_COMPILE_VERSION => x"0003", - REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature - REGIO_USE_1WIRE_INTERFACE => c_YES, - TIMING_TRIGGER_RAW => c_YES, - CLOCK_FREQUENCY => 100 -) -port map( - CLK => SYSCLK_IN, - RESET => RESET_IN, - CLK_EN => clk_en, - -- Media direction port - MED_DATAREADY_OUT => med_dataready_out_int, - MED_DATA_OUT => med_data_out_int, - MED_PACKET_NUM_OUT => med_packet_num_out_int, - MED_READ_IN => med_read_in_int, - MED_DATAREADY_IN => med_dataready_in_int, - MED_DATA_IN => med_data_in_int, - MED_PACKET_NUM_IN => med_packet_num_in_int, - MED_READ_OUT => med_read_out_int, - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - -- LVL1 trigger APL - LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received - LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received - LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) - LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT, - TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN, - LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, - LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, - LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT, - LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, - LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, - LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, - LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint - -- IPU Port - IPU_NUMBER_OUT => IPU_NUMBER_OUT, - IPU_READOUT_TYPE_OUT => open, -- 4bit readout type - IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, - IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, - IPU_DATA_IN => IPU_DATA_IN, - IPU_DATAREADY_IN => IPU_DATAREADY_IN, - IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN, - IPU_READ_OUT => IPU_READ_OUT, - IPU_LENGTH_IN => IPU_LENGTH_IN, - IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, - REGIO_REGISTERS_IN => regio_stat_regs, - REGIO_REGISTERS_OUT => regio_ctrl_regs, - COMMON_STAT_REG_STROBE => open, - COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number - STAT_REG_STROBE => open, - CTRL_REG_STROBE => open, - --following ports only used when using internal data port - REGIO_ADDR_OUT => REGIO_ADDR_OUT, - REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, - REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, - REGIO_DATA_OUT => REGIO_DATA_OUT, - REGIO_DATA_IN => REGIO_DATA_IN, - REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, - REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, - REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, - REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, - REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, - --IDRAM is used if no 1-wire interface, onewire used otherwise - REGIO_IDRAM_DATA_IN => x"0000", -- not used - REGIO_IDRAM_DATA_OUT => open, -- not used - REGIO_IDRAM_ADDR_IN => "000", -- not used - REGIO_IDRAM_WR_IN => '0', -- not used - REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, - REGIO_ONEWIRE_MONITOR_IN => '1', -- not used - REGIO_ONEWIRE_MONITOR_OUT => open, -- not used - -- New stuff - GLOBAL_TIME_OUT => open, - LOCAL_TIME_OUT => open, - TIME_SINCE_LAST_TRG_OUT => open, - TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks - TIMER_TICKS_OUT(0) => open, -- us ticks - -- Status and debug - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => stat_debug_1, --open, - STAT_DEBUG_2 => open, - MED_STAT_OP => open, - CTRL_MPLEX => x"00000000", - IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open -); + generic map ( + BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts + REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register! + REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", + REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature + REGIO_USE_1WIRE_INTERFACE => c_YES, + TIMING_TRIGGER_RAW => c_YES, + CLOCK_FREQUENCY => 100 + ) + port map ( + CLK => SYSCLK_IN, + RESET => RESET_IN, + CLK_EN => clk_en, + + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out_int, + MED_DATA_OUT => med_data_out_int, + MED_PACKET_NUM_OUT => med_packet_num_out_int, + MED_READ_IN => med_read_in_int, + MED_DATAREADY_IN => med_dataready_in_int, + MED_DATA_IN => med_data_in_int, + MED_PACKET_NUM_IN => med_packet_num_in_int, + MED_READ_OUT => med_read_out_int, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN => open, + LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT, + LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received + LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received + LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, + LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, + LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT, + LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, + LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => open, + TRG_TIMEOUT_DETECTED_OUT => open, + TRG_SPURIOUS_TRG_OUT => open, + TRG_MISSING_TMG_TRG_OUT => open, + TRG_SPIKE_DETECTED_OUT => open, + TRG_LONG_TRG_OUT => open, + + -- IPU Port + IPU_NUMBER_OUT => IPU_NUMBER_OUT, + IPU_READOUT_TYPE_OUT => open, -- 4bit readout type + IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, + IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, + IPU_DATA_IN => IPU_DATA_IN, + IPU_DATAREADY_IN => IPU_DATAREADY_IN, + IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN, + IPU_READ_OUT => IPU_READ_OUT, + IPU_LENGTH_IN => IPU_LENGTH_IN, + IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, + + REGIO_COMMON_STAT_REG_IN => open, + REGIO_COMMON_CTRL_REG_OUT => open, + REGIO_REGISTERS_IN => open, + REGIO_REGISTERS_OUT => open, + COMMON_STAT_REG_STROBE => open, + COMMON_CTRL_REG_STROBE => open, + STAT_REG_STROBE => open, + CTRL_REG_STROBE => open, + + --following ports only used when using internal data port + REGIO_ADDR_OUT => REGIO_ADDR_OUT, + REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, + REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, + REGIO_DATA_OUT => REGIO_DATA_OUT, + REGIO_DATA_IN => REGIO_DATA_IN, + REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, + REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, + REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, + REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, + REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, + + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN => x"0000", -- not used + REGIO_IDRAM_DATA_OUT => open, -- not used + REGIO_IDRAM_ADDR_IN => "000", -- not used + REGIO_IDRAM_WR_IN => '0', -- not used + REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, + REGIO_ONEWIRE_MONITOR_IN => '1', -- not used + REGIO_ONEWIRE_MONITOR_OUT => open, -- not used + REGIO_VAR_ENDPOINT_ID => open, -- not used + MY_ADDRESS_OUT => open, + + -- New stuff + GLOBAL_TIME_OUT => open, + LOCAL_TIME_OUT => open, + TIME_SINCE_LAST_TRG_OUT => open, + TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks + TIMER_TICKS_OUT(0) => open, -- us ticks + + -- Status and debug + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => stat_debug_1, + STAT_DEBUG_2 => open, + MED_STAT_OP => open, + CTRL_MPLEX => x"00000000", + IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + STAT_TRIGGER_OUT => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + +-- THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full +-- generic map( +-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), +-- INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? +-- REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), +-- REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), +-- BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts +-- REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] +-- REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] +-- --standard values for output registers +-- REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & +-- x"00000000_00000000_00000000_00000000" & +-- x"00000000_00000000_00000000_00000000" & +-- x"00000000_00000000_00000000_00000000", +-- --set to 0 for unused ctrl registers to save resources +-- REGIO_USED_CTRL_REGS => "0000000000000001", +-- --set to 0 for each unused bit in a register +-- REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & +-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & +-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & +-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", +-- REGIO_USE_DAT_PORT => c_YES, +-- REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register! +-- REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", +-- REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", +-- REGIO_INIT_ENDPOINT_ID => x"0001", +-- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), +-- REGIO_COMPILE_VERSION => x"0003", +-- REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature +-- REGIO_USE_1WIRE_INTERFACE => c_YES, +-- TIMING_TRIGGER_RAW => c_YES, +-- CLOCK_FREQUENCY => 100 +-- ) +-- port map( +-- CLK => SYSCLK_IN, +-- RESET => RESET_IN, +-- CLK_EN => clk_en, +-- -- Media direction port +-- MED_DATAREADY_OUT => med_dataready_out_int, +-- MED_DATA_OUT => med_data_out_int, +-- MED_PACKET_NUM_OUT => med_packet_num_out_int, +-- MED_READ_IN => med_read_in_int, +-- MED_DATAREADY_IN => med_dataready_in_int, +-- MED_DATA_IN => med_data_in_int, +-- MED_PACKET_NUM_IN => med_packet_num_in_int, +-- MED_READ_OUT => med_read_out_int, +-- MED_STAT_OP_IN => med_stat_op, +-- MED_CTRL_OP_OUT => med_ctrl_op, +-- -- LVL1 trigger APL +-- LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received +-- LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received +-- LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) +-- LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT, +-- TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN, +-- LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, +-- LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, +-- LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT, +-- LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, +-- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, +-- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, +-- LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint +-- -- IPU Port +-- IPU_NUMBER_OUT => IPU_NUMBER_OUT, +-- IPU_READOUT_TYPE_OUT => open, -- 4bit readout type +-- IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, +-- IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, +-- IPU_DATA_IN => IPU_DATA_IN, +-- IPU_DATAREADY_IN => IPU_DATAREADY_IN, +-- IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN, +-- IPU_READ_OUT => IPU_READ_OUT, +-- IPU_LENGTH_IN => IPU_LENGTH_IN, +-- IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, +-- -- Slow Control Data Port +-- REGIO_COMMON_STAT_REG_IN => common_stat_reg, +-- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, +-- REGIO_REGISTERS_IN => regio_stat_regs, +-- REGIO_REGISTERS_OUT => regio_ctrl_regs, +-- COMMON_STAT_REG_STROBE => open, +-- COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number +-- STAT_REG_STROBE => open, +-- CTRL_REG_STROBE => open, +-- --following ports only used when using internal data port +-- REGIO_ADDR_OUT => REGIO_ADDR_OUT, +-- REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, +-- REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, +-- REGIO_DATA_OUT => REGIO_DATA_OUT, +-- REGIO_DATA_IN => REGIO_DATA_IN, +-- REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, +-- REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, +-- REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, +-- REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, +-- REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, +-- --IDRAM is used if no 1-wire interface, onewire used otherwise +-- REGIO_IDRAM_DATA_IN => x"0000", -- not used +-- REGIO_IDRAM_DATA_OUT => open, -- not used +-- REGIO_IDRAM_ADDR_IN => "000", -- not used +-- REGIO_IDRAM_WR_IN => '0', -- not used +-- REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, +-- REGIO_ONEWIRE_MONITOR_IN => '1', -- not used +-- REGIO_ONEWIRE_MONITOR_OUT => open, -- not used +-- -- New stuff +-- GLOBAL_TIME_OUT => open, +-- LOCAL_TIME_OUT => open, +-- TIME_SINCE_LAST_TRG_OUT => open, +-- TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks +-- TIMER_TICKS_OUT(0) => open, -- us ticks +-- -- Status and debug +-- STAT_DEBUG_IPU => open, +-- STAT_DEBUG_1 => stat_debug_1, --open, +-- STAT_DEBUG_2 => open, +-- MED_STAT_OP => open, +-- CTRL_MPLEX => x"00000000", +-- IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", +-- STAT_ONEWIRE => open, +-- STAT_ADDR_DEBUG => open +-- ); ------------------------------------------------------------------------------------ -- 10s counter diff --git a/nodelist.txt b/nodelist.txt index 8ddb65b..8b9c58d 100755 --- a/nodelist.txt +++ b/nodelist.txt @@ -1,47 +1,5 @@ -[pbs2] +[lxhadeb07] system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs1] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs3] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs4] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs5] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs6] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs7] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ - -[pbs8] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ +corenum = 4 +env = /opt/lattice/diamond/3.4_x64/bin/lin64/diamond_env +workdir = /home/hadaq/lmaier/ADCM/adcm/workdir/ diff --git a/stdout.log b/stdout.log index c217a76..9b9518a 100644 --- a/stdout.log +++ b/stdout.log @@ -1,22 +1,30 @@ -Running in Lattice mode +Starting: /opt/synplicity/I-2013.09-SP1/linux_a_64/mbin/synbatch_orig +Install: /opt/synplicity/I-2013.09-SP1 +Date: Mon Sep 7 00:19:53 2015 +Version: I-2013.09-SP1 -Starting: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase/linux_a_64/mbin/synbatch -Install: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase -Hostname: brett -Date: Fri Aug 28 15:32:35 2015 -Version: J-2014.09L +Arguments: -product synplify_premier_dp -batch adcmv3.prj +ProductType: synplify_premier_dp -Arguments: -product synplify_pro -batch adcmv3.prj -ProductType: synplify_pro +License checkout: synplifypremierdp +License: synplifypremierdp from server lxcad01.gsi.de +Licensed Vendor: All FPGA +License Option: ident -CDPL_LOGDIR: /home/lmaier/.synopsys/fpga/cdpllog +Generating DM database... + +compile_dm Completed +Return Code: 0 +Run Time:00h:00m:00s + + +log file: "/home/hadaq/lmaier/ADCM/adcm/workdir/adcmv3.srr" -log file: "/home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srr" @@ -26,40 +34,28 @@ Running adcmv3|workdir Running: Compile on adcmv3|workdir -Running: Compile Process on adcmv3|workdir +Running: Compile HDL/EDIF on adcmv3|workdir Running: Compile Input on adcmv3|workdir -Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs - +Copied /home/hadaq/lmaier/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/hadaq/lmaier/ADCM/adcm/workdir/adcmv3.srs compiler Completed Return Code: 0 -Run Time:00h:00m:19s +Run Time:00h:00m:15s -Running: Multi-srs Generator on adcmv3|workdir - -Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_s.srs - - -multi_srs_gen Completed -Return Code: 0 -Run Time:00h:00m:02s - -Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_mult.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs +Complete: Compile HDL/EDIF on adcmv3|workdir -Complete: Compile Process on adcmv3|workdir - - -Running: Pre-mapping on adcmv3|workdir +Running: Premap on adcmv3|workdir premap Completed with warnings Return Code: 1 Run Time:00h:00m:05s + Complete: Compile on adcmv3|workdir @@ -68,12 +64,10 @@ Running: Map on adcmv3|workdir Running: Map & Optimize on adcmv3|workdir -Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_m.srm to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srm - - fpga_mapper Completed with warnings Return Code: 1 -Run Time:00h:03m:47s +Run Time:00h:02m:33s + Complete: Map on adcmv3|workdir @@ -81,5 +75,9 @@ Complete: Logic Synthesis on adcmv3|workdir exit status=0 + exit status=0 + +License checkin: synplifypremierdp +