From: Michael Boehmer Date: Tue, 7 Dec 2021 13:02:24 +0000 (+0100) Subject: link establishment works now stable (TM) X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=362195c3807bb02f1ba709a7289fa6d102897102;p=trbnet.git link establishment works now stable (TM) --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 5eb1298..e621236 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -220,10 +220,14 @@ begin ------------------------------------------------- -- byte/word alignment ------------------------------------------------- - word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else - word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else - word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + word_sync_i(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else + word_sync_i(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else + word_sync_i(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else + word_sync_i(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else '1'; WORD_SYNC_OUT <= word_sync_sel; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 8f6eda7..4569313 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -89,6 +89,9 @@ architecture med_sync_control_arch of med_sync_control_RS is signal rx_serdes_rst_i : std_logic; signal rx_pcs_rst_i : std_logic; + signal word_sync_rx_i : std_logic; + signal word_sync_tx_i : std_logic; + signal is_wap_zero_i : std_logic; signal debug_tx_control_i : std_logic_vector(31 downto 0); @@ -176,7 +179,7 @@ begin RX_DATA_IN => RX_DATA_IN, RX_K_IN => RX_K_IN, - WORD_SYNC_OUT => WORD_SYNC_OUT, + WORD_SYNC_OUT => word_sync_rx_i, RX_DLM_OUT => RX_DLM_OUT, RX_DLM_WORD_OUT => RX_DLM_WORD_OUT, @@ -211,7 +214,6 @@ begin ------------------------------------------------- -- TX Data ------------------------------------------------- - THE_TX_CONTROL: tx_control_RS generic map( SIM_MODE => SIM_MODE, @@ -231,6 +233,7 @@ begin TX_K_OUT => TX_K_OUT, -- synchronous signals WORD_SYNC_IN => WORD_SYNC_IN, + WORD_SYNC_OUT => word_sync_tx_i, SEND_DLM_IN => TX_DLM_IN, SEND_DLM_WORD_IN => TX_DLM_WORD_IN, SEND_RST_IN => TX_RST_IN, @@ -249,6 +252,12 @@ begin DEBUG_TX_CONTROL <= debug_tx_control_i; + -- WordSync is taken from RX in case of SP to sync the MPs in a hub. + -- In case of a root MP it is taken from MP to sync DLM sending. + -- NB: a root MP nees WORD_SYNC_IN set to '1' for operation. + -- MB: a root MP provides WORD_SYNC_OUT for DLM transmission timing. + WORD_SYNC_OUT <= word_sync_rx_i when (IS_MODE = c_IS_SLAVE) else word_sync_tx_i; + ------------------------------------------------- -- Generate LED signals ------------------------------------------------- diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index 49c8052..ca7a759 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -74,28 +74,6 @@ component lattice_ecp3_fifo_18x16_dualport_oreg ); end component; ---component main_rx_reset_RS is --- generic( --- SIM_MODE : integer := 0; --- IS_WAP_ZERO : integer := 0; --- IS_MODE : integer := c_IS_SLAVE --- ); --- port( --- CLEAR : in std_logic; -- async reset, active high --- LOCALCLK : in std_logic; -- CDR reference clock --- TX_PLL_LOL_IN : in std_logic; -- TX_PLOL form AUX channel --- RX_CDR_LOL_IN : in std_logic; -- CDR LOL --- RX_LOS_LOW_IN : in std_logic; -- RX LOS --- WA_POSITION_IN : in std_logic_vector(3 downto 0); --- SFP_LOS_IN : in std_logic; -- SFP LOS signal --- RX_PCS_RST_CH_C_OUT : out std_logic; --- RX_SERDES_RST_CH_C_OUT : out std_logic; --- LINK_RX_READY_OUT : out std_logic; -- RX SerDes is fully operational --- MASTER_RESET_OUT : out std_logic; -- can be used as master reset if sourced from Slave port --- STATE_OUT : out std_logic_vector(3 downto 0) --- ); ---end component; - component main_tx_reset_RS is generic( SIM_MODE : integer := 0 @@ -179,6 +157,7 @@ component tx_control_RS is TX_K_OUT : out std_logic; -- to TX SerDes -- synchronous signals WORD_SYNC_IN : in std_logic; -- byte/word sync + WORD_SYNC_OUT : out std_logic; SEND_DLM_IN : in std_logic; SEND_DLM_WORD_IN : in std_logic_vector(7 downto 0); SEND_RST_IN : in std_logic; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index acde2e6..77b259c 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -28,6 +28,7 @@ entity tx_control_RS is TX_K_OUT : out std_logic; -- to TX SerDes -- synchronous signals WORD_SYNC_IN : in std_logic; -- byte/word sync + WORD_SYNC_OUT : out std_logic; -- for root CTS port SEND_DLM_IN : in std_logic; SEND_DLM_WORD_IN : in std_logic_vector(7 downto 0); SEND_RST_IN : in std_logic; @@ -46,7 +47,7 @@ end entity; architecture arch of tx_control_RS is type state_t is (IDLE, SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, - SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H); + SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H); signal current_state : state_t; signal state_bits : std_logic_vector(3 downto 0); @@ -260,66 +261,71 @@ begin current_state <= IDLE; TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; --- toggle_idle <= '1'; -- added + WORD_SYNC_OUT <= '0'; else if( rising_edge(CLK_TX) ) then TX_K_OUT <= '0'; + WORD_SYNC_OUT <= '0'; debug_sending_dlm <= '0'; debug_sending_rst <= '0'; case current_state is when SEND_IDLE_L => - TX_DATA_OUT <= K_IDLE; - TX_K_OUT <= '1'; + TX_DATA_OUT <= K_IDLE; + TX_K_OUT <= '1'; if( WORD_SYNC_IN = '1' )then - current_state <= SEND_IDLE_H; + current_state <= SEND_IDLE_H; else - current_state <= SEND_IDLE_L; + current_state <= SEND_IDLE_L; end if; when SEND_IDLE_H => + WORD_SYNC_OUT <= '1'; if( (send_steady_idle_int = '1') or (toggle_idle = '1') ) then - TX_DATA_OUT <= D_IDLE1; - toggle_idle <= send_steady_idle_int; + TX_DATA_OUT <= D_IDLE1; + toggle_idle <= send_steady_idle_int; else - TX_DATA_OUT <= D_IDLE0; - toggle_idle <= '1'; + TX_DATA_OUT <= D_IDLE0; + toggle_idle <= '1'; end if; when SEND_DATA_L => - TX_DATA_OUT <= ram_dout(7 downto 0); - load_sop <= ram_dout(16); - load_eop <= ram_dout(17); - current_state <= SEND_DATA_H; + TX_DATA_OUT <= ram_dout(7 downto 0); + load_sop <= ram_dout(16); + load_eop <= ram_dout(17); + current_state <= SEND_DATA_H; when SEND_DATA_H => - TX_DATA_OUT <= ram_dout(15 downto 8); + WORD_SYNC_OUT <= '1'; + TX_DATA_OUT <= ram_dout(15 downto 8); when SEND_DLM_L => - TX_DATA_OUT <= K_DLM; - TX_K_OUT <= '1'; - current_state <= SEND_DLM_H; - debug_sending_dlm <= '1'; + TX_DATA_OUT <= K_DLM; + TX_K_OUT <= '1'; + current_state <= SEND_DLM_H; + debug_sending_dlm <= '1'; when SEND_DLM_H => - TX_DATA_OUT <= send_dlm_word_i; + WORD_SYNC_OUT <= '1'; + TX_DATA_OUT <= send_dlm_word_i; when SEND_RST_L => - TX_DATA_OUT <= K_RST; - TX_K_OUT <= '1'; - current_state <= SEND_RST_H; - debug_sending_rst <= '1'; + TX_DATA_OUT <= K_RST; + TX_K_OUT <= '1'; + current_state <= SEND_RST_H; + debug_sending_rst <= '1'; when IDLE => - TX_DATA_OUT <= K_NULL; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_L; + TX_DATA_OUT <= K_NULL; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_L; -- used to get out of async reset when SEND_RST_H => - TX_DATA_OUT <= send_rst_word_i; + WORD_SYNC_OUT <= '1'; + TX_DATA_OUT <= send_rst_word_i; when others => - current_state <= SEND_IDLE_L; + current_state <= SEND_IDLE_L; end case; if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or @@ -382,7 +388,8 @@ send_dlm_word_i <= SEND_DLM_WORD_IN; -- end if; -- end process THE_STORE_DLM_PROC; ---Send RST message +-- Send RST message +-- UNTESTED THE_STORE_RST_PROC: process( CLK_TX, RESET ) begin if( RESET = '1' ) then