From: Cahit Date: Tue, 26 Jan 2016 08:26:46 +0000 (+0100) Subject: delayes BUS HANDLER read signal one clock cycle to match the MULTICYCLE constraint X-Git-Tag: v2.3~55 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=36f7c5ebe78a152c74042aca31ae78d1738214e6;p=tdc.git delayes BUS HANDLER read signal one clock cycle to match the MULTICYCLE constraint --- diff --git a/releases/tdc_v2.3/BusHandler_record.vhd b/releases/tdc_v2.3/BusHandler_record.vhd index ffcfb09..316bd68 100644 --- a/releases/tdc_v2.3/BusHandler_record.vhd +++ b/releases/tdc_v2.3/BusHandler_record.vhd @@ -22,10 +22,11 @@ end BusHandler_record; architecture Behavioral of BusHandler_record is --Output signals - signal rx_data : std_logic_vector(31 downto 0); - signal rx_read : std_logic; - signal rx_write : std_logic; - signal rx_addr : std_logic_vector(6 downto 0); + signal rx_data : std_logic_vector(31 downto 0); + signal rx_read : std_logic; + signal rx_read_r : std_logic; + signal rx_write : std_logic; + signal rx_addr : std_logic_vector(6 downto 0); begin @@ -40,21 +41,22 @@ begin BUS_TX.ack <= '0'; BUS_TX.unknown <= '0'; BUS_TX.nack <= '0'; + rx_read_r <= rx_read; - if rx_read = '1' then + if rx_read_r = '1' then if to_integer(unsigned(rx_addr)) > BUS_LENGTH then -- if bigger than 64 BUS_TX.unknown <= '1'; else - BUS_TX.data <= DATA_IN(to_integer(unsigned(rx_addr))); - BUS_TX.ack <= '1'; + BUS_TX.data <= DATA_IN(to_integer(unsigned(rx_addr))); + BUS_TX.ack <= '1'; end if; elsif rx_write = '1' then if to_integer(unsigned(rx_addr)) > BUS_LENGTH then -- if bigger than 64 BUS_TX.unknown <= '1'; - else + else DATA_OUT(to_integer(unsigned(rx_addr))) <= rx_data; - BUS_TX.ack <= '1'; - end if; + BUS_TX.ack <= '1'; + end if; end if; end if; end process READ_WRITE_RESPONSE;