From: Jan Michel Date: Thu, 15 Jan 2015 17:33:06 +0000 (+0100) Subject: prepared design for pulser X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=379584cfc4445526ec953b78f06f9ffbdc2d156d;p=trb3.git prepared design for pulser --- diff --git a/base/trb3_periph_pulser.lpf b/base/trb3_periph_pulser.lpf new file mode 100644 index 0000000..580a0e2 --- /dev/null +++ b/base/trb3_periph_pulser.lpf @@ -0,0 +1,232 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ; + +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25; + +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25; + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; + +################################################################# +# TDC INPUTS +################################################################# + +LOCATE COMP "OUTP_0" SITE "P1"; +LOCATE COMP "OUTP_1" SITE "T2"; +LOCATE COMP "OUTP_2" SITE "R1"; +LOCATE COMP "OUTP_3" SITE "P5"; +LOCATE COMP "OUTP_4" SITE "N5"; + + + +# LOCATE COMP "INP_0" SITE "P1"; +# LOCATE COMP "INP_1" SITE "T2"; +# LOCATE COMP "INP_2" SITE "R1"; +# LOCATE COMP "INP_3" SITE "N3"; +# LOCATE COMP "OUTP_0" SITE "P5"; +# LOCATE COMP "OUTP_1" SITE "N5"; +# LOCATE COMP "INP_6" SITE "AC2"; +# LOCATE COMP "OUTP_2" SITE "AB1"; +# LOCATE COMP "INP_8" SITE "AA1"; +# LOCATE COMP "INP_9" SITE "W7"; +# LOCATE COMP "OUTP_3" SITE "Y5"; +# LOCATE COMP "OUTP_4" SITE "V6"; +# LOCATE COMP "INP_12" SITE "H2"; +# LOCATE COMP "INP_13" SITE "K3"; +# LOCATE COMP "INP_14" SITE "H1"; +# LOCATE COMP "INP_15" SITE "M5"; +# LOCATE COMP "INP_16" SITE "AD1"; +# LOCATE COMP "INP_17" SITE "AB5"; +# LOCATE COMP "INP_18" SITE "AB3"; +# LOCATE COMP "INP_19" SITE "Y6"; +# LOCATE COMP "INP_20" SITE "AA3"; +# LOCATE COMP "INP_21" SITE "W8"; +# LOCATE COMP "INP_22" SITE "V1"; +# LOCATE COMP "INP_23" SITE "T1"; +# LOCATE COMP "INP_24" SITE "P4"; +# LOCATE COMP "INP_25" SITE "T3"; +# LOCATE COMP "INP_26" SITE "R5"; +# LOCATE COMP "INP_27" SITE "T7"; +# LOCATE COMP "INP_28" SITE "K2"; +# LOCATE COMP "INP_29" SITE "J4"; +# LOCATE COMP "INP_30" SITE "D1"; +# LOCATE COMP "INP_31" SITE "K4"; +# LOCATE COMP "INP_32" SITE "J23"; +# LOCATE COMP "INP_33" SITE "G26"; +# LOCATE COMP "INP_34" SITE "F24"; +# LOCATE COMP "INP_35" SITE "H26"; +# LOCATE COMP "INP_36" SITE "K23"; +# LOCATE COMP "INP_37" SITE "F25"; +# LOCATE COMP "INP_38" SITE "AC26"; +# LOCATE COMP "INP_39" SITE "Y19"; +# LOCATE COMP "INP_40" SITE "AB24"; +# LOCATE COMP "INP_41" SITE "Y22"; +# LOCATE COMP "INP_42" SITE "AD24"; +# LOCATE COMP "INP_43" SITE "AE25"; +# LOCATE COMP "INP_44" SITE "W23"; +# LOCATE COMP "INP_45" SITE "AA25"; +# LOCATE COMP "INP_46" SITE "AA26"; +# LOCATE COMP "INP_47" SITE "W21"; +# LOCATE COMP "INP_48" SITE "H24"; +# LOCATE COMP "INP_49" SITE "L20"; +# LOCATE COMP "INP_50" SITE "K24"; +# LOCATE COMP "INP_51" SITE "M23"; +# LOCATE COMP "INP_52" SITE "L24"; +# LOCATE COMP "INP_53" SITE "M22"; +# LOCATE COMP "INP_54" SITE "J26"; +# LOCATE COMP "INP_55" SITE "N23"; +# LOCATE COMP "INP_56" SITE "K19"; +# LOCATE COMP "INP_57" SITE "P23"; +# LOCATE COMP "INP_58" SITE "L25"; +# LOCATE COMP "INP_59" SITE "P21"; +# LOCATE COMP "INP_60" SITE "R25"; +# LOCATE COMP "INP_61" SITE "T25"; +# LOCATE COMP "INP_62" SITE "T26"; +# LOCATE COMP "INP_63" SITE "V21"; + +# DEFINE PORT GROUP "INP_group" "INP*" ; +# IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +DEFINE PORT GROUP "OUT_group" "OUT*" ; +IOBUF GROUP "OUT_group" IO_TYPE=LVCMOS25; + +################################################################# +# Additional Lines to AddOn +################################################################# + +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 + +################################################################# +# DAC SPI & Flash ROM & Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "DAC_IN_SDI" SITE "D4"; #"DQUL_6" DQSUL0_T #86 +LOCATE COMP "DAC_OUT_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82 +LOCATE COMP "DAC_OUT_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_OUT_SDO" SITE "G5"; #"DQUL_2" DQUL0_2 #78 +LOCATE COMP "DAC_OUT_CLR" SITE "U24"; #"DQLR2_6" + +DEFINE PORT GROUP "DAC_IN_group" "DAC_IN_*" ; +IOBUF GROUP "DAC_IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "DAC_OUT_group" "DAC_OUT_*" ; +IOBUF GROUP "DAC_OUT_group" IO_TYPE=LVDS25; + +IOBUF PORT "DAC_OUT_SDO" IO_TYPE=LVDS25E ; + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; diff --git a/pulser/compile_frankfurt.pl b/pulser/compile_frankfurt.pl new file mode 100755 index 0000000..14139ab --- /dev/null +++ b/pulser/compile_frankfurt.pl @@ -0,0 +1,168 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity + +my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64'; +my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; +my $synplify_path_gsi = '/opt/synplicity/I-2013.09-SP1'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +#my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; +################################################################################### + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +unless(-e 'workdir') { + print "Creating workdir\n"; + system ("mkdir workdir"); + system ("cd workdir; ../../../trb3/base/linkdesignfiles.sh; cd ..;"); + } + +#create full lpf file +system("cp ../base/trb3_periph_pulser.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +# my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +my $c="ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3/pulser; LM_LICENSE_FILE=27000\@lxcad01.gsi.de $synplify_path_gsi/bin/synplify_premier_dp -batch $TOPNAME.prj\""; + +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.ncd"); + +$c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/pulser/config.vhd b/pulser/config.vhd new file mode 100644 index 0000000..3133516 --- /dev/null +++ b/pulser/config.vhd @@ -0,0 +1,77 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F30f"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4f"; + constant ADC_SAMPLING_RATE : integer := 40; + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91007000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 2 + t(42 downto 42) := "1"; --std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1)); + return t; +end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; \ No newline at end of file diff --git a/pulser/pulserddrecp3.vhd b/pulser/pulserddrecp3.vhd new file mode 100644 index 0000000..c8d1768 --- /dev/null +++ b/pulser/pulserddrecp3.vhd @@ -0,0 +1,273 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.6 +--/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n pulserddrecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -trioddr -io_type LVDS25 -width 5 -freq_in 250 -gear 2 -clk eclk -aligned -del -1 -num_clk 2 + +-- Thu Jan 15 17:25:40 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pulserddrecp3 is + port ( + clk: in std_logic; + clkout: out std_logic; + pll_lock: out std_logic; + pll_reset: in std_logic; + reset: in std_logic; + sclk: out std_logic; + tristate: in std_logic_vector(4 downto 0); + din: in std_logic_vector(3 downto 0); + q: out std_logic_vector(4 downto 0) + ); + attribute dont_touch : boolean; + attribute dont_touch of pulserddrecp3 : entity is true; +end entity; + +architecture Structure of pulserddrecp3 is + + -- internal signal declarations + signal buf_clkout: std_logic; + signal dqclk11: std_logic; + signal dqclk01: std_logic; + signal dqclk10: std_logic; + signal dqclk00: std_logic; + signal cdiv8: std_logic; + signal cdiv4: std_logic; + signal cdiv1: std_logic; + signal scuba_vhi: std_logic; + signal eclk: std_logic; + signal reset_d2: std_logic; + signal reset_d1: std_logic; + signal clkok2: std_logic; + signal clkok: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal scuba_vlo: std_logic; + signal clkintfb: std_logic; + signal buf_qo4: std_logic; + signal buf_qo3: std_logic; + signal buf_qo2: std_logic; + signal buf_qo1: std_logic; + signal tristateo: std_logic; + signal buf_qo0: std_logic; + signal sclk_t: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; + RST: in std_logic; RSTK: in std_logic; + WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; + DRPAI0: in std_logic; DFPAI3: in std_logic; + DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; + FDA2: in std_logic; FDA1: in std_logic; + FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; + CLKOK2: out std_logic; LOCK: out std_logic; + CLKINTFB: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component OFD1S3AX + port (D: in std_logic; SCLK: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component OBZ + port (I: in std_logic; T: in std_logic; O: out std_logic); + end component; + component CLKDIVB + port (CLKI: in std_logic; RST: in std_logic; + RELEASE: in std_logic; CDIV1: out std_logic; + CDIV2: out std_logic; CDIV4: out std_logic; + CDIV8: out std_logic); + end component; + component ODDRX2D + generic (MEMMODE : in String; ISI_CAL : in String); + port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic; + DB1: in std_logic; SCLK: in std_logic; + DQCLK1: in std_logic; DQCLK0: in std_logic; + Q: out std_logic); + end component; + component DQSBUFE1 + generic (DYNDEL_CNTL : in String; DYNDEL_VAL : in Integer; + DYNDEL_TYPE : in String); + port (ECLKW: in std_logic; RST: in std_logic; + DYNDELPOL: in std_logic; DYNDELAY6: in std_logic; + DYNDELAY5: in std_logic; DYNDELAY4: in std_logic; + DYNDELAY3: in std_logic; DYNDELAY2: in std_logic; + DYNDELAY1: in std_logic; DYNDELAY0: in std_logic; + DQCLK0: out std_logic; DQCLK1: out std_logic); + end component; + component ECLKSYNCA + port (ECLKI: in std_logic; STOP: in std_logic; + ECLKO: out std_logic); + end component; + attribute ODDRAPPS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute IO_TYPE : string; + attribute ODDRAPPS of Inst_ODDRX2D_0_4 : label is "ECLK_ALIGNED"; + attribute ODDRAPPS of Inst_ODDRX2D_0_3 : label is "ECLK_ALIGNED"; + attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED"; + attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED"; + attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED"; + attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "250.000000"; + attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "250.000000"; + attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "125.000000"; + attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "125.000000"; + attribute IO_TYPE of Inst1_OBZ4 : label is "LVDS25"; + attribute IO_TYPE of Inst1_OBZ3 : label is "LVDS25"; + attribute IO_TYPE of Inst1_OBZ2 : label is "LVDS25"; + attribute IO_TYPE of Inst1_OBZ1 : label is "LVDS25"; + attribute IO_TYPE of Inst1_OBZ0 : label is "LVDS25"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst_ODDRX2D_0_4: ODDRX2D + generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS") + port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), + SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo4); + + Inst_ODDRX2D_0_3: ODDRX2D + generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS") + port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), + SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo3); + + Inst_ODDRX2D_0_2: ODDRX2D + generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS") + port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), + SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo2); + + Inst_ODDRX2D_0_1: ODDRX2D + generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS") + port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), + SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1); + + Inst_ODDRX2D_0_0: ODDRX2D + generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS") + port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), + SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0); + + Inst7_DQSBUFE11: DQSBUFE1 + generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo, + DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo, + DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo, + DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo, + DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk01, DQCLK1=>dqclk11); + + Inst7_DQSBUFE10: DQSBUFE1 + generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo, + DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo, + DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo, + DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo, + DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk00, DQCLK1=>dqclk10); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst6_CLKDIVB: CLKDIVB + port map (CLKI=>eclk, RST=>reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8); + + Inst5_ECLKSYNCA: ECLKSYNCA + port map (ECLKI=>clkop, STOP=>reset_d2, ECLKO=>eclk); + + Inst4_FD1S3BX: FD1S3BX + port map (D=>reset_d1, CK=>clkok, PD=>reset, Q=>reset_d2); + + Inst3_FD1S3BX: FD1S3BX + port map (D=>reset, CK=>clkok, PD=>reset, Q=>reset_d1); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst2_EHXPLLF: EHXPLLF + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOS", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 2, CLKI_DIV=> 1, + FIN=> "125.000000") + port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>clkop, CLKOS=>clkos, + CLKOK=>clkok, CLKOK2=>clkok2, LOCK=>pll_lock, + CLKINTFB=>clkintfb); + + Inst1_OBZ4: OBZ + port map (I=>buf_qo4, T=>tristate(4), O=>q(4)); + + Inst1_OBZ3: OBZ + port map (I=>buf_qo3, T=>tristate(3), O=>q(3)); + + Inst1_OBZ2: OBZ + port map (I=>buf_qo2, T=>tristate(2), O=>q(2)); + + Inst1_OBZ1: OBZ + port map (I=>buf_qo1, T=>tristate(1), O=>q(1)); + + Inst1_OBZ0: OBZ + port map (I=>buf_qo0, T=>tristate(0), O=>q(0)); + + sclk <= sclk_t; + + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pulserddrecp3 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:OFD1S3AX use entity ecp3.OFD1S3AX(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:OBZ use entity ecp3.OBZ(V); end for; + for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; + for all:ODDRX2D use entity ecp3.ODDRX2D(V); end for; + for all:DQSBUFE1 use entity ecp3.DQSBUFE1(V); end for; + for all:ECLKSYNCA use entity ecp3.ECLKSYNCA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/pulser/trb3_periph.p2t b/pulser/trb3_periph.p2t new file mode 100644 index 0000000..019e5ed --- /dev/null +++ b/pulser/trb3_periph.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 11 +-c 1 +-e 2 +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/pulser/trb3_periph.p3t b/pulser/trb3_periph.p3t new file mode 100644 index 0000000..bf0053f --- /dev/null +++ b/pulser/trb3_periph.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "trb3_periph.log" +-o "trb3_periph.csv" +-pr "trb3_periph.prf" diff --git a/pulser/trb3_periph.prj b/pulser/trb3_periph.prj new file mode 100644 index 0000000..f4539b4 --- /dev/null +++ b/pulser/trb3_periph.prj @@ -0,0 +1,153 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd" +add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd" +add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd" +add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd" +add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" + +add_file -vhdl -lib "work" "pulserddrecp3.vhd" +add_file -vhdl -lib "work" "trb3_periph.vhd" + diff --git a/pulser/trb3_periph.vhd b/pulser/trb3_periph.vhd new file mode 100644 index 0000000..9fff1d1 --- /dev/null +++ b/pulser/trb3_periph.vhd @@ -0,0 +1,460 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.config.all; +use work.version.all; + + +entity trb3_periph is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + OUTP : out std_logic_vector(4 downto 0); + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + + + +end entity; + + +architecture trb3_periph_arch of trb3_periph is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + + signal regio_rx, buspulse_rx, busspi_rx, busmem_rx, bussed_rx : CTRLBUS_RX; + signal regio_tx, buspulse_tx, busspi_tx, busmem_tx, bussed_tx : CTRLBUS_TX; + signal readout_rx : READOUT_RX; + signal readout_tx : READOUT_TX; + + signal fee_data_finished_in : std_logic_vector(0 downto 0); + signal fee_data_write_in : std_logic_vector(0 downto 0); + signal fee_trg_release_in : std_logic_vector(0 downto 0); + signal fee_data_in : std_logic_vector(31 downto 0); + signal fee_trg_statusbits_in : std_logic_vector(31 downto 0); + + signal sed_debug : std_logic_vector(31 downto 0); + + signal din_i : std_logic_vector(3 downto 0); + signal timer : unsigned(7 downto 0) := (others => '0'); + signal tristate_i : std_logic_vector(4 downto 0); + + + component pulserddrecp3 is + port ( + clk: in std_logic; + clkout: out std_logic; + pll_lock: out std_logic; + pll_reset: in std_logic; + reset: in std_logic; + sclk: out std_logic; + tristate: in std_logic_vector(4 downto 0); + din: in std_logic_vector(3 downto 0); + q: out std_logic_vector(4 downto 0) + ); + end component; + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_PCLK_RIGHT, + RESET => '0', + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => CLK_PCLK_RIGHT, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map( + REGIO_NUM_STAT_REGS => 0, + REGIO_NUM_CTRL_REGS => 0, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"ff", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INIT_ADDRESS => INIT_ADDRESS, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 10, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**10-511, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid, + LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg, + LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg, + + LVL1_TRG_TYPE_OUT => readout_rx.trg_type, + LVL1_TRG_NUMBER_OUT => readout_rx.trg_number, + LVL1_TRG_CODE_OUT => readout_rx.trg_code, + LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information, + LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple, + TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout, + TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious, + TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing, + TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike, + + --Response from FEE + FEE_TRG_RELEASE_IN => fee_trg_release_in, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in, + FEE_DATA_IN => fee_data_in, + FEE_DATA_WRITE_IN => fee_data_write_in, + FEE_DATA_FINISHED_IN => fee_data_finished_in, + FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => (others => '0'), + REGIO_CTRL_REG_OUT => open, + REGIO_STAT_STROBE_OUT => open, + REGIO_CTRL_STROBE_OUT => open, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_RX => regio_rx, + BUS_TX => regio_tx, + + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks + + ); + + timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- + common_stat_reg <= (others => '0'); + +gen_rdo_tx : for i in 0 to 0 generate + fee_trg_release_in(i) <= readout_tx.busy_release; + fee_trg_statusbits_in(i*32+31 downto i*32) <= readout_tx.statusbits; + fee_data_in(i*32+31 downto i*32) <= readout_tx.data; + fee_data_write_in(i) <= readout_tx.data_write; + fee_data_finished_in(i) <= readout_tx.data_finished; +end generate; + + readout_tx.busy_release <= '1'; + readout_tx.data_finished<= '1'; + readout_tx.statusbits <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Pulser +--------------------------------------------------------------------------- + tristate_i <= "01010"; +--just generating some test output +timer <= timer + 1 when rising_edge(clk_125_i); +process begin + wait until rising_edge(clk_125_i); + if timer = x"01" then din_i <= x"3"; + elsif timer = x"02" then din_i <= x"f"; + elsif timer = x"03" then din_i <= x"1"; + else din_i <= x"0"; + end if; +end process; + + + THE_DDR: pulserddrecp3 + port map( + clk => CLK_GPLL_LEFT, + pll_lock => open, + pll_reset => '0', + reset => '0', + sclk => clk_125_i, + tristate => tristate_i, + din => din_i, + q => OUTP + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d500", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 2, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + REGIO_RX => regio_rx, + REGIO_TX => regio_tx, + + BUS_RX(0) => busmem_rx, --Flash + BUS_RX(1) => buspulse_rx, --Pulser + BUS_RX(2) => bussed_rx, --SED + BUS_TX(0) => busmem_tx, + BUS_TX(1) => buspulse_tx, + BUS_TX(2) => bussed_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + +THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + + BUS_ADDR_IN => busmem_rx.addr(8 downto 0), + BUS_READ_IN => busmem_rx.read, + BUS_WRITE_IN => busmem_rx.write, + BUS_DATAREADY_OUT => busmem_tx.rack, + BUS_WRITE_ACK_OUT => busmem_tx.wack, + BUS_UNKNOWN_ADDR_OUT => busmem_tx.unknown, + BUS_NO_MORE_DATA_OUT => busmem_tx.nack, + BUS_DATA_IN => busmem_rx.data, + BUS_DATA_OUT => busmem_tx.data, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_DIN, + SPI_SDI_IN => FLASH_DOUT + ); + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => open, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx, + DEBUG => sed_debug + ); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- +LED_GREEN <= not med_stat_op(9); +LED_ORANGE <= not med_stat_op(10); +LED_RED <= '1'; +LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= sed_debug(28 downto 24) & sed_debug(10 downto 0); + +end architecture; diff --git a/pulser/trb3_periph_constraints.lpf b/pulser/trb3_periph_constraints.lpf new file mode 100644 index 0000000..7b127a5 --- /dev/null +++ b/pulser/trb3_periph_constraints.lpf @@ -0,0 +1,38 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +#FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +#FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +#FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; + +################################################################# +# Locate Serdes and media interfaces +################################################################# + +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + + + +################################################################# +# Clocks +################################################################# +USE PRIMARY NET "CLK_PCLK_RIGHT_c";