From: Jan Michel Date: Wed, 22 Aug 2018 14:42:00 +0000 (+0200) Subject: adding some files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=37a2de5f88dc618bb7637620e3348ae4332fffbb;p=trb5sc.git adding some files --- 37a2de5f88dc618bb7637620e3348ae4332fffbb diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5aaed8d --- /dev/null +++ b/.gitignore @@ -0,0 +1,34 @@ +*~ +*.tcl +*.log +*.rpt +netlists +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log +workdir +workdir_* +*.bit +*.kate-swp* +*.kate-swap* +.run_manager.ini +reportview.xml +.kateproject.d +*/project/ +*/project2/ +modelsim.ini +*.mti +*.bak +work +*.wlf +*stacktrace.txt +*edn +licbug.txt +old +config_compile.pl +._Real_._Math_.vhd \ No newline at end of file diff --git a/pinout/trb5sc_basic.lpf b/pinout/trb5sc_basic.lpf new file mode 100644 index 0000000..c924c1f --- /dev/null +++ b/pinout/trb5sc_basic.lpf @@ -0,0 +1,330 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_125" SITE "AD1"; #was "OSC_CORE_125" +LOCATE COMP "CLK_200" SITE "AD32"; #was "OSC_CORE_200" +LOCATE COMP "CLK_EXT" SITE "C28"; #was "EXT_CLOCK" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "ENPIRION_CLOCK" SITE "AM31"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33; + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3"; +LOCATE COMP "TRIG_IN_RJ45" SITE "AC2"; +DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ; +IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "SPARE_0" SITE "AC3"; +LOCATE COMP "SPARE_1" SITE "AB1"; +DEFINE PORT GROUP "SPARE_group" "SPARE*" ; +IOBUF GROUP "SPARE_group" IO_TYPE=LVDS25 ; + +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_TX_DIS" SITE "AH28"; +LOCATE COMP "SFP_LOS" SITE "AK29"; +LOCATE COMP "SFP_MOD_0" SITE "AG28"; +IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +# LOCATE COMP "SFP_RATE_SEL" SITE "AG30"; +# LOCATE COMP "SFP_TX_FAULT" SITE "AH30"; +# LOCATE COMP "SFP_MOD_1" SITE "AG29"; +# LOCATE COMP "SFP_MOD_2" SITE "AJ28"; + + +################################################################# +# Frontend +################################################################# +LOCATE COMP "FE_GPIO_0" SITE "A18"; +LOCATE COMP "FE_GPIO_1" SITE "C18"; +LOCATE COMP "FE_GPIO_2" SITE "D18"; +LOCATE COMP "FE_GPIO_3" SITE "F18"; +LOCATE COMP "FE_GPIO_4" SITE "A19"; +LOCATE COMP "FE_GPIO_5" SITE "B19"; +LOCATE COMP "FE_GPIO_6" SITE "C19"; +LOCATE COMP "FE_GPIO_7" SITE "D19"; +LOCATE COMP "FE_GPIO_8" SITE "E19"; +LOCATE COMP "FE_GPIO_9" SITE "F19"; +LOCATE COMP "FE_GPIO_10" SITE "A20"; +LOCATE COMP "FE_GPIO_11" SITE "C20"; +DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; +IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +LOCATE COMP "FE_CLK_1" SITE "C5"; +LOCATE COMP "FE_CLK_2" SITE "P5"; +DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; +IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +# LOCATE COMP "FE_CLK_2_N" SITE "P4"; +# LOCATE COMP "FE_CLK_1_N" SITE "D5"; +# LOCATE COMP "FE_DIFF_0_N" SITE "T28"; +# LOCATE COMP "FE_DIFF_1_N" SITE "U28"; +# LOCATE COMP "FE_DIFF_2_N" SITE "P30"; +# LOCATE COMP "FE_DIFF_3_N" SITE "T30"; +# LOCATE COMP "FE_DIFF_4_N" SITE "P32"; +# LOCATE COMP "FE_DIFF_5_N" SITE "U30"; +# LOCATE COMP "FE_DIFF_6_N" SITE "T31"; +# LOCATE COMP "FE_DIFF_7_N" SITE "Y30"; +# LOCATE COMP "FE_DIFF_8_N" SITE "U32"; +# LOCATE COMP "FE_DIFF_9_N" SITE "W32"; +# LOCATE COMP "FE_DIFF_10_N" SITE "Y27"; +# LOCATE COMP "FE_DIFF_11_N" SITE "W28"; +# LOCATE COMP "FE_DIFF_12_N" SITE "W29"; +# LOCATE COMP "FE_DIFF_13_N" SITE "AC27"; +# LOCATE COMP "FE_DIFF_14_N" SITE "AB27"; +# LOCATE COMP "FE_DIFF_15_N" SITE "AD26"; +# LOCATE COMP "FE_DIFF_16_N" SITE "E29"; +# LOCATE COMP "FE_DIFF_17_N" SITE "F28"; +# LOCATE COMP "FE_DIFF_18_N" SITE "C31"; +# LOCATE COMP "FE_DIFF_19_N" SITE "D31"; +# LOCATE COMP "FE_DIFF_20_N" SITE "E30"; +# LOCATE COMP "FE_DIFF_21_N" SITE "D32"; +# LOCATE COMP "FE_DIFF_22_N" SITE "E32"; +# LOCATE COMP "FE_DIFF_23_N" SITE "H32"; +# LOCATE COMP "FE_DIFF_24_N" SITE "H30"; +# LOCATE COMP "FE_DIFF_25_N" SITE "K30"; +# LOCATE COMP "FE_DIFF_26_N" SITE "J32"; +# LOCATE COMP "FE_DIFF_27_N" SITE "L32"; +# LOCATE COMP "FE_DIFF_28_N" SITE "L30"; +# LOCATE COMP "FE_DIFF_29_N" SITE "K29"; +# LOCATE COMP "FE_DIFF_30_N" SITE "H28"; +# LOCATE COMP "FE_DIFF_31_N" SITE "K26"; +# LOCATE COMP "FE_DIFF_32_N" SITE "E4"; +# LOCATE COMP "FE_DIFF_33_N" SITE "F5"; +# LOCATE COMP "FE_DIFF_34_N" SITE "C2"; +# LOCATE COMP "FE_DIFF_35_N" SITE "D2"; +# LOCATE COMP "FE_DIFF_36_N" SITE "E3"; +# LOCATE COMP "FE_DIFF_37_N" SITE "D1"; +# LOCATE COMP "FE_DIFF_38_N" SITE "E1"; +# LOCATE COMP "FE_DIFF_39_N" SITE "H1"; +# LOCATE COMP "FE_DIFF_40_N" SITE "H3"; +# LOCATE COMP "FE_DIFF_41_N" SITE "K3"; +# LOCATE COMP "FE_DIFF_42_N" SITE "J1"; +# LOCATE COMP "FE_DIFF_43_N" SITE "L1"; +# LOCATE COMP "FE_DIFF_44_N" SITE "L3"; +# LOCATE COMP "FE_DIFF_45_N" SITE "K4"; +# LOCATE COMP "FE_DIFF_46_N" SITE "H5"; +# LOCATE COMP "FE_DIFF_47_N" SITE "K7"; +# LOCATE COMP "FE_DIFF_48_N" SITE "T5"; +# LOCATE COMP "FE_DIFF_49_N" SITE "U5"; +# LOCATE COMP "FE_DIFF_50_N" SITE "P3"; +# LOCATE COMP "FE_DIFF_51_N" SITE "T3"; +# LOCATE COMP "FE_DIFF_52_N" SITE "P1"; +# LOCATE COMP "FE_DIFF_53_N" SITE "U3"; +# LOCATE COMP "FE_DIFF_54_N" SITE "T2"; +# LOCATE COMP "FE_DIFF_55_N" SITE "Y3"; +# LOCATE COMP "FE_DIFF_56_N" SITE "U1"; +# LOCATE COMP "FE_DIFF_57_N" SITE "W1"; +# LOCATE COMP "FE_DIFF_58_N" SITE "Y6"; +# LOCATE COMP "FE_DIFF_59_N" SITE "W5"; +# LOCATE COMP "FE_DIFF_60_N" SITE "W4"; +# LOCATE COMP "FE_DIFF_61_N" SITE "AC6"; +# LOCATE COMP "FE_DIFF_62_N" SITE "AB6"; +# LOCATE COMP "FE_DIFF_63_N" SITE "AD7"; + +LOCATE COMP "FE_DIFF_0" SITE "R29"; +LOCATE COMP "FE_DIFF_1" SITE "T29"; +LOCATE COMP "FE_DIFF_2" SITE "P31"; +LOCATE COMP "FE_DIFF_3" SITE "R30"; +LOCATE COMP "FE_DIFF_4" SITE "N32"; +LOCATE COMP "FE_DIFF_5" SITE "U31"; +LOCATE COMP "FE_DIFF_6" SITE "R32"; +LOCATE COMP "FE_DIFF_7" SITE "W30"; +LOCATE COMP "FE_DIFF_8" SITE "T32"; +LOCATE COMP "FE_DIFF_9" SITE "V32"; +LOCATE COMP "FE_DIFF_10" SITE "Y26"; +LOCATE COMP "FE_DIFF_11" SITE "Y28"; +LOCATE COMP "FE_DIFF_12" SITE "Y29"; +LOCATE COMP "FE_DIFF_13" SITE "AB26"; +LOCATE COMP "FE_DIFF_14" SITE "AB28"; +LOCATE COMP "FE_DIFF_15" SITE "AC26"; +LOCATE COMP "FE_DIFF_16" SITE "D29"; +LOCATE COMP "FE_DIFF_17" SITE "F29"; +LOCATE COMP "FE_DIFF_18" SITE "B32"; +LOCATE COMP "FE_DIFF_19" SITE "D30"; +LOCATE COMP "FE_DIFF_20" SITE "F30"; +LOCATE COMP "FE_DIFF_21" SITE "C32"; +LOCATE COMP "FE_DIFF_22" SITE "F31"; +LOCATE COMP "FE_DIFF_23" SITE "F32"; +LOCATE COMP "FE_DIFF_24" SITE "H31"; +LOCATE COMP "FE_DIFF_25" SITE "J30"; +LOCATE COMP "FE_DIFF_26" SITE "K31"; +LOCATE COMP "FE_DIFF_27" SITE "K32"; +LOCATE COMP "FE_DIFF_28" SITE "L31"; +LOCATE COMP "FE_DIFF_29" SITE "J29"; +LOCATE COMP "FE_DIFF_30" SITE "H27"; +LOCATE COMP "FE_DIFF_31" SITE "K27"; +LOCATE COMP "FE_DIFF_32" SITE "D4"; +LOCATE COMP "FE_DIFF_33" SITE "F4"; +LOCATE COMP "FE_DIFF_34" SITE "B1"; +LOCATE COMP "FE_DIFF_35" SITE "D3"; +LOCATE COMP "FE_DIFF_36" SITE "F3"; +LOCATE COMP "FE_DIFF_37" SITE "C1"; +LOCATE COMP "FE_DIFF_38" SITE "F2"; +LOCATE COMP "FE_DIFF_39" SITE "F1"; +LOCATE COMP "FE_DIFF_40" SITE "H2"; +LOCATE COMP "FE_DIFF_41" SITE "J3"; +LOCATE COMP "FE_DIFF_42" SITE "K2"; +LOCATE COMP "FE_DIFF_43" SITE "K1"; +LOCATE COMP "FE_DIFF_44" SITE "L2"; +LOCATE COMP "FE_DIFF_45" SITE "J4"; +LOCATE COMP "FE_DIFF_46" SITE "H6"; +LOCATE COMP "FE_DIFF_47" SITE "K6"; +LOCATE COMP "FE_DIFF_48" SITE "R4"; +LOCATE COMP "FE_DIFF_49" SITE "T4"; +LOCATE COMP "FE_DIFF_50" SITE "P2"; +LOCATE COMP "FE_DIFF_51" SITE "R3"; +LOCATE COMP "FE_DIFF_52" SITE "N1"; +LOCATE COMP "FE_DIFF_53" SITE "U2"; +LOCATE COMP "FE_DIFF_54" SITE "R1"; +LOCATE COMP "FE_DIFF_55" SITE "W3"; +LOCATE COMP "FE_DIFF_56" SITE "T1"; +LOCATE COMP "FE_DIFF_57" SITE "V1"; +LOCATE COMP "FE_DIFF_58" SITE "Y7"; +LOCATE COMP "FE_DIFF_59" SITE "Y5"; +LOCATE COMP "FE_DIFF_60" SITE "Y4"; +LOCATE COMP "FE_DIFF_61" SITE "AB7"; +LOCATE COMP "FE_DIFF_62" SITE "AB5"; +LOCATE COMP "FE_DIFF_63" SITE "AC7"; +DEFINE PORT GROUP "FE_DIFF_group" "FE_DIFF*" ; +IOBUF GROUP "FE_DIFF_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Temperature, Flash & ID +################################################################# +LOCATE COMP "I2C_SDA" SITE "A11"; +LOCATE COMP "I2C_SCL" SITE "B11"; +LOCATE COMP "TMP_ALERT" SITE "C11"; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "REPROGRAM" SITE "AH1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16"; +IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ; + + +# LOCATE COMP "FLASH_HOLD" SITE "AL1"; +LOCATE COMP "FLASH_MISO" SITE "AJ2"; +LOCATE COMP "FLASH_MOSI" SITE "AK2"; +LOCATE COMP "FLASH_NCS" SITE "AJ3"; +LOCATE COMP "FLASH_SCLK" SITE "AJ1"; +# LOCATE COMP "FLASH_WP" SITE "AM2"; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; + + +LOCATE COMP "ADC_MISO" SITE "AK3"; +LOCATE COMP "ADC_MOSI" SITE "AL3"; +LOCATE COMP "ADC_NCS" SITE "AH3"; +LOCATE COMP "ADC_SCLK" SITE "AG3"; +IOBUF PORT "ADC_SCLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_NCS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MOSI" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MISO" IO_TYPE=LVTTL33 PULLMODE=UP ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_SFP_YELLOW" SITE "AG32"; +LOCATE COMP "LED_SFP_GREEN" SITE "AK30"; +LOCATE COMP "LED_SFP_RED" SITE "AH32"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_1" SITE "A26"; +LOCATE COMP "LED_2" SITE "B26"; +LOCATE COMP "LED_3" SITE "A28"; +LOCATE COMP "LED_4" SITE "A29"; +LOCATE COMP "LED_5" SITE "A30"; +LOCATE COMP "LED_6" SITE "A31"; +LOCATE COMP "LED_7" SITE "B29"; +LOCATE COMP "LED_8" SITE "B30"; +IOBUF PORT "LED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_3" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_4" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_5" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_6" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_7" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_8" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "LED_CLOCK_GREEN" SITE "AK32"; +LOCATE COMP "LED_CLOCK_RED" SITE "AJ32"; +LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30"; +LOCATE COMP "LED_TRIGGER_GREEN" SITE "AM30"; +LOCATE COMP "LED_TRIGGER_RED" SITE "AL30"; +IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVTTL33 ; + +################################################################# +# Test & Other IO +################################################################# +LOCATE COMP "TEST_1" SITE "A7"; +LOCATE COMP "TEST_2" SITE "A5"; +LOCATE COMP "TEST_3" SITE "A4"; +LOCATE COMP "TEST_4" SITE "A3"; +LOCATE COMP "TEST_5" SITE "A2"; +LOCATE COMP "TEST_6" SITE "B3"; +LOCATE COMP "TEST_7" SITE "B4"; +LOCATE COMP "TEST_8" SITE "B7"; +LOCATE COMP "TEST_9" SITE "C7"; +LOCATE COMP "TEST_10" SITE "C8"; +LOCATE COMP "TEST_11" SITE "D7"; +LOCATE COMP "TEST_12" SITE "D8"; +LOCATE COMP "TEST_13" SITE "E8"; +LOCATE COMP "TEST_14" SITE "F8"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + + +LOCATE COMP "HDR_IO_0" SITE "A23"; +LOCATE COMP "HDR_IO_1" SITE "A22"; +LOCATE COMP "HDR_IO_2" SITE "B22"; +LOCATE COMP "HDR_IO_3" SITE "A24"; +LOCATE COMP "HDR_IO_4" SITE "C23"; +LOCATE COMP "HDR_IO_5" SITE "B23"; +LOCATE COMP "HDR_IO_6" SITE "C22"; +LOCATE COMP "HDR_IO_7" SITE "C24"; +LOCATE COMP "HDR_IO_8" SITE "D23"; +LOCATE COMP "HDR_IO_9" SITE "D24"; +LOCATE COMP "HDR_IO_10" SITE "E23"; +LOCATE COMP "HDR_IO_11" SITE "D22"; +LOCATE COMP "HDR_IO_12" SITE "F23"; +LOCATE COMP "HDR_IO_13" SITE "E22"; +LOCATE COMP "HDR_IO_14" SITE "F20"; +LOCATE COMP "HDR_IO_15" SITE "F22"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +LOCATE COMP "BACK_GPIO_0" SITE "P28"; +LOCATE COMP "BACK_GPIO_1" SITE "P29"; +LOCATE COMP "BACK_GPIO_2" SITE "R27"; +LOCATE COMP "BACK_GPIO_3" SITE "T27"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; diff --git a/pinout/trb5scraw.lpf b/pinout/trb5scraw.lpf new file mode 100644 index 0000000..5941d23 --- /dev/null +++ b/pinout/trb5scraw.lpf @@ -0,0 +1,278 @@ + +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +LOCATE COMP "ADC_MISO" SITE "AK3"; +LOCATE COMP "ADC_MOSI" SITE "AL3"; +LOCATE COMP "ADC_NCS" SITE "AH3"; +LOCATE COMP "ADC_SCLK" SITE "AG3"; +LOCATE COMP "BACK_GPIO__0" SITE "P28"; +LOCATE COMP "BACK_GPIO__1" SITE "P29"; +LOCATE COMP "BACK_GPIO__2" SITE "R27"; +LOCATE COMP "BACK_GPIO__3" SITE "T27"; +LOCATE COMP "CFG_0" SITE "AM4"; +LOCATE COMP "CFG_1" SITE "AL4"; +LOCATE COMP "CFG_2" SITE "AK4"; +LOCATE COMP "DONE" SITE "AJ4"; +LOCATE COMP "ENPIRION_CLOCK" SITE "AM31"; +LOCATE COMP "EXT_CLOCK0_N" SITE "D28"; +LOCATE COMP "EXT_CLOCK0_P" SITE "C28"; +LOCATE COMP "FE_CLK_1_P" SITE "C5"; +LOCATE COMP "FE_CLK_2_P" SITE "P5"; +LOCATE COMP "FE_CLK_2_N" SITE "P4"; +LOCATE COMP "FE_CLK_1_N" SITE "D5"; +LOCATE COMP "FE_DIFF_13_P" SITE "AB26"; +LOCATE COMP "FE_DIFF_30_P" SITE "H27"; +LOCATE COMP "FE_DIFF_24_N" SITE "H30"; +LOCATE COMP "FE_DIFF_34_P" SITE "B1"; +LOCATE COMP "FE_DIFF_57_P" SITE "V1"; +LOCATE COMP "FE_DIFF_39_P" SITE "F1"; +LOCATE COMP "FE_DIFF_27_N" SITE "L32"; +LOCATE COMP "FE_DIFF_11_N" SITE "W28"; +LOCATE COMP "FE_DIFF_44_N" SITE "L3"; +LOCATE COMP "FE_DIFF_25_P" SITE "J30"; +LOCATE COMP "FE_DIFF_8_N" SITE "U32"; +LOCATE COMP "FE_DIFF_41_N" SITE "K3"; +LOCATE COMP "FE_DIFF_33_N" SITE "F5"; +LOCATE COMP "FE_DIFF_59_P" SITE "Y5"; +LOCATE COMP "FE_DIFF_0_N" SITE "T28"; +LOCATE COMP "FE_DIFF_52_N" SITE "P1"; +LOCATE COMP "FE_DIFF_63_P" SITE "AC7"; +LOCATE COMP "FE_DIFF_55_N" SITE "Y3"; +LOCATE COMP "FE_DIFF_38_P" SITE "F2"; +LOCATE COMP "FE_DIFF_9_N" SITE "W32"; +LOCATE COMP "FE_DIFF_48_N" SITE "T5"; +LOCATE COMP "FE_DIFF_15_P" SITE "AC26"; +LOCATE COMP "FE_DIFF_60_P" SITE "Y4"; +LOCATE COMP "FE_DIFF_38_N" SITE "E1"; +LOCATE COMP "FE_DIFF_63_N" SITE "AD7"; +LOCATE COMP "FE_DIFF_17_P" SITE "F29"; +LOCATE COMP "FE_DIFF_41_P" SITE "J3"; +LOCATE COMP "FE_DIFF_0_P" SITE "R29"; +LOCATE COMP "FE_DIFF_56_N" SITE "U1"; +LOCATE COMP "FE_DIFF_49_N" SITE "U5"; +LOCATE COMP "FE_DIFF_58_N" SITE "Y6"; +LOCATE COMP "FE_DIFF_45_P" SITE "J4"; +LOCATE COMP "FE_DIFF_45_N" SITE "K4"; +LOCATE COMP "FE_DIFF_58_P" SITE "Y7"; +LOCATE COMP "FE_DIFF_19_P" SITE "D30"; +LOCATE COMP "FE_DIFF_17_N" SITE "F28"; +LOCATE COMP "FE_DIFF_19_N" SITE "D31"; +LOCATE COMP "FE_DIFF_8_P" SITE "T32"; +LOCATE COMP "FE_DIFF_11_P" SITE "Y28"; +LOCATE COMP "FE_DIFF_28_P" SITE "L31"; +LOCATE COMP "FE_DIFF_7_P" SITE "W30"; +LOCATE COMP "FE_DIFF_1_N" SITE "U28"; +LOCATE COMP "FE_DIFF_37_N" SITE "D1"; +LOCATE COMP "FE_DIFF_18_N" SITE "C31"; +LOCATE COMP "FE_DIFF_4_P" SITE "N32"; +LOCATE COMP "FE_DIFF_5_P" SITE "U31"; +LOCATE COMP "FE_DIFF_21_P" SITE "C32"; +LOCATE COMP "FE_DIFF_7_N" SITE "Y30"; +LOCATE COMP "FE_DIFF_53_N" SITE "U3"; +LOCATE COMP "FE_DIFF_55_P" SITE "W3"; +LOCATE COMP "FE_DIFF_23_N" SITE "H32"; +LOCATE COMP "FE_DIFF_32_P" SITE "D4"; +LOCATE COMP "FE_DIFF_13_N" SITE "AC27"; +LOCATE COMP "FE_DIFF_47_P" SITE "K6"; +LOCATE COMP "FE_DIFF_40_N" SITE "H3"; +LOCATE COMP "FE_DIFF_46_N" SITE "H5"; +LOCATE COMP "FE_DIFF_42_P" SITE "K2"; +LOCATE COMP "FE_DIFF_28_N" SITE "L30"; +LOCATE COMP "FE_DIFF_21_N" SITE "D32"; +LOCATE COMP "FE_DIFF_50_P" SITE "P2"; +LOCATE COMP "FE_DIFF_53_P" SITE "U2"; +LOCATE COMP "FE_DIFF_25_N" SITE "K30"; +LOCATE COMP "FE_DIFF_16_N" SITE "E29"; +LOCATE COMP "FE_DIFF_54_P" SITE "R1"; +LOCATE COMP "FE_DIFF_54_N" SITE "T2"; +LOCATE COMP "FE_DIFF_61_N" SITE "AC6"; +LOCATE COMP "FE_DIFF_27_P" SITE "K32"; +LOCATE COMP "FE_DIFF_26_N" SITE "J32"; +LOCATE COMP "FE_DIFF_52_P" SITE "N1"; +LOCATE COMP "FE_DIFF_57_N" SITE "W1"; +LOCATE COMP "FE_DIFF_42_N" SITE "J1"; +LOCATE COMP "FE_DIFF_62_P" SITE "AB5"; +LOCATE COMP "FE_DIFF_22_N" SITE "E32"; +LOCATE COMP "FE_DIFF_1_P" SITE "T29"; +LOCATE COMP "FE_DIFF_14_N" SITE "AB27"; +LOCATE COMP "FE_DIFF_35_P" SITE "D3"; +LOCATE COMP "FE_DIFF_4_N" SITE "P32"; +LOCATE COMP "FE_DIFF_49_P" SITE "T4"; +LOCATE COMP "FE_DIFF_10_N" SITE "Y27"; +LOCATE COMP "FE_DIFF_35_N" SITE "D2"; +LOCATE COMP "FE_DIFF_32_N" SITE "E4"; +LOCATE COMP "FE_DIFF_26_P" SITE "K31"; +LOCATE COMP "FE_DIFF_51_P" SITE "R3"; +LOCATE COMP "FE_DIFF_6_P" SITE "R32"; +LOCATE COMP "FE_DIFF_43_N" SITE "L1"; +LOCATE COMP "FE_DIFF_18_P" SITE "B32"; +LOCATE COMP "FE_DIFF_47_N" SITE "K7"; +LOCATE COMP "FE_DIFF_10_P" SITE "Y26"; +LOCATE COMP "FE_DIFF_59_N" SITE "W5"; +LOCATE COMP "FE_DIFF_6_N" SITE "T31"; +LOCATE COMP "FE_DIFF_2_N" SITE "P30"; +LOCATE COMP "FE_DIFF_62_N" SITE "AB6"; +LOCATE COMP "FE_DIFF_12_N" SITE "W29"; +LOCATE COMP "FE_DIFF_51_N" SITE "T3"; +LOCATE COMP "FE_DIFF_43_P" SITE "K1"; +LOCATE COMP "FE_DIFF_3_N" SITE "T30"; +LOCATE COMP "FE_DIFF_61_P" SITE "AB7"; +LOCATE COMP "FE_DIFF_24_P" SITE "H31"; +LOCATE COMP "FE_DIFF_60_N" SITE "W4"; +LOCATE COMP "FE_DIFF_29_N" SITE "K29"; +LOCATE COMP "FE_DIFF_36_P" SITE "F3"; +LOCATE COMP "FE_DIFF_31_P" SITE "K27"; +LOCATE COMP "FE_DIFF_22_P" SITE "F31"; +LOCATE COMP "FE_DIFF_44_P" SITE "L2"; +LOCATE COMP "FE_DIFF_14_P" SITE "AB28"; +LOCATE COMP "FE_DIFF_5_N" SITE "U30"; +LOCATE COMP "FE_DIFF_31_N" SITE "K26"; +LOCATE COMP "FE_DIFF_56_P" SITE "T1"; +LOCATE COMP "FE_DIFF_29_P" SITE "J29"; +LOCATE COMP "FE_DIFF_20_N" SITE "E30"; +LOCATE COMP "FE_DIFF_33_P" SITE "F4"; +LOCATE COMP "FE_DIFF_37_P" SITE "C1"; +LOCATE COMP "FE_DIFF_23_P" SITE "F32"; +LOCATE COMP "FE_DIFF_36_N" SITE "E3"; +LOCATE COMP "FE_DIFF_20_P" SITE "F30"; +LOCATE COMP "FE_DIFF_9_P" SITE "V32"; +LOCATE COMP "FE_DIFF_30_N" SITE "H28"; +LOCATE COMP "FE_DIFF_2_P" SITE "P31"; +LOCATE COMP "FE_DIFF_15_N" SITE "AD26"; +LOCATE COMP "FE_DIFF_16_P" SITE "D29"; +LOCATE COMP "FE_DIFF_39_N" SITE "H1"; +LOCATE COMP "FE_DIFF_3_P" SITE "R30"; +LOCATE COMP "FE_DIFF_34_N" SITE "C2"; +LOCATE COMP "FE_DIFF_50_N" SITE "P3"; +LOCATE COMP "FE_DIFF_48_P" SITE "R4"; +LOCATE COMP "FE_DIFF_40_P" SITE "H2"; +LOCATE COMP "FE_DIFF_12_P" SITE "Y29"; +LOCATE COMP "FE_DIFF_46_P" SITE "H6"; +LOCATE COMP "FE_GPIO__0" SITE "A18"; +LOCATE COMP "FE_GPIO__1" SITE "C18"; +LOCATE COMP "FE_GPIO__2" SITE "D18"; +LOCATE COMP "FE_GPIO__3" SITE "F18"; +LOCATE COMP "FE_GPIO__4" SITE "A19"; +LOCATE COMP "FE_GPIO__5" SITE "B19"; +LOCATE COMP "FE_GPIO__6" SITE "C19"; +LOCATE COMP "FE_GPIO__7" SITE "D19"; +LOCATE COMP "FE_GPIO__8" SITE "E19"; +LOCATE COMP "FE_GPIO__9" SITE "F19"; +LOCATE COMP "FE_GPIO__10" SITE "A20"; +LOCATE COMP "FE_GPIO__11" SITE "C20"; +LOCATE COMP "FLASH_HOLD" SITE "AL1"; +LOCATE COMP "FLASH_MISO" SITE "AJ2"; +LOCATE COMP "FLASH_MOSI" SITE "AK2"; +LOCATE COMP "FLASH_NCS" SITE "AJ3"; +LOCATE COMP "FLASH_SCLK" SITE "AJ1"; +LOCATE COMP "FLASH_WP" SITE "AM2"; +LOCATE COMP "FPGA_REPROGRAM" SITE "AH1"; +LOCATE COMP "GND" SITE "AB13"; +LOCATE COMP "HDRX_BP_N" SITE "AM9"; +LOCATE COMP "HDRX_BP_P" SITE "AM8"; +LOCATE COMP "HDRX_FE1_P" SITE "AM20"; +LOCATE COMP "HDRX_FE1_N" SITE "AM21"; +LOCATE COMP "HDRX_FE0_N" SITE "AM18"; +LOCATE COMP "HDRX_FE0_P" SITE "AM17"; +LOCATE COMP "HDRX_SFP1_N" SITE "AM12"; +LOCATE COMP "HDRX_SFP1_P" SITE "AM11"; +LOCATE COMP "HDR_IO__0" SITE "A23"; +LOCATE COMP "HDR_IO__1" SITE "A22"; +LOCATE COMP "HDR_IO__2" SITE "B22"; +LOCATE COMP "HDR_IO__3" SITE "A24"; +LOCATE COMP "HDR_IO__4" SITE "C23"; +LOCATE COMP "HDR_IO__5" SITE "B23"; +LOCATE COMP "HDR_IO__6" SITE "C22"; +LOCATE COMP "HDR_IO__7" SITE "C24"; +LOCATE COMP "HDR_IO__8" SITE "D23"; +LOCATE COMP "HDR_IO__9" SITE "D24"; +LOCATE COMP "HDR_IO__10" SITE "E23"; +LOCATE COMP "HDR_IO__11" SITE "D22"; +LOCATE COMP "HDR_IO__12" SITE "F23"; +LOCATE COMP "HDR_IO__13" SITE "E22"; +LOCATE COMP "HDR_IO__14" SITE "F20"; +LOCATE COMP "HDR_IO__15" SITE "F22"; +LOCATE COMP "HDTX_BP_N" SITE "AK10"; +LOCATE COMP "HDTX_BP_P" SITE "AK9"; +LOCATE COMP "HDTX_FE0_N" SITE "AK19"; +LOCATE COMP "HDTX_FE0_P" SITE "AK18"; +LOCATE COMP "HDTX_FE1_N" SITE "AK22"; +LOCATE COMP "HDTX_FE1_P" SITE "AK21"; +LOCATE COMP "HDTX_SFP1_N" SITE "AK13"; +LOCATE COMP "HDTX_SFP1_P" SITE "AK12"; +LOCATE COMP "I2C_SDA" SITE "A11"; +LOCATE COMP "I2C_SCL" SITE "B11"; +LOCATE COMP "INITN" SITE "AG4"; +LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16"; +LOCATE COMP "JTAG_TCK" SITE "AK5"; +LOCATE COMP "JTAG_TDI" SITE "AJ5"; +LOCATE COMP "JTAG_TDO" SITE "AG5"; +LOCATE COMP "JTAG_TMS" SITE "AM5"; +LOCATE COMP "LED_1" SITE "A26"; +LOCATE COMP "LED_2" SITE "B26"; +LOCATE COMP "LED_3" SITE "A28"; +LOCATE COMP "LED_4" SITE "A29"; +LOCATE COMP "LED_5" SITE "A30"; +LOCATE COMP "LED_6" SITE "A31"; +LOCATE COMP "LED_7" SITE "B29"; +LOCATE COMP "LED_8" SITE "B30"; +LOCATE COMP "LED_CLOCK_GREEN" SITE "AK32"; +LOCATE COMP "LED_CLOCK_RED" SITE "AJ32"; +LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30"; +LOCATE COMP "LED_TRIGGER_GREEN" SITE "AM30"; +LOCATE COMP "LED_TRIGGER_RED" SITE "AL30"; +LOCATE COMP "N_7016661" SITE "AM14"; +LOCATE COMP "N_7016665" SITE "AM15"; +LOCATE COMP "N_7016713" SITE "AM23"; +LOCATE COMP "N_7016717" SITE "AM24"; +LOCATE COMP "OSC_CORE_125_P" SITE "AD1"; +LOCATE COMP "OSC_CORE_200_P" SITE "AD32"; +LOCATE COMP "OSC_CORE_125_N" SITE "AE1"; +LOCATE COMP "OSC_CORE_200_N" SITE "AE32"; +LOCATE COMP "PROGRAMN" SITE "AH4"; +LOCATE COMP "SFP1_LED_YELLOW" SITE "AG32"; +LOCATE COMP "SFP1_LED_GREEN" SITE "AK30"; +LOCATE COMP "SFP1_LED_RED" SITE "AH32"; +LOCATE COMP "SFP1_TX_DIS" SITE "AH28"; +LOCATE COMP "SFP1_LOS" SITE "AK29"; +LOCATE COMP "SFP1_RATE_SEL" SITE "AG30"; +LOCATE COMP "SFP1_MOD_0" SITE "AG28"; +LOCATE COMP "SFP1_TX_FAULT" SITE "AH30"; +LOCATE COMP "SFP1_MOD_1" SITE "AG29"; +LOCATE COMP "SFP1_MOD_2" SITE "AJ28"; +LOCATE COMP "SPARE1_P" SITE "AB1"; +LOCATE COMP "SPARE1_N" SITE "AC1"; +LOCATE COMP "SPARE0_P" SITE "AC3"; +LOCATE COMP "SPARE0_N" SITE "AB2"; +LOCATE COMP "TEST_1" SITE "A7"; +LOCATE COMP "TEST_2" SITE "A5"; +LOCATE COMP "TEST_3" SITE "A4"; +LOCATE COMP "TEST_4" SITE "A3"; +LOCATE COMP "TEST_5" SITE "A2"; +LOCATE COMP "TEST_6" SITE "B3"; +LOCATE COMP "TEST_7" SITE "B4"; +LOCATE COMP "TEST_8" SITE "B7"; +LOCATE COMP "TEST_9" SITE "C7"; +LOCATE COMP "TEST_10" SITE "C8"; +LOCATE COMP "TEST_11" SITE "D7"; +LOCATE COMP "TEST_12" SITE "D8"; +LOCATE COMP "TEST_13" SITE "E8"; +LOCATE COMP "TEST_14" SITE "F8"; +LOCATE COMP "TMP_ALERT" SITE "C11"; +LOCATE COMP "TRIG_IN_BACKPL_N" SITE "AE3"; +LOCATE COMP "TRIG_IN_BACKPL_P" SITE "AD3"; +LOCATE COMP "TRIG_IN_RJ45_N" SITE "AE2"; +LOCATE COMP "TRIG_IN_RJ45_P" SITE "AC2"; +LOCATE COMP "V1_1_CORE" SITE "AA12"; +LOCATE COMP "V1_1_SERDES" SITE "AC20"; +LOCATE COMP "V3__3" SITE "AC10"; +LOCATE COMP "V2__5" SITE "T10"; +LOCATE COMP "VCCA" SITE "AJ18"; +LOCATE COMP "VCCAUX" SITE "Y10"; +LOCATE COMP "VCCAUXA" SITE "AJ24"; +LOCATE COMP "VREF_2" SITE "J26"; +LOCATE COMP "VREF_3" SITE "V29"; +LOCATE COMP "VREF_6" SITE "V4"; +LOCATE COMP "VREF_7" SITE "J7"; diff --git a/template/compile.pl b/template/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/template/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/template/config.vhd b/template/config.vhd new file mode 100644 index 0000000..582874d --- /dev/null +++ b/template/config.vhd @@ -0,0 +1,121 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 0; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F350"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"80"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl new file mode 100644 index 0000000..339c361 --- /dev/null +++ b/template/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "dirich", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'dirich2', +par_options => '../par.p2t', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/template/par.p2t b/template/par.p2t new file mode 100644 index 0000000..2ce0381 --- /dev/null +++ b/template/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 10 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/template/tdc_release b/template/tdc_release new file mode 120000 index 0000000..887cdbb --- /dev/null +++ b/template/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3/ \ No newline at end of file diff --git a/template/trb5sc_template.lpf b/template/trb5sc_template.lpf new file mode 100644 index 0000000..ea94653 --- /dev/null +++ b/template/trb5sc_template.lpf @@ -0,0 +1,42 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLOCK_IN 200 MHz; +FREQUENCY PORT CLOCK_CAL 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C45D" 12 40; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj new file mode 100644 index 0000000..4820e35 --- /dev/null +++ b/template/trb5sc_template.prj @@ -0,0 +1,217 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_template" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_template.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + +add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" +add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + + +add_file -vhdl -lib work "./trb5sc_template.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd new file mode 100644 index 0000000..55a23df --- /dev/null +++ b/template/trb5sc_template.vhd @@ -0,0 +1,418 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_template is + port( + CLK_200 : in std_logic; --Main Oscillator + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + FE_GPIO : inout std_logic_vector(11 downto 0); + FE_CLK : out std_logic_vector( 2 downto 1); + FE_DIFF : inout std_logic_vector(63 downto 0); + + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : out std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0); + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_template is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_clk_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal timer : TIMERS; + signal hdr_io : std_logic_vector(9 downto 0); + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + + + +begin + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + +THE_CAL_PLL : entity work.pll_in125_out33 + port map( + CLKI => CLOCK_CAL, + CLKOP => clk_cal + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_NCS, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => trigger_inputs_i, + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + monitor_inputs_i <= FE_DIFF(MONITOR_INPUT_NUM-1 downto 0); + trigger_inputs_i <= FE_DIFF(TRIGGER_INPUT_NUM-1 downto 0); + + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); + lcd_data(91 downto 80) <= timer.temperature; + lcd_data(95 downto 92) <= x"0"; + lcd_data(159 downto 96) <= timer.uid; + lcd_data(191 downto 160) <= debug_tools; + lcd_data(511 downto 192) <= (others => '0'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off; + + + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_NO, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLOCK_IN, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_IN, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); + +-- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= FE_DIFF(NUM_TDC_CHANNELS-2 downto 0); + end generate; + + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + +