From: hadeshyp Date: Fri, 30 Apr 2010 10:04:18 +0000 (+0000) Subject: 30-04-10 X-Git-Tag: oldGBE~289 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=38565b7e077275b28f5c6ace91034a47af6d88b0;p=trbnet.git 30-04-10 --- diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index 438fcad..2f0a3e6 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -12,11 +12,14 @@ use work.version.all; entity trb_net16_gbe_buf is generic( - DO_SIMULATION : integer range 0 to 1 := 1 + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 ); port( CLK : in std_logic; TEST_CLK : in std_logic; -- only for simulation! + CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode RESET : in std_logic; GSR_N : in std_logic; -- Debug @@ -40,6 +43,17 @@ port( SLV_ACK_OUT : out std_logic; SLV_DATA_IN : in std_logic_vector(31 downto 0); SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; -- CTS interface CTS_NUMBER_IN : in std_logic_vector (15 downto 0); CTS_CODE_IN : in std_logic_vector (7 downto 0); @@ -209,6 +223,8 @@ port( DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 + READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 + READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 -- PacketConstructor interface PC_WR_EN_OUT : out std_logic; PC_DATA_OUT : out std_logic_vector (7 downto 0); @@ -279,6 +295,7 @@ port ( PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 -- NEW PORTS FC_WR_EN_OUT : out std_logic; FC_DATA_OUT : out std_logic_vector(7 downto 0); @@ -511,12 +528,18 @@ port ( end component; component trb_net16_med_ecp_sfp_gbe_8b is +-- gk 28.04.10 +generic ( + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); port( RESET : in std_logic; GSR_N : in std_logic; CLK_125_OUT : out std_logic; CLK_RX_OUT : out std_logic; CLK_TX_OUT : out std_logic; + CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk + CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk --SGMII connection to frame transmitter (tsmac) FT_TX_CLK_EN_OUT : out std_logic; FT_RX_CLK_EN_OUT : out std_logic; @@ -574,6 +597,35 @@ port( ); end component; +component gbe_setup is +port( + CLK : in std_logic; + RESET : in std_logic; + + -- interface to regio bus + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + + GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0); + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); + GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0); + GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); + GBE_USE_GBE_OUT : out std_logic; + GBE_USE_TRBNET_OUT : out std_logic; + GBE_USE_MULTIEVENTS_OUT : out std_logic; + GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 + GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 + GBE_DELAY_OUT : out std_logic_vector(31 downto 0) -- gk 28.04.10 +); +end component; signal ig_bsm_save : std_logic_vector(3 downto 0); signal ig_bsm_load : std_logic_vector(3 downto 0); @@ -704,14 +756,31 @@ signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); signal ip_cfg_mem_data : std_logic_vector(31 downto 0); signal ip_cfg_mem_clk : std_logic; +-- gk 22.04.10 +signal max_packet : std_logic_vector(31 downto 0); +signal use_gbe : std_logic; +signal use_trbnet : std_logic; +signal use_multievents : std_logic; +-- gk 26.04.10 +signal readout_ctr : std_logic_vector(23 downto 0); +signal readout_ctr_valid : std_logic; +signal gbe_trig_nr : std_logic_vector(31 downto 0); +-- gk 28.04.10 +signal pc_delay : std_logic_vector(31 downto 0); + begin stage_ctrl_regs <= STAGE_CTRL_REGS_IN; +-- gk 23.04.10 +LED_PACKET_SENT_OUT <= pc_ready; +LED_AN_DONE_N_OUT <= not pcs_an_complete; + +-- gk 22.04.10 moved to gbe_setup entity -- PacketConstructor fixed magic values -pc_decoding <= x"00020001"; -- !!!! swap it!!!! -pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! +--pc_decoding <= x"00020001"; -- !!!! swap it!!!! -- gk 22.04.10 +--pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -- gk 22.04.10 +--pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! -- gk 22.04.10 -- FrameConstructor fixed magic values fc_type <= x"0008"; fc_ihl_version <= x"45"; @@ -719,11 +788,42 @@ fc_tos <= x"10"; fc_ttl <= x"ff"; fc_protocol <= x"11"; +-- gk 22.04.10 new entity to set values via slow control +SETUP : gbe_setup +port map( + CLK => CLK, + RESET => RESET, + + -- gk 26.04.10 + -- interface to regio bus + BUS_ADDR_IN => BUS_ADDR_IN, + BUS_DATA_IN => BUS_DATA_IN, + BUS_DATA_OUT => BUS_DATA_OUT, + BUS_WRITE_EN_IN => BUS_WRITE_EN_IN, + BUS_READ_EN_IN => BUS_READ_EN_IN, + BUS_ACK_OUT => BUS_ACK_OUT, + + GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10 + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT => pc_event_id, + GBE_SUBEVENT_DEC_OUT => pc_decoding, + GBE_QUEUE_DEC_OUT => pc_queue_dec, + GBE_MAX_PACKET_OUT => max_packet, + GBE_MAX_FRAME_OUT => pc_max_frame_size, + GBE_USE_GBE_OUT => use_gbe, + GBE_USE_TRBNET_OUT => use_trbnet, + GBE_USE_MULTIEVENTS_OUT => use_multievents, + GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10 + GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10 + GBE_DELAY_OUT => pc_delay -- gk 28.04.10 +); + -- IP configurator: allows IP config to change for each event builder THE_IP_CONFIGURATOR: ip_configurator port map( - CLK => CLK, - RESET => RESET, + CLK => CLK, + RESET => RESET, -- configuration interface START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10 BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10 @@ -735,12 +835,12 @@ port map( DEST_MAC_OUT => fc_dest_mac, DEST_IP_OUT => fc_dest_ip, DEST_UDP_OUT => fc_dest_udp, - SRC_MAC_OUT => fc_src_mac, - SRC_IP_OUT => fc_src_ip, - SRC_UDP_OUT => fc_src_udp, - MTU_OUT => pc_max_frame_size, + SRC_MAC_OUT => fc_src_mac, + SRC_IP_OUT => fc_src_ip, + SRC_UDP_OUT => fc_src_udp, + MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10 -- Debug - DEBUG_OUT => open + DEBUG_OUT => open ); -- gk 27.03.01 @@ -769,14 +869,14 @@ port map( -- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS THE_IPU_INTERFACE: trb_net16_ipu2gbe port map( - CLK => CLK, + CLK => CLK, RESET => RESET, --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_NUMBER_IN => CTS_NUMBER_IN, CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, --Information sent to CTS --status data, equipped with DHDR CTS_DATA_OUT => cts_data, @@ -795,10 +895,12 @@ port map( START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10 BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10 CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10 - DATA_GBE_ENABLE_IN => '1', --: in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN => '0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULTI_EVT_ENABLE_IN => '0', --: in std_logic; -- enable multi event packets - MAX_MESSAGE_SIZE_IN => x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl + DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10 + DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10 + MULTI_EVT_ENABLE_IN => use_multievents, --'1', --: in std_logic; -- enable multi event packets -- gk 22.04.10 + MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10 + READOUT_CTR_IN => readout_ctr, -- gk 26.04.10 + READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10 -- PacketConstructor interface PC_WR_EN_OUT => pc_wr_en, PC_DATA_OUT => pc_data, @@ -843,7 +945,8 @@ port map( PC_EVENT_ID_IN => pc_event_id, PC_TRIG_NR_IN => pc_trig_nr, PC_QUEUE_DEC_IN => pc_queue_dec, - PC_MAX_FRAME_SIZE_IN => pc_max_frame_size, + PC_MAX_FRAME_SIZE_IN => pc_max_frame_size, + PC_DELAY_IN => pc_delay, -- gk 28.04.10 -- NEW PORTS FC_WR_EN_OUT => fc_wr_en, FC_DATA_OUT => fc_data, @@ -1019,46 +1122,102 @@ imp_gen: if (DO_SIMULATION = 0) generate rx_error => open ); - -- PHY part - PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b - port map( RESET => RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_RX_OUT => open, - CLK_TX_OUT => open, - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" - ); + serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate + -- PHY part + PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b + generic map( + USE_125MHZ_EXTCLK => 0 + ) + port map( + RESET => RESET, + GSR_N => GSR_N, + CLK_125_OUT => serdes_clk_125, + CLK_RX_OUT => open, + CLK_TX_OUT => open, + CLK_125_TX_IN => CLK_125_TX_IN, + CLK_125_RX_IN => CLK_125_RX_IN, + FT_TX_CLK_EN_OUT => mac_tx_clk_en, + FT_RX_CLK_EN_OUT => mac_rx_clk_en, + --connection to frame transmitter (tsmac) + FT_COL_OUT => mac_col, + FT_CRS_OUT => mac_crs, + FT_TXD_IN => pcs_txd, + FT_TX_EN_IN => pcs_tx_en, + FT_TX_ER_IN => pcs_tx_er, + --SFP Connection + SD_RXD_P_IN => SFP_RXD_P_IN, + SD_RXD_N_IN => SFP_RXD_N_IN, + SD_TXD_P_OUT => SFP_TXD_P_OUT, + SD_TXD_N_OUT => SFP_TXD_N_OUT, + SD_REFCLK_P_IN => SFP_REFCLK_P_IN, + SD_REFCLK_N_IN => SFP_REFCLK_N_IN, + SD_PRSNT_N_IN => SFP_PRSNT_N_IN, + SD_LOS_IN => SFP_LOS_IN, + SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff + MR_ADV_ABILITY_IN => x"0020", -- full duplex only + MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, + MR_AN_PAGE_RX_OUT => pcs_an_page_rx, + MR_AN_COMPLETE_OUT => pcs_an_complete, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_AN_ENABLE_IN => '1', -- do autonegotiation + MR_RESTART_AN_IN => MR_RESTART_IN, + -- Status and control port + STAT_OP => open, + CTRL_OP => x"0000", + STAT_DEBUG => pcs_stat_debug, --open, + CTRL_DEBUG => x"0000_0000_0000_0000" + ); + end generate serdes_intclk_gen; + + serdes_extclk_gen: if (USE_125MHZ_EXTCLK = 1) generate + -- PHY part + PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b + generic map( + USE_125MHZ_EXTCLK => 1 + ) + port map( RESET => RESET, + GSR_N => GSR_N, + CLK_125_OUT => serdes_clk_125, + CLK_RX_OUT => open, + CLK_TX_OUT => open, + CLK_125_TX_IN => '0', -- not used + CLK_125_RX_IN => '0', -- not used + FT_TX_CLK_EN_OUT => mac_tx_clk_en, + FT_RX_CLK_EN_OUT => mac_rx_clk_en, + --connection to frame transmitter (tsmac) + FT_COL_OUT => mac_col, + FT_CRS_OUT => mac_crs, + FT_TXD_IN => pcs_txd, + FT_TX_EN_IN => pcs_tx_en, + FT_TX_ER_IN => pcs_tx_er, + --SFP Connection + SD_RXD_P_IN => SFP_RXD_P_IN, + SD_RXD_N_IN => SFP_RXD_N_IN, + SD_TXD_P_OUT => SFP_TXD_P_OUT, + SD_TXD_N_OUT => SFP_TXD_N_OUT, + SD_REFCLK_P_IN => SFP_REFCLK_P_IN, + SD_REFCLK_N_IN => SFP_REFCLK_N_IN, + SD_PRSNT_N_IN => SFP_PRSNT_N_IN, + SD_LOS_IN => SFP_LOS_IN, + SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff + MR_ADV_ABILITY_IN => x"0020", -- full duplex only + MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, + MR_AN_PAGE_RX_OUT => pcs_an_page_rx, + MR_AN_COMPLETE_OUT => pcs_an_complete, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_AN_ENABLE_IN => '1', -- do autonegotiation + MR_RESTART_AN_IN => MR_RESTART_IN, + -- Status and control port + STAT_OP => open, + CTRL_OP => x"0000", + STAT_DEBUG => pcs_stat_debug, --open, + CTRL_DEBUG => x"0000_0000_0000_0000" + ); + end generate serdes_extclk_gen; stage_stat_regs(31 downto 28) <= x"d"; stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index ef7d4e2..147b936 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -27,6 +27,7 @@ port( PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP + PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 -- FrameConstructor ports FC_WR_EN_OUT : out std_logic; FC_DATA_OUT : out std_logic_vector(7 downto 0); @@ -135,7 +136,7 @@ signal sub_ctr : std_logic_vector(4 downto 0); signal my_int_ctr : integer range 0 to 3; signal my_ctr : std_logic_vector(1 downto 0); -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP); +type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); signal loadCurrentState, loadNextState: loadStates; signal load_state : std_logic_vector(3 downto 0); @@ -161,6 +162,8 @@ signal pc_padding : std_logic; -- gk 29.03.10 signal rst_after_sub_comb : std_logic; -- gk 08.04.10 signal rst_after_sub : std_logic; -- gk 08.04.10 signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 +signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 +signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 begin @@ -402,7 +405,7 @@ queueSizeProc : process(CLK) begin if rising_edge(CLK) then if (RESET = '1') or (loadCurrentState = CLEANUP) then - queue_size <= x"00000028"; -- + 8B for queue headers and 20B for termination + queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers end if; @@ -427,7 +430,7 @@ end process loadMachineProc; loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, - bytes_loaded, divide_position) + bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr) begin case loadCurrentState is when LIDLE => @@ -505,15 +508,53 @@ begin else loadNextState <= LOAD_TERM; end if; + -- gk 28.04.10 when CLEANUP => load_state <= x"9"; - loadNextState <= LIDLE; + if (PC_DELAY_IN = x"0000_0000") then + loadNextState <= LIDLE; + else + loadNextState <= DELAY; + end if; + -- gk 28.04.10 + when DELAY => + load_state <= x"a"; + if (delay_ctr = x"0000_0000") then + loadNextState <= LIDLE; + else + loadNextState <= DELAY; + end if; when others => load_state <= x"f"; loadNextState <= LIDLE; end case; end process loadMachine; +-- delay counters +-- gk 28.04.10 +DELAY_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ((RESET = '1') or (loadCurrentState = LIDLE)) then + delay_ctr <= PC_DELAY_IN; + elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then + delay_ctr <= delay_ctr - x"1"; + end if; + end if; +end process DELAY_CTR_PROC; + +-- gk 28.04.10 +TICKS_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then + ticks_ctr <= x"00"; + elsif (loadCurrentState = DELAY) then + ticks_ctr <= ticks_ctr + x"1"; + end if; + end if; +end process TICKS_CTR_PROC; + dividePositionProc : process(CLK) begin if rising_edge(CLK) then diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index 8608fa1..31db1b9 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -36,6 +36,8 @@ port( DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 + READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 + READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 -- PacketConstructor interface PC_WR_EN_OUT : out std_logic; PC_DATA_OUT : out std_logic_vector (7 downto 0); @@ -178,13 +180,13 @@ signal pc_eod_qq : std_logic; signal debug : std_logic_vector(31 downto 0); -- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; +signal bank_select : std_logic_vector(3 downto 0); +signal save_addr_comb : std_logic; +signal save_addr : std_logic; +signal addr_saved_comb : std_logic; +signal addr_saved : std_logic; +signal start_config : std_logic; +signal config_done : std_logic; signal add_sub_state : std_logic; signal add_sub_state_comb : std_logic; signal add_sub_ctr : std_logic_vector(3 downto 0); @@ -200,6 +202,9 @@ signal rst_msg_comb : std_logic; signal more_subevents : std_logic; signal data_phase2 : std_logic; signal data_phase2_comb : std_logic; +signal trig_random : std_logic_vector(7 downto 0); +signal readout_ctr : std_logic_vector(23 downto 0); +signal readout_ctr_lock : std_logic; begin @@ -208,6 +213,23 @@ begin BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 START_CONFIG_OUT <= start_config; -- gk 27.03.10 config_done <= CONFIG_DONE_IN; -- gk 29.03.10 + +-- gk 26.04.10 +READOUT_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then + readout_ctr <= READOUT_CTR_IN; + readout_ctr_lock <= '0'; + elsif ((CTS_START_READOUT_IN = '1') and (readout_ctr_lock = '0')) then + readout_ctr <= readout_ctr + x"1"; + readout_ctr_lock <= '1'; + elsif (CTS_START_READOUT_IN = '0') then + readout_ctr_lock <= '0'; + end if; + end if; +end process READOUT_CTR_PROC; + -- gk 27.03.10 bank_select_proc : process( CLK ) begin @@ -256,13 +278,13 @@ cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_I -- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped -- for GbE inside the packet constructor. -- --- Long live the Endianess! +-- Long live the Endianess! -- Sync all critical pathes THE_SYNC_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to a process + --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below sf_wr_en <= sf_wr_en_comb; ce_rem_ctr <= ce_rem_ctr_comb; sf_rd_en <= sf_rd_en_comb; @@ -611,7 +633,8 @@ begin state2 <= x"2"; if( remove_done = '1' ) then if (MULTI_EVT_ENABLE_IN = '1') then - if(actual_message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then + -- gk 29.04.10 + if((actual_message_size + pc_sub_size) < MAX_MESSAGE_SIZE_IN) then loadNextState <= CALCA; calc_pad_comb <= '1'; else @@ -768,6 +791,7 @@ begin end process LOAD_SUB_DONE_PROC; -- gk 20.04.10 +-- used only in multiple event mode MORE_SUBEVENTS_PROC : process(CLK) begin if rising_edge(CLK) then @@ -779,6 +803,19 @@ begin end if; end process MORE_SUBEVENTS_PROC; +-- gk 26.04.10 +TRIG_RANDOM_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ((RESET = '1') or (rst_regs = '1')) then + trig_random <= (others => '0'); + elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then + trig_random <= pc_data; + end if; + end if; +end process TRIG_RANDOM_PROC; + + -- Counter for stripping the unneeded parts of the data stream, and saving the important parts THE_REMOVE_CTR: process( CLK ) begin @@ -791,7 +828,7 @@ begin end if; end process THE_REMOVE_CTR; -remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt address +remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address THE_REM_DONE_SYNC: process( CLK ) begin @@ -871,15 +908,22 @@ begin end if; end process THE_READ_SIZE_PROC; +-- gk 08.04.10 +-- used only in multi event mode ACTUAL_MSG_SIZE_PROC : process(CLK) begin if(rising_edge(CLK)) then if( (RESET = '1') or (rst_msg = '1') ) then - actual_message_size <= (others => '0'); - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - actual_message_size <= actual_message_size + pc_sub_size + 4 + 8; - elsif( (calc_pad = '1') and (padding_needed = '0') ) then - actual_message_size <= actual_message_size + pc_sub_size + 8; + actual_message_size <= x"0000_0028"; -- gk 29.04.10 termination + queue headers + -- gk 28.04.10 + elsif (pc_sos = '1') then + actual_message_size <= actual_message_size + pc_sub_size + x"10"; -- gk 28.04.10 +x10 for subevent headers +-- elsif ( (read_done = '1') and (data_phase = '1') ) then +-- actual_message_size <= actual_message_size + pc_sub_size; +-- elsif( (calc_pad = '1') and (padding_needed = '1') ) then +-- actual_message_size <= actual_message_size + pc_sub_size + 4 + 8; +-- elsif( (calc_pad = '1') and (padding_needed = '0') ) then +-- actual_message_size <= actual_message_size + pc_sub_size + 8; end if; end if; end process ACTUAL_MSG_SIZE_PROC; @@ -915,7 +959,7 @@ PC_SOS_OUT <= pc_sos; PC_EOD_OUT <= pc_eod_q; PC_DATA_OUT <= pc_data_q; PC_WR_EN_OUT <= pc_wr_en_qq; -PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr; +PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; -- x"0000" & pc_trig_nr; -- gk 26.04.10 PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; PC_PADDING_OUT <= padding_needed;