From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 27 Feb 2015 13:23:11 +0000 (+0100)
Subject: statebits also to ADC clock domain
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=392d9f925be625a978762070db957f2394ffaab9;p=trb3.git

statebits also to ADC clock domain
---

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index dc8d58e..00a5876 100644
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -107,7 +107,7 @@ begin
   READOUT_TX.data_write <= RDO_write_main when rising_edge(CLK_SYS);
   READOUT_TX.data       <= RDO_data_main when rising_edge(CLK_SYS);
   readout_reset         <= CONTROL(12) when rising_edge(CLK_SYS);
-  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8));
+  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC);
 
   proc_readout : process
     variable channelselect : integer range 0 to 3;