From: hadeshyp Date: Thu, 3 May 2012 10:56:36 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~86 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=397f664e82f7d5bce868c0721dee005ddd519862;p=trbnet.git *** empty log message *** --- diff --git a/gbe_ecp2m/ipcores/serdes_ch4.ipx b/gbe_ecp2m/ipcores/serdes_ch4.ipx new file mode 100644 index 0000000..82a5965 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.ipx @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/gbe_ecp2m/ipcores/serdes_ch4.jhd b/gbe_ecp2m/ipcores/serdes_ch4.jhd new file mode 100644 index 0000000..0338a8f --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.jhd @@ -0,0 +1,7 @@ +MODULE serdes_ch4 DEFIN serdes_ch4.vhd + SUBMODULE PCSD + INSTANCE PCSD_INST + SUBMODULE VHI + INSTANCE vhi_inst + SUBMODULE VLO + INSTANCE vlo_inst diff --git a/gbe_ecp2m/ipcores/serdes_ch4.lpc b/gbe_ecp2m/ipcores/serdes_ch4.lpc new file mode 100644 index 0000000..daf6272 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.lpc @@ -0,0 +1,258 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.1 +ModuleName=serdes_ch4 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/04/2012 +Time=20:33:49 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +_mode0=DISABLED +_mode1=DISABLED +_mode2=DISABLED +_mode3=RXTX +_protocol0=G8B10B +_protocol1=G8B10B +_protocol2=G8B10B +_protocol3=GIGE +_ldr0=DISABLED +_ldr1=DISABLED +_ldr2=DISABLED +_ldr3=DISABLED +_datarange=1.25 +_pll_txsrc=INTERNAL +_refclk_mult=10X +_refclk_rate=125.0 +_tx_protocol0=DISABLED +_tx_protocol1=DISABLED +_tx_protocol2=DISABLED +_tx_protocol3=GIGE +_tx_data_rate0=FULL +_tx_data_rate1=FULL +_tx_data_rate2=FULL +_tx_data_rate3=FULL +_tx_data_width0=8 +_tx_data_width1=8 +_tx_data_width2=8 +_tx_data_width3=8 +_tx_fifo0=ENABLED +_tx_fifo1=ENABLED +_tx_fifo2=ENABLED +_tx_fifo3=ENABLED +_tx_ficlk_rate0=125.0 +_tx_ficlk_rate1=125.0 +_tx_ficlk_rate2=125.0 +_tx_ficlk_rate3=125.0 +_pll_rxsrc0=EXTERNAL +_pll_rxsrc1=EXTERNAL +_pll_rxsrc2=EXTERNAL +_pll_rxsrc3=INTERNAL +Multiplier0= +Multiplier1= +Multiplier2= +Multiplier3= +_rx_datarange0=2.5 +_rx_datarange1=2.5 +_rx_datarange2=2.5 +_rx_datarange3=1.25 +_rx_protocol0=DISABLED +_rx_protocol1=DISABLED +_rx_protocol2=DISABLED +_rx_protocol3=GIGE +_rx_data_rate0=FULL +_rx_data_rate1=FULL +_rx_data_rate2=FULL +_rx_data_rate3=FULL +_rxrefclk_rate0=250.0 +_rxrefclk_rate1=250.0 +_rxrefclk_rate2=250.0 +_rxrefclk_rate3=125.0 +_rx_data_width0=8 +_rx_data_width1=8 +_rx_data_width2=8 +_rx_data_width3=8 +_rx_fifo0=ENABLED +_rx_fifo1=ENABLED +_rx_fifo2=ENABLED +_rx_fifo3=ENABLED +_rx_ficlk_rate0=250.0 +_rx_ficlk_rate1=250.0 +_rx_ficlk_rate2=250.0 +_rx_ficlk_rate3=125.0 +_tdrv_ch0=0 +_tdrv_ch1=0 +_tdrv_ch2=0 +_tdrv_ch3=0 +_tx_pre0=DISABLED +_tx_pre1=DISABLED +_tx_pre2=DISABLED +_tx_pre3=DISABLED +_rterm_tx0=50 +_rterm_tx1=50 +_rterm_tx2=50 +_rterm_tx3=50 +_rx_eq0=DISABLED +_rx_eq1=DISABLED +_rx_eq2=DISABLED +_rx_eq3=DISABLED +_rterm_rx0=50 +_rterm_rx1=50 +_rterm_rx2=50 +_rterm_rx3=50 +_rx_dcc0=AC +_rx_dcc1=AC +_rx_dcc2=AC +_rx_dcc3=AC +_los_threshold_mode0=LOS_E +_los_threshold_mode1=LOS_E +_los_threshold_mode2=LOS_E +_los_threshold_mode3=LOS_E +_los_threshold_lo0=2 +_los_threshold_lo1=2 +_los_threshold_lo2=2 +_los_threshold_lo3=2 +_los_threshold_hi0=7 +_los_threshold_hi1=7 +_los_threshold_hi2=7 +_los_threshold_hi3=7 +_pll_term=50 +_pll_dcc=AC +_pll_lol_set=0 +_tx_sb0=DISABLED +_tx_sb1=DISABLED +_tx_sb2=DISABLED +_tx_sb3=DISABLED +_tx_8b10b0=ENABLED +_tx_8b10b1=ENABLED +_tx_8b10b2=ENABLED +_tx_8b10b3=ENABLED +_rx_sb0=DISABLED +_rx_sb1=DISABLED +_rx_sb2=DISABLED +_rx_sb3=DISABLED +_ird0=DISABLED +_ird1=DISABLED +_ird2=DISABLED +_ird3=DISABLED +_rx_8b10b0=ENABLED +_rx_8b10b1=ENABLED +_rx_8b10b2=ENABLED +_rx_8b10b3=ENABLED +_rxwa0=ENABLED +_rxwa1=ENABLED +_rxwa2=ENABLED +_rxwa3=ENABLED +_ilsm0=ENABLED +_ilsm1=ENABLED +_ilsm2=ENABLED +_ilsm3=ENABLED +_scomma0=K28P157 +_scomma1=K28P157 +_scomma2=K28P157 +_scomma3=K28P5 +_comma_a0=1100000101 +_comma_a1=1100000101 +_comma_a2=1100000101 +_comma_a3=1100000101 +_comma_b0=0011111010 +_comma_b1=0011111010 +_comma_b2=0011111010 +_comma_b3=0011111010 +_comma_m0=1111111100 +_comma_m1=1111111100 +_comma_m2=1111111100 +_comma_m3=1111111111 +_ctc0=DISABLED +_ctc1=DISABLED +_ctc2=DISABLED +_ctc3=DISABLED +_cc_match_mode0=1 +_cc_match_mode1=1 +_cc_match_mode2=1 +_cc_match_mode3=2 +_k00=00 +_k01=00 +_k02=00 +_k03=01 +_k10=00 +_k11=00 +_k12=00 +_k13=00 +_k20=01 +_k21=01 +_k22=01 +_k23=01 +_k30=01 +_k31=01 +_k32=01 +_k33=00 +_byten00=00000000 +_byten01=00000000 +_byten02=00000000 +_byten03=10111100 +_byten10=00000000 +_byten11=00000000 +_byten12=00000000 +_byten13=01010000 +_byten20=00011100 +_byten21=00011100 +_byten22=00011100 +_byten23=10111100 +_byten30=00011100 +_byten31=00011100 +_byten32=00011100 +_byten33=01010000 +_cc_min_ipg0=3 +_cc_min_ipg1=3 +_cc_min_ipg2=3 +_cc_min_ipg3=3 +_cchmark=9 +_cclmark=7 +_loopback=DISABLED +_lbtype0=DISABLED +_lbtype1=DISABLED +_lbtype2=DISABLED +_lbtype3=DISABLED +_teidle_ch0=DISABLED +_teidle_ch1=DISABLED +_teidle_ch2=DISABLED +_teidle_ch3=DISABLED +_rst_gen=DISABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal +_sci_ports=DISABLED +_sci_int_port=DISABLED +_refck2core=DISABLED +Regen=auto +PAR1=0 +PARTrace1=0 +PAR3=0 +PARTrace3=0 + +[FilesGenerated] +serdes_ch4.pp=pp +serdes_ch4.tft=tft +serdes_ch4.txt=pcs_module +serdes_ch4.sym=sym diff --git a/gbe_ecp2m/ipcores/serdes_ch4.naf b/gbe_ecp2m/ipcores/serdes_ch4.naf new file mode 100644 index 0000000..22645f6 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.naf @@ -0,0 +1,48 @@ +hdinp_ch3 i +hdinn_ch3 i +hdoutp_ch3 o +hdoutn_ch3 o +rxiclk_ch3 i +txiclk_ch3 i +rx_full_clk_ch3 o +rx_half_clk_ch3 o +tx_full_clk_ch3 o +tx_half_clk_ch3 o +fpga_rxrefclk_ch3 i +txdata_ch3[7] i +txdata_ch3[6] i +txdata_ch3[5] i +txdata_ch3[4] i +txdata_ch3[3] i +txdata_ch3[2] i +txdata_ch3[1] i +txdata_ch3[0] i +tx_k_ch3 i +xmit_ch3 i +tx_disp_correct_ch3 i +rxdata_ch3[7] o +rxdata_ch3[6] o +rxdata_ch3[5] o +rxdata_ch3[4] o +rxdata_ch3[3] o +rxdata_ch3[2] o +rxdata_ch3[1] o +rxdata_ch3[0] o +rx_k_ch3 o +rx_disp_err_ch3 o +rx_cv_err_ch3 o +rx_serdes_rst_ch3_c i +sb_felb_ch3_c i +sb_felb_rst_ch3_c i +tx_pcs_rst_ch3_c i +tx_pwrup_ch3_c i +rx_pcs_rst_ch3_c i +rx_pwrup_ch3_c i +rx_los_low_ch3_s o +lsm_status_ch3_s o +rx_cdr_lol_ch3_s o +fpga_txrefclk i +tx_serdes_rst_c i +tx_pll_lol_qd_s o +rst_qd_c i +serdes_rst_qd_c i diff --git a/gbe_ecp2m/ipcores/serdes_ch4.pp b/gbe_ecp2m/ipcores/serdes_ch4.pp new file mode 100644 index 0000000..76f371d --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.pp @@ -0,0 +1,191 @@ +#define _device_name "LFE3-150EA" +#define _ch0_pll_rxsrc "REFCLK_EXT" +#define _ch0_mode "DISABLED" +#define _ch0_protocol "G8B10B" +#define _ch0_ldr "DISABLED" +#define _ch0_tx_data_rate "FULL" +#define _ch0_tx_data_width "8" +#define _ch0_tx_fifo "ENABLED" +#define _ch0_tx_ficlk_rate 125.0 +#define _ch0_rx_datarange "MEDHIGH" +#define _ch0_rx_data_rate "FULL" +#define _ch0_rxrefclk_rate "250.0" +#define _ch0_rx_data_width "8" +#define _ch0_rx_fifo "ENABLED" +#define _ch0_rx_ficlk_rate 250.0 +#define _ch0_tdrv "0" +#define _ch0_tx_pre "DISABLED" +#define _ch0_rterm_tx "50" +#define _ch0_rx_eq "DISABLED" +#define _ch0_rterm_rx "50" +#define _ch0_rx_dcc "AC" +#define _los_threshold_lo0 "2" +#define _ch0_tx_sb "DISABLED" +#define _ch0_tx_8b10b "ENABLED" +#define _ch0_rx_sb "DISABLED" +#define _ch0_ird "DISABLED" +#define _ch0_rx_8b10b "ENABLED" +#define _ch0_rxwa "ENABLED" +#define _ch0_ilsm "ENABLED" +#define _ch0_scomma "K28P157" +#define _ch0_comma_a "1100000101" +#define _ch0_comma_b "0011111010" +#define _ch0_comma_m "1111111100" +#define _ch0_ctc "DISABLED" +#define _ch0_cc_match_mode "1" +#define _ch0_byten "0000000000" +#define _ch0_byten1 "0000000000" +#define _ch0_byten2 "0100011100" +#define _ch0_byten3 "0100011100" +#define _ch0_cc_min_ipg "3" +#define _ch0_lbtype "DISABLED" +#define _ch0_teidle "DISABLED" +#define _ch0_rx_lol_port "INTERNAL" + +#define _ch1_pll_rxsrc "REFCLK_EXT" +#define _ch1_mode "DISABLED" +#define _ch1_protocol "G8B10B" +#define _ch1_ldr "DISABLED" +#define _ch1_tx_data_rate "FULL" +#define _ch1_tx_data_width "8" +#define _ch1_tx_fifo "ENABLED" +#define _ch1_tx_ficlk_rate 125.0 +#define _ch1_rx_datarange "MEDHIGH" +#define _ch1_rx_data_rate "FULL" +#define _ch1_rxrefclk_rate "250.0" +#define _ch1_rx_data_width "8" +#define _ch1_rx_fifo "ENABLED" +#define _ch1_rx_ficlk_rate 250.0 +#define _ch1_tdrv "0" +#define _ch1_tx_pre "DISABLED" +#define _ch1_rterm_tx "50" +#define _ch1_rx_eq "DISABLED" +#define _ch1_rterm_rx "50" +#define _ch1_rx_dcc "AC" +#define _los_threshold_lo1 "2" +#define _ch1_tx_sb "DISABLED" +#define _ch1_tx_8b10b "ENABLED" +#define _ch1_rx_sb "DISABLED" +#define _ch1_ird "DISABLED" +#define _ch1_rx_8b10b "ENABLED" +#define _ch1_rxwa "ENABLED" +#define _ch1_ilsm "ENABLED" +#define _ch1_scomma "K28P157" +#define _ch1_comma_a "1100000101" +#define _ch1_comma_b "0011111010" +#define _ch1_comma_m "1111111100" +#define _ch1_ctc "DISABLED" +#define _ch1_cc_match_mode "1" +#define _ch1_byten "0000000000" +#define _ch1_byten1 "0000000000" +#define _ch1_byten2 "0100011100" +#define _ch1_byten3 "0100011100" +#define _ch1_cc_min_ipg "3" +#define _ch1_lbtype "DISABLED" +#define _ch1_teidle "DISABLED" +#define _ch1_rx_lol_port "INTERNAL" + +#define _ch2_pll_rxsrc "REFCLK_EXT" +#define _ch2_mode "DISABLED" +#define _ch2_protocol "G8B10B" +#define _ch2_ldr "DISABLED" +#define _ch2_tx_data_rate "FULL" +#define _ch2_tx_data_width "8" +#define _ch2_tx_fifo "ENABLED" +#define _ch2_tx_ficlk_rate 125.0 +#define _ch2_rx_datarange "MEDHIGH" +#define _ch2_rx_data_rate "FULL" +#define _ch2_rxrefclk_rate "250.0" +#define _ch2_rx_data_width "8" +#define _ch2_rx_fifo "ENABLED" +#define _ch2_rx_ficlk_rate 250.0 +#define _ch2_tdrv "0" +#define _ch2_tx_pre "DISABLED" +#define _ch2_rterm_tx "50" +#define _ch2_rx_eq "DISABLED" +#define _ch2_rterm_rx "50" +#define _ch2_rx_dcc "AC" +#define _los_threshold_lo2 "2" +#define _ch2_tx_sb "DISABLED" +#define _ch2_tx_8b10b "ENABLED" +#define _ch2_rx_sb "DISABLED" +#define _ch2_ird "DISABLED" +#define _ch2_rx_8b10b "ENABLED" +#define _ch2_rxwa "ENABLED" +#define _ch2_ilsm "ENABLED" +#define _ch2_scomma "K28P157" +#define _ch2_comma_a "1100000101" +#define _ch2_comma_b "0011111010" +#define _ch2_comma_m "1111111100" +#define _ch2_ctc "DISABLED" +#define _ch2_cc_match_mode "1" +#define _ch2_byten "0000000000" +#define _ch2_byten1 "0000000000" +#define _ch2_byten2 "0100011100" +#define _ch2_byten3 "0100011100" +#define _ch2_cc_min_ipg "3" +#define _ch2_lbtype "DISABLED" +#define _ch2_teidle "DISABLED" +#define _ch2_rx_lol_port "INTERNAL" + +#define _ch3_pll_rxsrc "REFCLK_CORE" +#define _ch3_mode "RXTX" +#define _ch3_protocol "GIGE" +#define _ch3_ldr "DISABLED" +#define _ch3_tx_data_rate "FULL" +#define _ch3_tx_data_width "8" +#define _ch3_tx_fifo "ENABLED" +#define _ch3_tx_ficlk_rate 125.0 +#define _ch3_rx_datarange "MED" +#define _ch3_rx_data_rate "FULL" +#define _ch3_rxrefclk_rate "125.0" +#define _ch3_rx_data_width "8" +#define _ch3_rx_fifo "ENABLED" +#define _ch3_rx_ficlk_rate 125.0 +#define _ch3_tdrv "0" +#define _ch3_tx_pre "DISABLED" +#define _ch3_rterm_tx "50" +#define _ch3_rx_eq "DISABLED" +#define _ch3_rterm_rx "50" +#define _ch3_rx_dcc "AC" +#define _los_threshold_lo3 "2" +#define _ch3_tx_sb "DISABLED" +#define _ch3_tx_8b10b "ENABLED" +#define _ch3_rx_sb "DISABLED" +#define _ch3_ird "DISABLED" +#define _ch3_rx_8b10b "ENABLED" +#define _ch3_rxwa "ENABLED" +#define _ch3_ilsm "ENABLED" +#define _ch3_scomma "K28P5" +#define _ch3_comma_a "1100000101" +#define _ch3_comma_b "0011111010" +#define _ch3_comma_m "1111111111" +#define _ch3_ctc "DISABLED" +#define _ch3_cc_match_mode "2" +#define _ch3_byten "0110111100" +#define _ch3_byten1 "0001010000" +#define _ch3_byten2 "0110111100" +#define _ch3_byten3 "0001010000" +#define _ch3_cc_min_ipg "3" +#define _ch3_lbtype "DISABLED" +#define _ch3_teidle "DISABLED" +#define _ch3_rx_lol_port "INTERNAL" + +#define _datarange "MED" +#define _pll_txsrc "REFCLK_CORE" +#define _refclk_mult "10X" +#define _refclk_rate 125.0 +#define _pll_term "50" +#define _pll_dcc "AC" +#define _pll_lol_set "0" +#define _cchmark "9" +#define _cclmark "7" +#define _rst_gen "DISABLED" +#define _sci_ports "DISABLED" +#define _sci_int_port "DISABLED" +#define _refck2core "DISABLED" +#define _circuit_name serdes_ch4 +#define _lang vhdl + +#include +#include diff --git a/gbe_ecp2m/ipcores/serdes_ch4.readme b/gbe_ecp2m/ipcores/serdes_ch4.readme new file mode 100644 index 0000000..98e2a4b --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.readme @@ -0,0 +1,141 @@ + + TOOL: orcapp + DATE: 19-MAR-2008 13:11:52 + TITLE: Lattice Semiconductor Corporation + MODULE: serdes_ch4 + DESIGN: serdes_ch4 + FILENAME: serdes_ch4.readme + PROJECT: Unknown + VERSION: 2.0 + This file is auto generated by the ispLEVER + + +NOTE: This readme file has been provided to instantiate the interface +netlist. Since this template contains synthesis attributes for precision that +are crucial to the design flow, we recommend that you use this +template in your FPGA design. +entity chip is +port ( + +-- Add your FPGA design top level I/Os here + + +-- ASIC side pins for PCSD. These pins must exist for the +-- PCS core. + refclkp : in std_logic; + refclkn : in std_logic; + hdinp_ch0 : in std_logic; + hdinn_ch0 : in std_logic; + hdinp_ch1 : in std_logic; + hdinn_ch1 : in std_logic; + hdinp_ch2 : in std_logic; + hdinn_ch2 : in std_logic; + hdinp_ch3 : in std_logic; + hdinn_ch3 : in std_logic; + + hdoutp_ch0 : out std_logic; + hdoutn_ch0 : out std_logic; + hdoutp_ch1 : out std_logic; + hdoutn_ch1 : out std_logic; + hdoutp_ch2 : out std_logic; + hdoutn_ch2 : out std_logic; + hdoutp_ch3 : out std_logic; + hdoutn_ch3 : out std_logic; + + +); +end chip; + +architecture chip_arch of chip is + +-- This defines all the high-speed ports. You may have to remove +-- some of them depending on your design. +attribute nopad : string; +attribute nopad of + refclkp, refclkn, + hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, + hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, + hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, + hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; + + COMPONENT serdes_ch4 + PORT( + hdinp_ch3 : IN std_logic; + hdinn_ch3 : IN std_logic; + rxiclk_ch3 : IN std_logic; + txiclk_ch3 : IN std_logic; + fpga_rxrefclk_ch3 : IN std_logic; + txdata_ch3 : IN std_logic_vector(7 downto 0); + tx_k_ch3 : IN std_logic; + xmit_ch3 : IN std_logic; + tx_disp_correct_ch3 : IN std_logic; + rx_serdes_rst_ch3_c : IN std_logic; + sb_felb_ch3_c : IN std_logic; + sb_felb_rst_ch3_c : IN std_logic; + tx_pcs_rst_ch3_c : IN std_logic; + tx_pwrup_ch3_c : IN std_logic; + rx_pcs_rst_ch3_c : IN std_logic; + rx_pwrup_ch3_c : IN std_logic; + fpga_txrefclk : IN std_logic; + tx_serdes_rst_c : IN std_logic; + rst_qd_c : IN std_logic; + serdes_rst_qd_c : IN std_logic; + hdoutp_ch3 : OUT std_logic; + hdoutn_ch3 : OUT std_logic; + rx_full_clk_ch3 : OUT std_logic; + rx_half_clk_ch3 : OUT std_logic; + tx_full_clk_ch3 : OUT std_logic; + tx_half_clk_ch3 : OUT std_logic; + rxdata_ch3 : OUT std_logic_vector(7 downto 0); + rx_k_ch3 : OUT std_logic; + rx_disp_err_ch3 : OUT std_logic; + rx_cv_err_ch3 : OUT std_logic; + rx_los_low_ch3_s : OUT std_logic; + lsm_status_ch3_s : OUT std_logic; + rx_cdr_lol_ch3_s : OUT std_logic; + tx_pll_lol_qd_s : OUT std_logic + ); + END COMPONENT; + + + + uut: serdes_ch4 PORT MAP( + hdinp_ch3 => hdinp_ch3, + hdinn_ch3 => hdinn_ch3, + hdoutp_ch3 => hdoutp_ch3, + hdoutn_ch3 => hdoutn_ch3, + rxiclk_ch3 => rxiclk_ch3, + txiclk_ch3 => txiclk_ch3, + rx_full_clk_ch3 => rx_full_clk_ch3, + rx_half_clk_ch3 => rx_half_clk_ch3, + tx_full_clk_ch3 => tx_full_clk_ch3, + tx_half_clk_ch3 => tx_half_clk_ch3, + fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3, + txdata_ch3 => txdata_ch3, + tx_k_ch3 => tx_k_ch3, + xmit_ch3 => xmit_ch3, + tx_disp_correct_ch3 => tx_disp_correct_ch3, + rxdata_ch3 => rxdata_ch3, + rx_k_ch3 => rx_k_ch3, + rx_disp_err_ch3 => rx_disp_err_ch3, + rx_cv_err_ch3 => rx_cv_err_ch3, + rx_serdes_rst_ch3_c => rx_serdes_rst_ch3_c, + sb_felb_ch3_c => sb_felb_ch3_c, + sb_felb_rst_ch3_c => sb_felb_rst_ch3_c, + tx_pcs_rst_ch3_c => tx_pcs_rst_ch3_c, + tx_pwrup_ch3_c => tx_pwrup_ch3_c, + rx_pcs_rst_ch3_c => rx_pcs_rst_ch3_c, + rx_pwrup_ch3_c => rx_pwrup_ch3_c, + rx_los_low_ch3_s => rx_los_low_ch3_s, + lsm_status_ch3_s => lsm_status_ch3_s, + rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s, + fpga_txrefclk => fpga_txrefclk, + tx_serdes_rst_c => tx_serdes_rst_c, + tx_pll_lol_qd_s => tx_pll_lol_qd_s, + rst_qd_c => rst_qd_c, + serdes_rst_qd_c => serdes_rst_qd_c + ); + + + + diff --git a/gbe_ecp2m/ipcores/serdes_ch4.sort b/gbe_ecp2m/ipcores/serdes_ch4.sort new file mode 100644 index 0000000..9e836ba --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.sort @@ -0,0 +1 @@ +serdes_ch4.vhd diff --git a/gbe_ecp2m/ipcores/serdes_ch4.sym b/gbe_ecp2m/ipcores/serdes_ch4.sym new file mode 100644 index 0000000..9e4bc20 Binary files /dev/null and b/gbe_ecp2m/ipcores/serdes_ch4.sym differ diff --git a/gbe_ecp2m/ipcores/serdes_ch4.tft b/gbe_ecp2m/ipcores/serdes_ch4.tft new file mode 100644 index 0000000..b9db080 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.tft @@ -0,0 +1,100 @@ +@set suppresnewline=on@ + +@comment --------------------------------------------------------------------- @ +@comment Template-drive TFI generator @ +@comment Template for TFI generation. @ +@comment --------------------------------------------------------------------- @ + +@set suppresnewline=off@ + TOOL: orcapp + DATE: 19-MAR-2008 13:11:52 + TITLE: %title% + MODULE: %module% + DESIGN: %module% + FILENAME: %filename% + PROJECT: %project% + VERSION: %ver% + This file is auto generated by the ispLEVER +@set suppresnewline=on@ + +@cr@ +@cr@ + +@set sigdelim=@ + +NOTE: This readme file has been provided to instantiate the interface@cr@ +netlist. Since this template contains synthesis attributes for precision that@cr@ +are crucial to the design flow, we recommend that you use this@cr@ +template in your FPGA design.@cr@ +entity chip is@cr@ +port (@cr@ +@cr@ +-- Add your FPGA design top level I/Os here@cr@ +@cr@ +@cr@ +-- ASIC side pins for PCSD. These pins must exist for the@cr@ +-- PCS core.@cr@ + refclkp : in std_logic;@cr@ + refclkn : in std_logic;@cr@ + hdinp_ch0 : in std_logic;@cr@ + hdinn_ch0 : in std_logic;@cr@ + hdinp_ch1 : in std_logic;@cr@ + hdinn_ch1 : in std_logic;@cr@ + hdinp_ch2 : in std_logic;@cr@ + hdinn_ch2 : in std_logic;@cr@ + hdinp_ch3 : in std_logic;@cr@ + hdinn_ch3 : in std_logic;@cr@ +@cr@ + hdoutp_ch0 : out std_logic;@cr@ + hdoutn_ch0 : out std_logic;@cr@ + hdoutp_ch1 : out std_logic;@cr@ + hdoutn_ch1 : out std_logic;@cr@ + hdoutp_ch2 : out std_logic;@cr@ + hdoutn_ch2 : out std_logic;@cr@ + hdoutp_ch3 : out std_logic;@cr@ + hdoutn_ch3 : out std_logic;@cr@ +@cr@ +@cr@ +);@cr@ +end chip;@cr@ +@cr@ +architecture chip_arch of chip is@cr@ +@cr@ +-- This defines all the high-speed ports. You may have to remove@cr@ +-- some of them depending on your design.@cr@ +attribute nopad : string;@cr@ +attribute nopad of@cr@ + refclkp, refclkn,@cr@ + hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ + hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ + hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ + hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ + +@cr@ +@tab@COMPONENT %module% +@set sigdelim=@ +@cr@@tab@PORT( +@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ +@ifhas oport=*@ @comment if the design has any output ports... @ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ + @set sigdelim=;@ + @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ +@endif@ +@ifnhas oport=*@ @comment we need an "else in this language! @ + @set sigdelim=;@ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ +@endif@ +@cr@@tab@@tab@);@cr@ +@tab@END COMPONENT;@cr@@cr@ +@comment Now do a signal declaration for each port @ + +@cr@@cr@ +@comment do the component instantiation @ +@set sigdelim=,@ +@tab@uut: %module% PORT MAP( +@iterate@%port% +@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ +@cr@@tab@);@cr@@cr@ +@set suppresnewline=off@ + + diff --git a/gbe_ecp2m/ipcores/serdes_ch4.txt b/gbe_ecp2m/ipcores/serdes_ch4.txt new file mode 100644 index 0000000..6b3b65f --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.txt @@ -0,0 +1,59 @@ +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSD quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSD quad to the final design requirements. + +DEVICE_NAME "LFE3-150EA" +CH3_PROTOCOL "GIGE" +CH0_MODE "DISABLED" +CH1_MODE "DISABLED" +CH2_MODE "DISABLED" +CH3_MODE "RXTX" +CH3_CDR_SRC "REFCLK_CORE" +PLL_SRC "REFCLK_CORE" +TX_DATARATE_RANGE "MED" +CH3_RX_DATARATE_RANGE "MED" +REFCK_MULT "10X" +#REFCLK_RATE 125.0 +CH3_RX_DATA_RATE "FULL" +CH3_TX_DATA_RATE "FULL" +CH3_TX_DATA_WIDTH "8" +CH3_RX_DATA_WIDTH "8" +CH3_TX_FIFO "ENABLED" +CH3_RX_FIFO "ENABLED" +CH3_TDRV "0" +#CH3_TX_FICLK_RATE 125.0 +#CH3_RXREFCLK_RATE "125.0" +#CH3_RX_FICLK_RATE 125.0 +CH3_TX_PRE "DISABLED" +CH3_RTERM_TX "50" +CH3_RX_EQ "DISABLED" +CH3_RTERM_RX "50" +CH3_RX_DCC "AC" +CH3_LOS_THRESHOLD_LO "2" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH3_TX_SB "DISABLED" +CH3_RX_SB "DISABLED" +CH3_TX_8B10B "ENABLED" +CH3_RX_8B10B "ENABLED" +CH3_COMMA_A "1100000101" +CH3_COMMA_B "0011111010" +CH3_COMMA_M "1111111111" +CH3_RXWA "ENABLED" +CH3_ILSM "ENABLED" +CH3_CTC "DISABLED" +CH3_CC_MATCH3 "0110111100" +CH3_CC_MATCH4 "0001010000" +CH3_CC_MATCH_MODE "2" +CH3_CC_MIN_IPG "3" +CCHMARK "9" +CCLMARK "7" +CH3_SSLB "DISABLED" +CH3_SPLBPORTS "DISABLED" +CH3_PCSLBPORTS "DISABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "DISABLED" + + diff --git a/gbe_ecp2m/ipcores/serdes_ch4.vhd b/gbe_ecp2m/ipcores/serdes_ch4.vhd new file mode 100644 index 0000000..9f3f819 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4.vhd @@ -0,0 +1,2689 @@ + + + +--synopsys translate_off + +library pcsd_work; +use pcsd_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSD is +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String +-- CONFIG_FILE : String := "serdes_ch4.txt"; +-- QUAD_MODE : String := "SINGLE"; +-- CH0_CDR_SRC : String := "REFCLK_EXT"; +-- CH1_CDR_SRC : String := "REFCLK_EXT"; +-- CH2_CDR_SRC : String := "REFCLK_EXT"; +-- CH3_CDR_SRC : String := "REFCLK_CORE"; +-- PLL_SRC : String := "REFCLK_CORE" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); + +end PCSD; + +architecture PCSD_arch of PCSD is + + +component PCSD_sim +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String; + CH1_CDR_SRC : String; + CH2_CDR_SRC : String; + CH3_CDR_SRC : String; + PLL_SRC : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + +begin + +PCSD_sim_inst : PCSD_sim +generic map ( + CONFIG_FILE => CONFIG_FILE, + QUAD_MODE => QUAD_MODE, + CH0_CDR_SRC => CH0_CDR_SRC, + CH1_CDR_SRC => CH1_CDR_SRC, + CH2_CDR_SRC => CH2_CDR_SRC, + CH3_CDR_SRC => CH3_CDR_SRC, + PLL_SRC => PLL_SRC + ) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, + FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, + FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, + FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, + FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, + FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, + FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, + FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, + FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, + FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, + FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, + FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, + FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, + FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, + FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, + FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, + FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, + FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, + FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, + LDR_CORE2TX_0 => LDR_CORE2TX_0, + LDR_CORE2TX_1 => LDR_CORE2TX_1, + LDR_CORE2TX_2 => LDR_CORE2TX_2, + LDR_CORE2TX_3 => LDR_CORE2TX_3, + FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, + FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, + FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, + FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, + PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, + PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, + PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, + PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, + PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, + PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, + PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, + PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, + PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, + PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, + PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, + PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, + PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, + PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, + PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, + PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, + PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, + PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, + PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, + PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_TX_F_CLK_0 => FF_TX_F_CLK_0, + FF_TX_F_CLK_1 => FF_TX_F_CLK_1, + FF_TX_F_CLK_2 => FF_TX_F_CLK_2, + FF_TX_F_CLK_3 => FF_TX_F_CLK_3, + FF_TX_H_CLK_0 => FF_TX_H_CLK_0, + FF_TX_H_CLK_1 => FF_TX_H_CLK_1, + FF_TX_H_CLK_2 => FF_TX_H_CLK_2, + FF_TX_H_CLK_3 => FF_TX_H_CLK_3, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, + FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, + FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, + FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RLOS_HI_0 => FFS_RLOS_HI_0, + FFS_RLOS_HI_1 => FFS_RLOS_HI_1, + FFS_RLOS_HI_2 => FFS_RLOS_HI_2, + FFS_RLOS_HI_3 => FFS_RLOS_HI_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, + PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, + PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, + PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, + PCIE_RXVALID_0 => PCIE_RXVALID_0, + PCIE_RXVALID_1 => PCIE_RXVALID_1, + PCIE_RXVALID_2 => PCIE_RXVALID_2, + PCIE_RXVALID_3 => PCIE_RXVALID_3, + FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, + FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, + FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, + FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, + FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, + FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, + FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, + FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, + LDR_RX2CORE_0 => LDR_RX2CORE_0, + LDR_RX2CORE_1 => LDR_RX2CORE_1, + LDR_RX2CORE_2 => LDR_RX2CORE_2, + LDR_RX2CORE_3 => LDR_RX2CORE_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7, + REFCLK_FROM_NQ => REFCLK_FROM_NQ, + REFCLK_TO_NQ => REFCLK_TO_NQ + ); + +end PCSD_arch; + +--synopsys translate_on + + + + +--synopsys translate_off +library ECP3; +use ECP3.components.all; +--synopsys translate_on + + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_ch4 is + GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt"); + port ( +------------------ +-- CH0 -- +-- CH1 -- +-- CH2 -- +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (7 downto 0); + tx_k_ch3 : in std_logic; + xmit_ch3 : in std_logic; + tx_disp_correct_ch3 : in std_logic; + rxdata_ch3 : out std_logic_vector (7 downto 0); + rx_k_ch3 : out std_logic; + rx_disp_err_ch3 : out std_logic; + rx_cv_err_ch3 : out std_logic; + rx_serdes_rst_ch3_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pcs_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pcs_rst_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; +---- Miscillaneous ports + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end serdes_ch4; + + +architecture serdes_ch4_arch of serdes_ch4 is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; + + + +component PCSD +--synopsys translate_off +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; + attribute QUAD_MODE: string; + attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; + attribute PLL_SRC: string; + attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH3_CDR_SRC: string; + attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal refclk_from_nq : std_logic := '0'; +signal fpsc_vlo : std_logic := '0'; +signal fpsc_vhi : std_logic := '1'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); +signal tx_full_clk_ch3_sig : std_logic; + +signal refclk2fpga_sig : std_logic; +signal tx_pll_lol_qd_sig : std_logic; +signal rx_los_low_ch0_sig : std_logic; +signal rx_los_low_ch1_sig : std_logic; +signal rx_los_low_ch2_sig : std_logic; +signal rx_los_low_ch3_sig : std_logic; +signal rx_cdr_lol_ch0_sig : std_logic; +signal rx_cdr_lol_ch1_sig : std_logic; +signal rx_cdr_lol_ch2_sig : std_logic; +signal rx_cdr_lol_ch3_sig : std_logic; + + + + + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); +vhi_inst : VHI port map(Z => fpsc_vhi); + + rx_los_low_ch3_s <= rx_los_low_ch3_sig; + rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; + tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; + tx_full_clk_ch3 <= tx_full_clk_ch3_sig; + +-- pcs_quad instance +PCSD_INST : PCSD +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE, + QUAD_MODE => "SINGLE", + CH3_CDR_SRC => "REFCLK_CORE", + PLL_SRC => "REFCLK_CORE" + ) +--synopsys translate_on +port map ( + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + +----- CH0 ----- + HDOUTP0 => open, + HDOUTN0 => open, + HDINP0 => fpsc_vlo, + HDINN0 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, + PCIE_TXCOMPLIANCE_0 => fpsc_vlo, + PCIE_RXPOLARITY_0 => fpsc_vlo, + PCIE_POWERDOWN_0_0 => fpsc_vlo, + PCIE_POWERDOWN_0_1 => fpsc_vlo, + PCIE_RXVALID_0 => open, + PCIE_PHYSTATUS_0 => open, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => fpsc_vlo, + FF_TXI_CLK_0 => fpsc_vlo, + FF_EBRD_CLK_0 => fpsc_vlo, + FF_RX_F_CLK_0 => open, + FF_RX_H_CLK_0 => open, + FF_TX_F_CLK_0 => open, + FF_TX_H_CLK_0 => open, + FFC_CK_CORE_RX_0 => fpsc_vlo, + FF_TX_D_0_0 => fpsc_vlo, + FF_TX_D_0_1 => fpsc_vlo, + FF_TX_D_0_2 => fpsc_vlo, + FF_TX_D_0_3 => fpsc_vlo, + FF_TX_D_0_4 => fpsc_vlo, + FF_TX_D_0_5 => fpsc_vlo, + FF_TX_D_0_6 => fpsc_vlo, + FF_TX_D_0_7 => fpsc_vlo, + FF_TX_D_0_8 => fpsc_vlo, + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => fpsc_vlo, + FF_TX_D_0_11 => fpsc_vlo, + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => open, + FF_RX_D_0_1 => open, + FF_RX_D_0_2 => open, + FF_RX_D_0_3 => open, + FF_RX_D_0_4 => open, + FF_RX_D_0_5 => open, + FF_RX_D_0_6 => open, + FF_RX_D_0_7 => open, + FF_RX_D_0_8 => open, + FF_RX_D_0_9 => open, + FF_RX_D_0_10 => open, + FF_RX_D_0_11 => open, + FF_RX_D_0_12 => open, + FF_RX_D_0_13 => open, + FF_RX_D_0_14 => open, + FF_RX_D_0_15 => open, + FF_RX_D_0_16 => open, + FF_RX_D_0_17 => open, + FF_RX_D_0_18 => open, + FF_RX_D_0_19 => open, + FF_RX_D_0_20 => open, + FF_RX_D_0_21 => open, + FF_RX_D_0_22 => open, + FF_RX_D_0_23 => open, + + FFC_RRST_0 => fpsc_vlo, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => fpsc_vlo, + FFC_TXPWDNB_0 => fpsc_vlo, + FFC_LANE_RX_RST_0 => fpsc_vlo, + FFC_RXPWDNB_0 => fpsc_vlo, + FFS_RLOS_LO_0 => open, + FFS_RLOS_HI_0 => open, + FFS_PCIE_CON_0 => open, + FFS_PCIE_DONE_0 => open, + FFS_LS_SYNC_STATUS_0 => open, + FFS_CC_OVERRUN_0 => open, + FFS_CC_UNDERRUN_0 => open, + FFS_SKP_ADDED_0 => open, + FFS_SKP_DELETED_0 => open, + FFS_RLOL_0 => open, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + LDR_CORE2TX_0 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, + LDR_RX2CORE_0 => open, + FFS_CDR_TRAIN_DONE_0 => open, + FFC_DIV11_MODE_TX_0 => fpsc_vlo, + FFC_RATE_MODE_TX_0 => fpsc_vlo, + FFC_DIV11_MODE_RX_0 => fpsc_vlo, + FFC_RATE_MODE_RX_0 => fpsc_vlo, + +----- CH1 ----- + HDOUTP1 => open, + HDOUTN1 => open, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, + PCIE_TXCOMPLIANCE_1 => fpsc_vlo, + PCIE_RXPOLARITY_1 => fpsc_vlo, + PCIE_POWERDOWN_1_0 => fpsc_vlo, + PCIE_POWERDOWN_1_1 => fpsc_vlo, + PCIE_RXVALID_1 => open, + PCIE_PHYSTATUS_1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_TX_F_CLK_1 => open, + FF_TX_H_CLK_1 => open, + FFC_CK_CORE_RX_1 => fpsc_vlo, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_RLOS_HI_1 => open, + FFS_PCIE_CON_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_SKP_ADDED_1 => open, + FFS_SKP_DELETED_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + LDR_CORE2TX_1 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, + LDR_RX2CORE_1 => open, + FFS_CDR_TRAIN_DONE_1 => open, + FFC_DIV11_MODE_TX_1 => fpsc_vlo, + FFC_RATE_MODE_TX_1 => fpsc_vlo, + FFC_DIV11_MODE_RX_1 => fpsc_vlo, + FFC_RATE_MODE_RX_1 => fpsc_vlo, + +----- CH2 ----- + HDOUTP2 => open, + HDOUTN2 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, + PCIE_TXCOMPLIANCE_2 => fpsc_vlo, + PCIE_RXPOLARITY_2 => fpsc_vlo, + PCIE_POWERDOWN_2_0 => fpsc_vlo, + PCIE_POWERDOWN_2_1 => fpsc_vlo, + PCIE_RXVALID_2 => open, + PCIE_PHYSTATUS_2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_TX_F_CLK_2 => open, + FF_TX_H_CLK_2 => open, + FFC_CK_CORE_RX_2 => fpsc_vlo, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_RLOS_HI_2 => open, + FFS_PCIE_CON_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_SKP_ADDED_2 => open, + FFS_SKP_DELETED_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + LDR_CORE2TX_2 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, + LDR_RX2CORE_2 => open, + FFS_CDR_TRAIN_DONE_2 => open, + FFC_DIV11_MODE_TX_2 => fpsc_vlo, + FFC_RATE_MODE_TX_2 => fpsc_vlo, + FFC_DIV11_MODE_RX_2 => fpsc_vlo, + FFC_RATE_MODE_RX_2 => fpsc_vlo, + +----- CH3 ----- + HDOUTP3 => hdoutp_ch3, + HDOUTN3 => hdoutn_ch3, + HDINP3 => hdinp_ch3, + HDINN3 => hdinn_ch3, + PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, + PCIE_TXCOMPLIANCE_3 => fpsc_vlo, + PCIE_RXPOLARITY_3 => fpsc_vlo, + PCIE_POWERDOWN_3_0 => fpsc_vlo, + PCIE_POWERDOWN_3_1 => fpsc_vlo, + PCIE_RXVALID_3 => open, + PCIE_PHYSTATUS_3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => rxiclk_ch3, + FF_TXI_CLK_3 => txiclk_ch3, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => rx_full_clk_ch3, + FF_RX_H_CLK_3 => rx_half_clk_ch3, + FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, + FF_TX_H_CLK_3 => tx_half_clk_ch3, + FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, + FF_TX_D_3_0 => txdata_ch3(0), + FF_TX_D_3_1 => txdata_ch3(1), + FF_TX_D_3_2 => txdata_ch3(2), + FF_TX_D_3_3 => txdata_ch3(3), + FF_TX_D_3_4 => txdata_ch3(4), + FF_TX_D_3_5 => txdata_ch3(5), + FF_TX_D_3_6 => txdata_ch3(6), + FF_TX_D_3_7 => txdata_ch3(7), + FF_TX_D_3_8 => tx_k_ch3, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => xmit_ch3, + FF_TX_D_3_11 => tx_disp_correct_ch3, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => rxdata_ch3(0), + FF_RX_D_3_1 => rxdata_ch3(1), + FF_RX_D_3_2 => rxdata_ch3(2), + FF_RX_D_3_3 => rxdata_ch3(3), + FF_RX_D_3_4 => rxdata_ch3(4), + FF_RX_D_3_5 => rxdata_ch3(5), + FF_RX_D_3_6 => rxdata_ch3(6), + FF_RX_D_3_7 => rxdata_ch3(7), + FF_RX_D_3_8 => rx_k_ch3, + FF_RX_D_3_9 => rx_disp_err_ch3, + FF_RX_D_3_10 => rx_cv_err_ch3, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + + FFC_RRST_3 => rx_serdes_rst_ch3_c, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, + FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c, + FFC_TXPWDNB_3 => tx_pwrup_ch3_c, + FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, + FFC_RXPWDNB_3 => rx_pwrup_ch3_c, + FFS_RLOS_LO_3 => rx_los_low_ch3_sig, + FFS_RLOS_HI_3 => open, + FFS_PCIE_CON_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, + FFS_CC_OVERRUN_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_SKP_ADDED_3 => open, + FFS_SKP_DELETED_3 => open, + FFS_RLOL_3 => rx_cdr_lol_ch3_sig, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + LDR_CORE2TX_3 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, + LDR_RX2CORE_3 => open, + FFS_CDR_TRAIN_DONE_3 => open, + FFC_DIV11_MODE_TX_3 => fpsc_vlo, + FFC_RATE_MODE_TX_3 => fpsc_vlo, + FFC_DIV11_MODE_RX_3 => fpsc_vlo, + FFC_RATE_MODE_RX_3 => fpsc_vlo, + +----- Auxilliary ---- + SCIWDATA7 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA0 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIRDATA7 => open, + SCIRDATA6 => open, + SCIRDATA5 => open, + SCIRDATA4 => open, + SCIRDATA3 => open, + SCIRDATA2 => open, + SCIRDATA1 => open, + SCIRDATA0 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_CK_CORE_TX => fpga_txrefclk, + FFC_MACRO_RST => serdes_rst_qd_c, + FFC_QUAD_RST => rst_qd_c, + FFC_TRST => tx_serdes_rst_c, + FFS_PLOL => tx_pll_lol_qd_sig, + FFC_SYNC_TOGGLE => fpsc_vlo, + REFCK2CORE => refclk2fpga_sig, + CIN0 => fpsc_vlo, + CIN1 => fpsc_vlo, + CIN2 => fpsc_vlo, + CIN3 => fpsc_vlo, + CIN4 => fpsc_vlo, + CIN5 => fpsc_vlo, + CIN6 => fpsc_vlo, + CIN7 => fpsc_vlo, + CIN8 => fpsc_vlo, + CIN9 => fpsc_vlo, + CIN10 => fpsc_vlo, + CIN11 => fpsc_vlo, + COUT0 => open, + COUT1 => open, + COUT2 => open, + COUT3 => open, + COUT4 => open, + COUT5 => open, + COUT6 => open, + COUT7 => open, + COUT8 => open, + COUT9 => open, + COUT10 => open, + COUT11 => open, + COUT12 => open, + COUT13 => open, + COUT14 => open, + COUT15 => open, + COUT16 => open, + COUT17 => open, + COUT18 => open, + COUT19 => open, + REFCLK_FROM_NQ => refclk_from_nq, + REFCLK_TO_NQ => open); + + + + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on +end serdes_ch4_arch ; diff --git a/gbe_ecp2m/ipcores/serdes_ch4_generate.log b/gbe_ecp2m/ipcores/serdes_ch4_generate.log new file mode 100644 index 0000000..26130c0 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes_ch4_generate.log @@ -0,0 +1,29 @@ +Starting process: Module + +Starting process: + + Module Name: serdes_ch4 + Core Name: PCS + LPC file : serdes_ch4.lpc + Parameter File : serdes_ch4.pp + Command line: /opt/lattice/diamond/1.4/ispfpga/bin/lin/orcapp -Fmaco serdes_ch4.pp + Return Value: + + + + Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/. successfully! + +/opt/lattice/diamond/1.4/bin/lin/hdl2jhd -tfi -mod serdes_ch4 -ext readme -out serdes_ch4 -tpl serdes_ch4.tft serdes_ch4.vhd + +Done successfully! +File: serdes_ch4.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + +