From: Manuel Penschuck Date: Sat, 7 Feb 2015 14:42:56 +0000 (+0100) Subject: Recorrected some typos X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=39840d091cc68e3d8d96a7ad7b681f8f2694cff9;p=reports.git Recorrected some typos --- diff --git a/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf b/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf index 2bf347b..46ce0b2 100644 Binary files a/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf and b/GSI_2015_MP_CBMNet/trb3_cbmnet.pdf differ diff --git a/GSI_2015_MP_CBMNet/trb3_cbmnet.tex b/GSI_2015_MP_CBMNet/trb3_cbmnet.tex index a759df4..ea5f11f 100644 --- a/GSI_2015_MP_CBMNet/trb3_cbmnet.tex +++ b/GSI_2015_MP_CBMNet/trb3_cbmnet.tex @@ -26,11 +26,11 @@ \maketitle The TRB3 is a flexible and modular FPGA-based data acquisition platform originating from the HADES detector at GSI. -Unifying all base-functionality on a universal main-board, connectivity to the experimental setup is established using up to five application-specific add-on boards. +Unifying all base-functionality on a universal main board, connectivity to the experimental setup is established using up to five application-specific add-on boards. The platform is used by a number of detectors, amongst them prototypes for CBM-MVD and CBM-RICH. -The board features five inexpensive Lattice ECP3 FPGA optimised for a high IO count rather than computational power which is typically not required for early DAQ stages: -One central chip primarily executes management- and network-related tasks, while the remaining FPGAs together with their respective add-ons form four independent sub-systems. +The board features five inexpensive Lattice ECP3 FPGAs optimised for a high IO count rather than computational power, which is typically not required for early DAQ stages: +one central chip primarily executes management- and network-related tasks while the remaining FPGAs together with their respective add-ons form four independent sub-systems. Applications include FPGA-based TDC- (up to 264 channels/board with a precision of 7.2~ps RMS [1]) and ADC-measurements as well as the read-out of high-speed digital signals, e.g. for the MAPS in case of CBM-MVD. The TRB3 can be operated in a stand-alone fashion only requiring an external power supply and a PC capable of Gigabit Ethernet (GbE); however, large systems are inherently supported by its internal network protocol, TrbNet, which was originally developed for HADES. @@ -41,17 +41,18 @@ The adoption included the implementation of CBMNet's physical layer, the migrati Since TrbNet features a central trigger and read-out scheme, CBM's streaming data transport is emulated using a free-running mode of operation based on periodic pulsers. These cause the frontends to deliver their zero-suppressed data in packets with a temporal binning comparable to FlesNet's timeslices. -To reduce data overhead, load adaptive trigger frequencies based on external signals, such as an spill-indicator, are supported. +To reduce data overhead load adaptive trigger frequencies based on external signals, such as an spill-indicator, are supported. -As shown in Fig.~\ref{fig:l2ea4-f1} current network typologies foresee a single CBMNet bridge for (possibly) multiple interconnected TRB3s as TrbNet hubs are easily available; +As shown in Fig.~\ref{fig:l2ea4-f1}, current network typologies foresee a single CBMNet bridge for (possibly) multiple interconnected TRB3s since TrbNet hubs are easily available; in case of bandwidth limitation multiple uplink modules are provisioned in the firmware. -A unpacker software building on top of the FlesDaq infrastructure is available in CBMRoot. -Additionally a dual-stack uplink with CBMNet and GbE is possible. +An unpacker software building on top of the FlesDAQ infrastructure~[2] is available in CBMRoot. +Additionally, a dual-stack uplink with CBMNet and GbE is feasible. Synchronisation with native CBMNet frontends is possible by means of freely configurable DLMs. -Different approaches using one or many DLMs are supported an exhibit and event-to-event jitter of $< 50$~ps RMS after converting TrbNet timestamps into the CBMNet domain. +Several approaches suitable one to many DLMs are supported and exhibit an event-to-event jitter of $< 50$~ps RMS after converting TrbNet timestamps into the CBMNet domain. -Graphical user interfaces to configure, monitor and debug the new firmware was developed and successfully tested in conjunction with the current CBM-RICH prototype during a beam time in November 2014 at Cern (PS). +Graphical user interfaces to configure, monitor and debug the new firmware were developed and enable non-experts to operate the system. +The network bridge was successfully used in conjunction with the current CBM-RICH prototype during a beam time in November 2014 at Cern (PS). \begin{figure}[t] \begin{center} @@ -73,6 +74,9 @@ Graphical user interfaces to configure, monitor and debug the new firmware was d C. Ugur and the TRB3 collaboration, ``264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs'', IEEE NoMe TDC, October 2013 + \bibitem{} + D. Hutter, ``NOT KNOWN YET'', ????, March 2015 + \end{thebibliography} \end{document}