From: Adrian Weber Date: Mon, 1 Feb 2021 15:12:45 +0000 (+0100) Subject: change MBS part of cbmrich Trb5sc to new version from cri repo and change TDC to... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=39a41ef97c44eba07232ed0cfde45926261ad69f;p=trb5sc.git change MBS part of cbmrich Trb5sc to new version from cri repo and change TDC to stretched edge for ToT --- diff --git a/cbmrich/config.vhd b/cbmrich/config.vhd index e50a74b..e24a910 100644 --- a/cbmrich/config.vhd +++ b/cbmrich/config.vhd @@ -20,7 +20,7 @@ package config is constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3 + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj index 0463bb2..245251d 100644 --- a/cbmrich/trb5sc_cbmrich.prj +++ b/cbmrich/trb5sc_cbmrich.prj @@ -238,6 +238,8 @@ add_file -vhdl -lib work "../../cri/src/cri_cbm_rich_calib.vhd" add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd" add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd" +add_file -vhdl -lib work "../../cri/src/DLM_CTS_generator.vhd" + #CTS add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" diff --git a/cbmrich/trb5sc_cbmrich.vhd b/cbmrich/trb5sc_cbmrich.vhd index 10579d5..c981760 100644 --- a/cbmrich/trb5sc_cbmrich.vhd +++ b/cbmrich/trb5sc_cbmrich.vhd @@ -116,8 +116,8 @@ architecture arch of trb5sc_cbmrich is signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); signal rdack, wrack : std_logic; - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , bus_mbs_gen_tx, bustdccal_tx, buscts_tx, buscrireg_tx, busCriDataDbgReg_tx, bus_mbs_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, bus_mbs_gen_rx, bustdccal_rx, buscts_rx, buscrireg_rx, busCriDataDbgReg_rx, bus_mbs_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , bustdccal_tx, buscts_tx, buscrireg_tx, busCriDataDbgReg_tx, bus_mbs_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, bustdccal_rx, buscts_rx, buscrireg_rx, busCriDataDbgReg_rx, bus_mbs_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -197,11 +197,6 @@ architecture arch of trb5sc_cbmrich is signal cts_ipu_busy : std_logic; signal async_ext_trig : std_logic; - signal mbs_trigger : std_logic; - - signal mbs_local_trigger_num_in : std_logic_vector(15 downto 0); - signal mbs_local_trigger_in : std_logic; - --RESET sequence from CRI (as on combiner; ToBe checked) signal reset_via_cri_long, reset_via_cri_timer, last_reset_via_cri_long, make_reset : std_logic; @@ -639,76 +634,46 @@ THE_CTS : CTS --------------------------------------------------------------------------- -- MBS ---------------------------------------------------------------------------- - - THE_MBS_GENERATOR : entity work.mbs_generator_cbmrich - port map ( - CLK_SYS => clk_sys, - CLK_RX => med2int(INTERFACE_NUM).clk_full, - RESET_IN => reset_i, - - DLM_RX_IN => dlm_rx_i, - DLM_RX_DATA => dlm_rx_word, - - MBS_LOC_TRIG => mbs_local_trigger_in, - MBS_LOC_TRIG_NUM => mbs_local_trigger_num_in, - - BUS_RX => bus_mbs_gen_rx, - BUS_TX => bus_mbs_gen_tx - ); - - - THE_MBS_MASTER : entity work.mbs_master - port map ( - CLK => med2int(INTERFACE_NUM).clk_half, - RESET_IN => reset_i, - - MBS_CLOCK_OUT => open, - MBS_DATA_OUT => mbs_trigger, - - --data output for read-out - TRIGGER_IN => mbs_local_trigger_in, - TRIGGER_NUMBER_IN => mbs_local_trigger_num_in, - DATA_OUT => open, - WRITE_OUT => open, - FINISHED_OUT => open, - STATUSBIT_OUT => open - ); - - - THE_MBS_REC : entity work.mbs_recv - generic map( - USE_40MHz => c_NO - ) - port map ( - CLK => clk_sys, - RESET_IN => reset_i, - - MBS_IN => mbs_trigger, - CLK_200 => clk_full_osc, - - TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1), - TRG_SYNC_OUT => cts_ext_trigger, - - TRIGGER_IN => cts_rdo_rx.data_valid, - TRG_NUMBER_IN => cts_trg_number, - TRG_CODE_IN => cts_trg_code, - TIMING_TRG_IN => cts_trigger_out, - - DATA_OUT => cts_rdo_additional(0).data, - WRITE_OUT => cts_rdo_additional(0).data_write, - FINISHED_OUT => cts_rdo_additional(0).data_finished, - STATUSBIT_OUT => cts_rdo_additional(0).statusbits, - - REGIO_IN => bus_mbs_rx, - REGIO_OUT => bus_mbs_tx, +--------------------------------------------------------------------------- - CONTROL_REG_IN => cts_ext_control, - STATUS_REG_OUT => cts_ext_status, - HEADER_REG_OUT => cts_ext_header, - - DEBUG => cts_ext_debug - ); + THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator + generic map( + INCL_REGIO => c_YES + ) + port map ( + CLK => clk_sys, + RESET_IN => reset_i, + + -- recovered clock, synchronous to DLM @240MHz + CLK_RCV => med2int(INTERFACE_NUM).clk_full, + + --DLM inputs + DLM_IN => dlm_rx_i, + DLM_MSG_IN => dlm_rx_word, + + --trigger outputs + TRG_ASYNC_OUT => async_ext_trig, + TRG_SYNC_OUT => cts_ext_trigger, + + --data output for read-out + TRIGGER_IN => cts_rdo_rx.data_valid, + + -- Data connection to Streamer + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + + --Registers / Debug + REGIO_IN => bus_mbs_rx, + REGIO_OUT => bus_mbs_tx, + + -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode) + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + HEADER_REG_OUT => cts_ext_header, + DEBUG => cts_ext_debug + ); --------------------------------------------------------------------------- -- Bus Handler @@ -717,8 +682,8 @@ THE_CTS : CTS THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"e000", 5 => x"a000", 6 => x"8300", 7 => x"e500", 8 => x"e400", 9 => x"e410", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 9, 5 => 11, 6 => 8, 7 => 8, 8 => 4, 9 => 2, others => 0), + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"e000", 5 => x"a000", 6 => x"8300", 7 => x"e500", 8 => x"e400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 9, 5 => 11, 6 => 8, 7 => 8, 8 => 2, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -736,8 +701,7 @@ THE_CTS : CTS BUS_RX(5) => buscts_rx, BUS_RX(6) => buscrireg_rx, BUS_RX(7) => busCriDataDbgReg_rx, - BUS_RX(8) => bus_mbs_gen_rx, - BUS_RX(9) => bus_mbs_rx, + BUS_RX(8) => bus_mbs_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, @@ -747,8 +711,7 @@ THE_CTS : CTS BUS_TX(5) => buscts_tx, BUS_TX(6) => buscrireg_tx, BUS_TX(7) => busCriDataDbgReg_tx, - BUS_TX(8) => bus_mbs_gen_tx, - BUS_TX(9) => bus_mbs_tx, + BUS_TX(8) => bus_mbs_tx, STAT_DEBUG => open );