From: Jan Michel Date: Mon, 2 Jun 2025 12:18:03 +0000 (+0200) Subject: push latest changes, software update, disable flash X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=39c6973c97728ac09beb494e3d36ca4819bf0ab4;p=logicbox.git push latest changes, software update, disable flash --- diff --git a/default/config_compile_frankfurt.pl b/default/config_compile_frankfurt.pl index a9d1489..deab44c 100644 --- a/default/config_compile_frankfurt.pl +++ b/default/config_compile_frankfurt.pl @@ -6,8 +6,8 @@ Speedgrade => '5', TOPNAME => "logicbox", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', -synplify_path => '/d/jspc29/lattice/synplify/N-2017.09-1', +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', # synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", # synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", diff --git a/default/logicbox.prj b/default/logicbox.prj index ee99ae2..00785f8 100644 --- a/default/logicbox.prj +++ b/default/logicbox.prj @@ -4,7 +4,7 @@ #project files -add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" +add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.12/cae_library/synthesis/vhdl/machxo3lf.vhd" #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" @@ -17,6 +17,7 @@ add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd" add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd" add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v" add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v" + add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd" add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd" diff --git a/default/logicbox.vhd b/default/logicbox.vhd index 69d1af4..41db033 100644 --- a/default/logicbox.vhd +++ b/default/logicbox.vhd @@ -81,8 +81,8 @@ architecture arch of logicbox is ------------------------------------- signal pulser : std_logic; signal pulser_counter : unsigned(27 downto 0) := (others => '0'); - signal pulser_periodlength : unsigned(27 downto 0) := x"0000002"; - signal pulser_pulslength : unsigned(27 downto 0) := x"0000001"; + signal pulser_periodlength : unsigned(27 downto 0) := x"0002000"; + signal pulser_pulslength : unsigned(27 downto 0) := x"000000a"; signal pulser_periodlength_buffer : unsigned(27 downto 0); signal pulser_pulslength_buffer : unsigned(27 downto 0); @@ -318,34 +318,40 @@ THE_UART : entity work.uart_sctrl ); -THE_FLASH_CONTROLLER : entity generic_flash_ctrl - generic map( - DATA_BUS_WIDTH => 32 - ) - port map( - - CLK_l => clk_33, - CLK_f => clk_33, - RESET => '0', - - SPI_DATA_IN => uart_data_out, - SPI_DATA_OUT => uart_data_in, - SPI_ADDR_IN => uart_addr_out, - SPI_WRITE_IN => uart_write_out, - SPI_READ_IN => uart_read_out, - SPI_READY_OUT => uart_ready_in, - SPI_BUSY_IN => uart_busy_out, - - LOC_DATA_OUT => uart_rx_data, - LOC_DATA_IN => uart_tx_data, - LOC_ADDR_OUT => uart_addr, - LOC_WRITE_OUT => bus_write, - LOC_READ_OUT => bus_read, - LOC_READY_IN => bus_ready, - LOC_BUSY_OUT => bus_busy - - ); - +--THE_FLASH_CONTROLLER : entity generic_flash_ctrl + --generic map( + --DATA_BUS_WIDTH => 32, + --USE_I2C_PROG => 0 + --) + --port map( + + --CLK_l => clk_33, + --CLK_f => clk_33, + --RESET => '0', + + --SPI_DATA_IN => uart_data_out, + --SPI_DATA_OUT => uart_data_in, + --SPI_ADDR_IN => uart_addr_out, + --SPI_WRITE_IN => uart_write_out, + --SPI_READ_IN => uart_read_out, + --SPI_READY_OUT => uart_ready_in, + --SPI_BUSY_IN => uart_busy_out, + + --LOC_DATA_OUT => uart_rx_data, + --LOC_DATA_IN => uart_tx_data, + --LOC_ADDR_OUT => uart_addr, + --LOC_WRITE_OUT => bus_write, + --LOC_READ_OUT => bus_read, + --LOC_READY_IN => bus_ready, + --LOC_BUSY_OUT => bus_busy + --); +uart_rx_data <= uart_data_out; +uart_data_in <= uart_tx_data; +uart_addr <= uart_addr_out; +bus_write <= uart_write_out; +bus_read <= uart_read_out; +uart_ready_in <= bus_ready; +bus_busy <= uart_busy_out; --------------------------------------------------------------------------- -- Read/WRITE REGISTERS VIA UART/FLASH diff --git a/stretcher/compile.pl b/stretcher/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/stretcher/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/stretcher/config_compile_frankfurt.pl b/stretcher/config_compile_frankfurt.pl new file mode 100644 index 0000000..e25ed7e --- /dev/null +++ b/stretcher/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'MachXO3LF', +Devicename => 'LCMXO3LF-2100E', +Package => 'WLCSP49', +Speedgrade => '5', + +TOPNAME => "logicbox", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +make_jed => 1, diff --git a/stretcher/logicbox.prj b/stretcher/logicbox.prj new file mode 100644 index 0000000..00785f8 --- /dev/null +++ b/stretcher/logicbox.prj @@ -0,0 +1,90 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03L-SP1 +#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt + +#project files + +add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.12/cae_library/synthesis/vhdl/machxo3lf.vhd" + +#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/uart_sctrl.vhd" +add_file -vhdl -lib work "../code/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd" +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd" +add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v" +add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v" + +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd" + +add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd" + + +add_file -vhdl -lib work "logicbox.vhd" + + + +#implementation: "LogicBox" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par + +#device options +set_option -technology MACHXO3LF +set_option -part LCMXO3LF_2100E +set_option -package UWG49CTR +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "logicbox" + +# mapper_options +set_option -frequency 1 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 1000 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 1 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 +set_option -multi_file_compilation_unit 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/logicbox.edf" + +#set log file +set_option log_file "workdir/logicbox.srf" +impl -active "workdir" diff --git a/stretcher/logicbox.vhd b/stretcher/logicbox.vhd new file mode 100644 index 0000000..fd37f8e --- /dev/null +++ b/stretcher/logicbox.vhd @@ -0,0 +1,451 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library machxo3lf; +use machxo3lf.all; + +library work; +use work.all;--trb_net_std.all; + +entity logicbox is + port( + CLK : in std_logic; + + INPUT : in std_logic_vector(3 downto 0); + OUTPUT : out std_logic_vector(3 downto 0); + + LED : inout std_logic_vector(3 downto 0); + + STATUSI : in std_logic; + STATUSO : in std_logic; + CONTROLI : out std_logic; + CONTROLO : out std_logic; + + RX_OUT : out std_logic; + TX_IN : in std_logic; + CBUS : in std_logic + ); +end entity; + +architecture arch of logicbox is + signal clk_i, clk_osc, clk_33,clk_266 : std_logic; + signal led_i : std_logic_vector(3 downto 0); + signal timer_i : unsigned(31 downto 0) := (others => '0'); + signal config : std_logic_vector(3 downto 0); + signal led_highz : std_logic; + + type led_timer_t is array(0 to 3) of unsigned(26 downto 0); + signal led_timer : led_timer_t; + signal led_state : std_logic_vector(3 downto 0); + signal stretch_timer : led_timer_t; + signal stretch_state : std_logic_vector(3 downto 0); + + --UART + ------------------------------------- + signal uart_data_out : std_logic_vector(31 downto 0); + signal uart_data_in : std_logic_vector(31 downto 0); + signal uart_addr_out : std_logic_vector(7 downto 0); + signal uart_read_out : std_logic := '0'; + signal uart_write_out : std_logic := '0'; + signal uart_ready_in : std_logic; + signal uart_busy_out : std_logic; + + signal uart_rx_data : std_logic_vector(31 downto 0); + signal uart_tx_data : std_logic_vector(31 downto 0); + signal uart_addr : std_logic_vector(7 downto 0); + signal bus_read : std_logic := '0'; + signal bus_write : std_logic := '0'; + signal bus_ready : std_logic; + signal bus_busy : std_logic; + + signal input_i : std_logic_vector(3 downto 0); + signal input_selected : std_logic_vector(3 downto 0); + signal input_stretched, input_hold : std_logic_vector(3 downto 0); + signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0); + signal input_and, input_or : std_logic; + + signal edge_rising, edge_falling : std_logic_vector(3 downto 0); + signal reg : std_logic_vector(31 downto 0); + signal last_config : std_logic_vector(3 downto 0); + + signal sed_error : std_logic; + signal sed_debug : std_logic_vector(31 downto 0); + signal controlsed_i : std_logic_vector(3 downto 0); + signal reset_counters : std_logic; + + signal disabled_inp : std_logic_vector(3 downto 0) := x"0"; + + type cnt_t is array(0 to 3) of unsigned(23 downto 0); + signal input_counters : cnt_t; + + --PULSER + ------------------------------------- + signal pulser : std_logic; + signal pulser_counter : unsigned(27 downto 0) := (others => '0'); + signal pulser_periodlength : unsigned(27 downto 0) := x"0002000"; + signal pulser_pulslength : unsigned(27 downto 0) := x"000000a"; + signal pulser_periodlength_buffer : unsigned(27 downto 0); + signal pulser_pulslength_buffer : unsigned(27 downto 0); + + + component OSCH + generic (NOM_FREQ: string := "133.00"); + port ( + STDBY :IN std_logic; + OSC :OUT std_logic; + SEDSTDBY :OUT std_logic + ); + end component; + + +begin + +--------------------------------------------------------------------------- +-- I/O Logic +--------------------------------------------------------------------------- +-- 0 1:1, +-- 1 1:4 fan-out, +-- 2 1:1, O1 is or of inputs + +-- 3 1:1, invert +-- 4 1:4 fan-out, invert +-- 5 1:1, O1 is or of inputs, invert + +-- 6 1:1, rising_edge to 14-21 ns +-- 7 1:1, falling_edge to 14-21 ns + +-- 8 1:1, stretching by +14-21ns +-- 9 1:4 fan-out, stretching +-- a 1:1, O1 is or of inputs, stretching + +-- b O0 is and, O2 is or of all enabled outputs +-- c like b, but inverted inputs + +-- e pulser, default 8.1 kHz, 60ns +-- f pulser, default 8.1 kHz, 60ns, negative + +input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1); +input_selected <= not input_i when config >= x"8" else input_i; + +--input_stretched <= input_hold or input_reg_0 or input_reg_1; + +--Stretcher needs to work with negative signals as well +input_hold <= input_selected or (input_hold and not input_reg_0); + +input_reg_0 <= input_hold when rising_edge(clk_33); +input_reg_1 <= input_reg_0 when rising_edge(clk_33); +input_reg_2 <= input_reg_1 when rising_edge(clk_33); + +--edge_rising <= input_stretched and not input_reg_2; +--edge_falling <= not input_stretched and input_reg_2; + +--input_and <= (input_selected(0) or disabled_inp(0)) + --and (input_selected(1) or disabled_inp(1)) + --and (input_selected(2) or disabled_inp(2)) + --and (input_selected(3) or disabled_inp(3)); + +--input_or <= (input_selected(0) and not disabled_inp(0)) + --or (input_selected(1) and not disabled_inp(1)) + --or (input_selected(2) and not disabled_inp(2)) + --or (input_selected(3) and not disabled_inp(3)); + + +--process(INPUT,config, STATUSI) + --begin + --case config is + --when x"0" => + --OUTPUT <= input_selected; + --when x"1" => + --OUTPUT <= (others => input_selected(0)); + --when x"2" => + --OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & (input_selected(0) or input_selected(2)) & input_selected(0); + --when x"3" => + --OUTPUT <= input_selected; + --when x"4" => + --OUTPUT <= (others => input_selected(0)); + --when x"5" => + --OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & + --(input_selected(0) or input_selected(2)) & input_selected(0); + --when x"6" => + --OUTPUT <= edge_rising; + --when x"7" => + --OUTPUT <= edge_falling; + --when x"8" => + --OUTPUT <= input_stretched; + --when x"9" => + --OUTPUT <= (others => input_stretched(0)); + --when x"a" => + --OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0); + --when x"b" => + --OUTPUT <= '0' & input_or & '0' & input_and; + --when x"c" => + --OUTPUT <= '0' & input_or & '0' & input_and; + --when x"e" => + --OUTPUT <= (others => pulser); + --when x"f" => + --OUTPUT <= (others => not pulser); + --when others => + --OUTPUT <= input_selected; + --end case; + OUTPUT <= stretch_state; + --end process; + +----------------------------------------------------------------------------- +---- Pulser +----------------------------------------------------------------------------- + --PROC_PULSER : process begin + --wait until rising_edge(clk_i); + --pulser_counter <= pulser_counter + 1; + + --if pulser_counter = x"0000000" then + --pulser <= '1'; + --pulser_pulslength_buffer <= pulser_pulslength; + --pulser_periodlength_buffer <= pulser_periodlength; + --end if; + + --if pulser_counter = pulser_pulslength_buffer then + --pulser <= '0'; + --end if; + + --if pulser_counter = pulser_periodlength_buffer then + --pulser_counter <= (others => '0'); + --end if; + --end process; + + + + PROC_STRETCHER : process + variable config_length : integer range 0 to 7; + begin + wait until rising_edge(clk_33); + config_length := to_integer(unsigned(config(2 downto 0))); + for i in 0 to 3 loop + if (input_reg_1(i) xor input_reg_2(i)) = '1' then + stretch_timer(i) <= (others => '0'); + stretch_timer(i)(config_length*2+10) <= '1'; + end if; + + if stretch_timer(i) /= 0 then + stretch_timer(i) <= stretch_timer(i) - 1; + end if; + + if stretch_timer(i) = 0 then + stretch_state(i) <= '1'; + else + stretch_state(i) <= '0'; + end if; + + + end loop; + end process; + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + PROC_LED : process begin + wait until rising_edge(clk_33); + if not (config = last_config) and timer_i(25) = '0' then + led_i <= config; + elsif STATUSI = '0' then + led_i <= led_state; + else + led_i <= led_state(2) & led_state(3) & led_state(0) & led_state(1); + end if; + end process; + + PROC_LED_STATE : process begin + wait until rising_edge(clk_33); + for i in 0 to 3 loop + if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(21 downto 19) > 0) then + led_state(i) <= not led_state(i); + led_timer(i) <= 0; + elsif led_timer(i)(21) = '1' then + led_state(i) <= input_reg_1(i); + else + led_timer(i) <= led_timer(i) + 1; + end if; + end loop; + end process; + +--------------------------------------------------------------------------- +-- Counter +--------------------------------------------------------------------------- + --PROC_CNT : process begin + --wait until rising_edge(clk_i); + --for i in 0 to 3 loop + --if input_reg_1(i) = '1' and input_reg_2(i) = '0' then + --input_counters(i) <= input_counters(i) + 1; + --end if; + --if reset_counters = '1' then + --input_counters(i) <= (others => '0'); + --end if; + --end loop; + --end process; + + +--------------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------------- +clk_source: OSCH + generic map ( NOM_FREQ => "133" ) + port map ( + STDBY => '0', + OSC => clk_osc, + SEDSTDBY => open + ); + +THE_PLL : entity work.pll_in133_out33_133_266 + port map ( + CLKI => clk_osc, + CLKOP => clk_i, --133 + CLKOS => clk_33, --33 + CLKOS2=> clk_266 --266 + ); + +timer_i <= timer_i + 1 when rising_edge(clk_33); + +--------------------------------------------------------------------------- +-- Read configuration switch +--------------------------------------------------------------------------- +process begin + wait until rising_edge(clk_33); + if timer_i(25 downto 8) = 0 then + led_highz <= '1'; + last_config <= config; + if timer_i(7 downto 0) = x"ff" then + config <= not LED; + end if; + else + led_highz <= '0'; + end if; +end process; + +LED <= led_i when led_highz = '0' else "ZZZZ"; + +--------------------------------------------------------------------------- +-- UART +--------------------------------------------------------------------------- +--THE_UART : entity work.uart_sctrl + --generic map( + --CLOCK_SPEED => 33250000 + --) + --port map( + --CLK => clk_33, + --RESET => '0', + --UART_RX => TX_IN, + --UART_TX => RX_OUT, + + --DATA_OUT => uart_data_out, + --DATA_IN => uart_data_in, + --ADDR_OUT => uart_addr_out, + --WRITE_OUT => uart_write_out, + --READ_OUT => uart_read_out, + --READY_IN => uart_ready_in, + --BUSY_OUT => uart_busy_out, + + --DEBUG => open + --); + + +--THE_FLASH_CONTROLLER : entity generic_flash_ctrl + --generic map( + --DATA_BUS_WIDTH => 32, + --USE_I2C_PROG => 0 + --) + --port map( + + --CLK_l => clk_33, + --CLK_f => clk_33, + --RESET => '0', + + --SPI_DATA_IN => uart_data_out, + --SPI_DATA_OUT => uart_data_in, + --SPI_ADDR_IN => uart_addr_out, + --SPI_WRITE_IN => uart_write_out, + --SPI_READ_IN => uart_read_out, + --SPI_READY_OUT => uart_ready_in, + --SPI_BUSY_IN => uart_busy_out, + + --LOC_DATA_OUT => uart_rx_data, + --LOC_DATA_IN => uart_tx_data, + --LOC_ADDR_OUT => uart_addr, + --LOC_WRITE_OUT => bus_write, + --LOC_READ_OUT => bus_read, + --LOC_READY_IN => bus_ready, + --LOC_BUSY_OUT => bus_busy + --); +--uart_rx_data <= uart_data_out; +--uart_data_in <= uart_tx_data; +--uart_addr <= uart_addr_out; +--bus_write <= uart_write_out; +--bus_read <= uart_read_out; +--uart_ready_in <= bus_ready; +--bus_busy <= uart_busy_out; + +--------------------------------------------------------------------------- +-- Read/WRITE REGISTERS VIA UART/FLASH +--------------------------------------------------------------------------- +--PROC_REGS : process begin + --wait until rising_edge(clk_33); + + ----register <=> UART datatransfer + --------------------------------------------------------------------- + --bus_ready <= '0'; + --reset_counters <= '0'; +---- ufm_go <= '0'; --for operating UFM_control + + --if bus_read = '1' then + ----send out data from registers over RS232 + --bus_ready <= '1'; + --case uart_addr is + --when x"00" => uart_tx_data <= x"0000000" & config; + --when x"10" => uart_tx_data <= x"0000000" & disabled_inp; + --when x"ee" => uart_tx_data <= sed_debug; + + --when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength); + --when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength); + + --when x"30" => uart_tx_data <= x"00" & std_logic_vector(input_counters(0)); + --when x"31" => uart_tx_data <= x"00" & std_logic_vector(input_counters(1)); + --when x"32" => uart_tx_data <= x"00" & std_logic_vector(input_counters(2)); + --when x"33" => uart_tx_data <= x"00" & std_logic_vector(input_counters(3)); + + --when others => uart_tx_data <= x"00000000"; + --end case; + + --elsif bus_write = '1' then + ----write registers with data from received from RS232 + --case uart_addr is + + --when x"10" => disabled_inp <= uart_rx_data(3 downto 0); + + --when x"20" => if uart_rx_data = x"00000000" or uart_rx_data = x"00000001" then + --pulser_periodlength <= x"0000001"; + --else + --pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1; + --end if; + --when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0); + + --when x"30" => reset_counters <= '1'; + + --when x"ee" => controlsed_i <= uart_rx_data(3 downto 0); + + --when others => null; + --end case; + --end if; + +--end process; + + +-- THE_SED : entity work.sedcheck +-- port map( +-- CLK => clk_i, +-- ERROR_OUT => sed_error, +-- +-- CONTROL_IN => controlsed_i, +-- DEBUG => sed_debug +-- ); + +end architecture; diff --git a/stretcher/par.p2t b/stretcher/par.p2t new file mode 100644 index 0000000..39a0684 --- /dev/null +++ b/stretcher/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1