From: Jan Michel <j.michel@gsi.de>
Date: Fri, 10 Feb 2017 17:29:54 +0000 (+0100)
Subject: merge logicbox.vhd
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3a2d75d25ea6295c312b3cb8c006bfc528133536;p=logicbox.git

merge logicbox.vhd
---

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index 92e9d4f..b59dea1 100644
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -69,7 +69,7 @@ architecture arch of logicbox is
   signal pulser_pulslength : unsigned(27 downto 0) := x"0000001";
   signal pulser_periodlength_buffer : unsigned(27 downto 0);
   signal pulser_pulslength_buffer : unsigned(27 downto 0);
-  
+
   --UFM
   -------------------------------------
   signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write
@@ -80,6 +80,7 @@ architecture arch of logicbox is
   signal ufm_bus_ready_out : std_logic;
   signal ufm_bus_ready_in : std_logic;
   signal ufm_busy : std_logic;
+
   
   component OSCH
     generic (NOM_FREQ: string := "133.00");
@@ -417,6 +418,21 @@ end process;
 --     DEBUG      => sed_debug
 --     );
 
+--   process begin
+--     wait until rising_edge(clk_i);
+--     if counter = x"40" then
+--       counter <= 0;
+--       pwm <= '1';
+--     else  
+--       counter <= counter + 1;
+--       pwm <= '0';
+--     end if; 
+--   end process;
+--     
+--     
+--     OUTPUT <= '0' & pwm & '0' & pwm;
+--     CONTROLO <= pwm;
+    
 end architecture;