From: Michael Traxler <M.Traxler@gsi.de>
Date: Wed, 15 Nov 2023 01:25:53 +0000 (+0100)
Subject: added DiRICH5d, mt
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3a4061767034d8b9c639cd3c436afe7870e1fe66;p=daqdocu.git

added DiRICH5d, mt
---

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index b3315cb..8d42201 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -159,6 +159,7 @@ All boards of a given type are accessible by a broadcast address (0xFE\_\_) at t
  \item 0x55 FaRICH1 TDCv4
  \item 0x56 DiRICH1 TDCv4
  \item 0x57 DiRICH5s TDCv2
+ \item 0x58 DiRICH5d TDCv2   
  \item 0x60 Trb3sc
  \item 0x61 Trb3sc Backplane Master w/ GbE
  \item 0x62 Trb3sc CTS w/ SFP
@@ -201,6 +202,7 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen in the
  \item 0xF3CE crate master TRB3sc
  \item 0xF3D1 DiRICH
  \item 0xF3D5 DiRICH5s
+ \item 0xF3D8 DiRICH5d
  \item 0xF3DC DiRICH combiner
  \item 0xF355 Trb5sc
 \end{itemize*}
@@ -222,6 +224,7 @@ The upper 16 Bit are used by the software to identify the hardware before progra
  \item[9700] design for DiRich Combiner module, \verb!combiner!
  \item[9900] design for Munich Skyroc boards
  \item[9A00] design for DiRICH5s, \verb!dirich5s!
+ \item[9A80] design for DiRICH5d, \verb!dirich5d!
  \item[9B00] design for FaRICH1, \verb!farich!
  \item[9C00] design for DiRICH1, \verb!dirich!