From: Tobias Weber Date: Thu, 9 Aug 2018 13:18:21 +0000 (+0200) Subject: pipe for generator output. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3b30990bc93a0f4aa7bada2ff18eed08807063fb;p=trb3.git pipe for generator output. --- diff --git a/mupix/Mupix8/sources/Simulation/Generator3.vhd b/mupix/Mupix8/sources/Simulation/Generator3.vhd index f7fc745..fe052e7 100644 --- a/mupix/Mupix8/sources/Simulation/Generator3.vhd +++ b/mupix/Mupix8/sources/Simulation/Generator3.vhd @@ -10,119 +10,133 @@ library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; entity Generator3 is - generic( - iWIDTH : natural := 32); - port( - clk : in std_logic; - reset : in std_logic; - start_gen : in std_logic; - data_num : in std_logic_vector(31 downto 0); - data_pause : in std_logic_vector(31 downto 0); - data_down : in std_logic_vector(31 downto 0); - chan_sel : in std_logic_vector(1 downto 0); - data_out : out std_logic_vector(iWIDTH - 1 downto 0); - writeEn : out std_logic + generic( + iWIDTH : natural := 32); + port( + clk : in std_logic; + reset : in std_logic; + start_gen : in std_logic; + data_num : in std_logic_vector(31 downto 0); + data_pause : in std_logic_vector(31 downto 0); + data_down : in std_logic_vector(31 downto 0); + chan_sel : in std_logic_vector(1 downto 0); + data_out : out std_logic_vector(iWIDTH - 1 downto 0); + writeEn : out std_logic ); end Generator3; architecture Behavior of Generator3 is -type state is (idle, gen, pause, down); -type chan_type is array (0 to 3) of std_logic_vector(15 downto 0); + type state is (idle, gen, pause, down); + type chan_type is array (0 to 3) of std_logic_vector(15 downto 0); -signal data_fsm : state := idle; -signal writeEn_int : std_logic := '0'; -signal num_ctr : unsigned(31 downto 0) := (others => '0'); -signal pause_ctr : unsigned(31 downto 0) := (others => '0'); -signal down_ctr : unsigned(31 downto 0) := (others => '0'); ---signal data_int : unsigned(15 downto 0) := (others => '0'); -constant chan_sig : chan_type := ( - 0 => x"C01C", - 1 => x"C02C", - 2 => x"C03C", - 3 => x"C04C" -); + signal data_fsm : state := idle; + signal writeEn_int : std_logic := '0'; + signal num_ctr : unsigned(31 downto 0) := (others => '0'); + signal pause_ctr : unsigned(31 downto 0) := (others => '0'); + signal down_ctr : unsigned(31 downto 0) := (others => '0'); + constant chan_sig : chan_type := ( + 0 => x"C01C", + 1 => x"C02C", + 2 => x"C03C", + 3 => x"C04C" + ); + + signal data_out_i : std_logic_vector(iWIDTH - 1 downto 0) := (others => '0'); + signal writeEn_i : std_logic := '0'; begin - generator: process (clk) - begin - if rising_edge(clk) then - if reset = '1' then - data_fsm <= idle; - num_ctr <= (others => '0'); - pause_ctr <= (others => '0'); - down_ctr <= (others => '0'); --- data_int <= (others => '0'); - writeEn_int <= '0'; + generator : process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + data_fsm <= idle; + num_ctr <= (others => '0'); + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); + + writeEn_int <= '0'; + else + case data_fsm is + + when idle => + num_ctr <= (others => '0'); + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); + writeEn_int <= '0'; + if start_gen = '1' and unsigned(data_num) > 0 then + data_fsm <= gen; else - case data_fsm is - - when idle => - num_ctr <= (others => '0'); - pause_ctr <= (others => '0'); - down_ctr <= (others => '0'); - writeEn_int <= '0'; - if start_gen = '1' and unsigned(data_num) > 0 then - data_fsm <= gen; - else - data_fsm <= idle; - end if; - - when gen => - if unsigned(data_num) > 0 then - pause_ctr <= (others => '0'); - down_ctr <= (others => '0'); --- data_int <= data_int + 1; - writeEn_int <= '1'; - num_ctr <= num_ctr + 1; - if num_ctr < unsigned(data_num) - 1 then - if unsigned(data_pause) > 0 then - data_fsm <= pause; - else - data_fsm <= gen; - end if; - else - data_fsm <= down; - end if; - else - data_fsm <= idle; - end if; - - when pause => - writeEn_int <= '0'; - if unsigned(data_pause) > 0 then - if pause_ctr < unsigned(data_pause) - 1 then - data_fsm <= pause; - pause_ctr <= pause_ctr + 1; - else - data_fsm <= gen; - end if; - else - data_fsm <= idle; - end if; - - when down => - writeEn_int <= '0'; - num_ctr <= (others => '0'); - if unsigned(data_down) > 0 then - if down_ctr < unsigned(data_down) - 1 then - data_fsm <= down; - down_ctr <= down_ctr + 1; - else - data_fsm <= gen; - end if; - else - data_fsm <= idle; - end if; - end case; + data_fsm <= idle; end if; - writeEn <= writeEn_int; - data_out <= chan_sig(to_integer(unsigned(chan_sel))) & std_logic_vector(num_ctr(15 downto 0)) & x"BE"; - end if; - end process generator; - + + when gen => + if unsigned(data_num) > 0 then + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); + writeEn_int <= '1'; + num_ctr <= num_ctr + 1; + if num_ctr < unsigned(data_num) - 1 then + if unsigned(data_pause) > 0 then + data_fsm <= pause; + else + data_fsm <= gen; + end if; + else + data_fsm <= down; + end if; + else + data_fsm <= idle; + end if; + + when pause => + writeEn_int <= '0'; + if unsigned(data_pause) > 0 then + if pause_ctr < unsigned(data_pause) - 1 then + data_fsm <= pause; + pause_ctr <= pause_ctr + 1; + else + data_fsm <= gen; + end if; + else + data_fsm <= idle; + end if; + + when down => + writeEn_int <= '0'; + num_ctr <= (others => '0'); + if unsigned(data_down) > 0 then + if down_ctr < unsigned(data_down) - 1 then + data_fsm <= down; + down_ctr <= down_ctr + 1; + else + data_fsm <= gen; + end if; + else + data_fsm <= idle; + end if; + end case; + end if; + writeEn_i <= writeEn_int; + data_out_i <= chan_sig(to_integer(unsigned(chan_sel))) & std_logic_vector(num_ctr(15 downto 0)) & x"BE"; + end if; + end process generator; + + output : process (clk) is + begin -- process output + if rising_edge(clk) then -- rising clock edge + if reset = '1' then -- synchronous reset (active lowhigh) + writeEn <= '0'; + data_out <= (others => '0'); + else + writeEn <= writeEn_i; + data_out <= data_out_i; + end if; + end if; + end process output; + end Behavior;