From: hadeshyp <hadeshyp>
Date: Thu, 13 May 2010 13:26:08 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3d565c77ef54b909d5f357d6478b372158ab6ce8;p=daqdocu.git

*** empty log message ***
---

diff --git a/main.tex b/main.tex
index 61a654e..1a2ce29 100755
--- a/main.tex
+++ b/main.tex
@@ -50,7 +50,7 @@
 
 \title{DaqNet - A Preliminary Handbook}
 \date{\today ~-~\thistime}
-\author{Jan Michel}
+\author{Jan Michel, Michael B\"ohmer, Grzegorz Korcyl}
 
 
 \newcommand{\filename}[1]{\textit{#1}}
@@ -153,4 +153,4 @@
 \clearpage
 \bibliography{biblio}
 
-\end{document}
\ No newline at end of file
+\end{document}
diff --git a/slowcontrol.tex b/slowcontrol.tex
index 4aa0ea4..6f5eeef 100755
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -30,7 +30,7 @@ addresses and the board ID.}
 \begin{center}
   \begin{tabular}[c]{|c|c|c|c|c|c|}
   \hline
-  \textsc{Dtype} & \textsc{Description} & F0 & F1 & F2 & F3 \\ 
+  \textsc{Dtype} & \textsc{Description} & F0 & F1 & F2 & F3 \\
   \hline\hline
   8 & read register & address & 0 & 0 & reserved\\
   9 & write register & address & data(31..16) & data(15..0) & reserved \\
@@ -44,7 +44,7 @@ section about addresses} \\
   \caption{[Register read/write protocol]Register read/write protocol. The config word for multiple accesses has the highest bit selecting between fixed (0) addresses and ascending (1) addresses. The lower 15 bit on the read operation select the maximum number of read accesses to be made. A multiple write always consists of one starting word containing address and mode followed by an arbitrary number of data packets.}
   \label{RegIO:protocol}
 \end{center}
-\end{table} 
+\end{table}
 
 
 Internally it also has logic to readout the 1-wire temperature logic and to assign network addresses. Other features include a global timer and configurable easy-to-use status and control registers. Additional, more complex logic can be connected to the internal data bus.
@@ -297,11 +297,14 @@ The first common control register consists of strobe signals for dummy timing tr
 3 & master reset \\
 10 & reset sequence counter \\
 15 & reboot FPGA \\
-16 - 23 & dummy timing triggers \\
+16 - 19 & dummy timing triggers \\
+20 - 21 & reserved \\
+22 & Begin Run trigger \\
+23 & End Run trigger \\
 24 - 31 & user defined \\
 \hline
 \end{tabular}
-\caption{Common Control Register 0}
+\caption{Common Control Register 0. All bits are strobe signals.}
 \label{CommonCtrlReg0}
 \end{center}
 \end{table}