From: Jan Michel <j.michel@gsi.de>
Date: Tue, 16 Apr 2013 09:32:25 +0000 (+0200)
Subject: added debug output, changed LEDs
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3e1556fadd6b98e0d01b068b9fa5dcab6969a114;p=soda.git

added debug output, changed LEDs
---

diff --git a/soda_slave/trb3_periph_sodaslave.vhd b/soda_slave/trb3_periph_sodaslave.vhd
index 61a780c..d6670cd 100644
--- a/soda_slave/trb3_periph_sodaslave.vhd
+++ b/soda_slave/trb3_periph_sodaslave.vhd
@@ -198,14 +198,16 @@ architecture trb3_periph_sodaslave_arch of trb3_periph_sodaslave is
   signal rx_dlm_i          : std_logic;
   signal tx_dlm_word       : std_logic_vector(7 downto 0);
   signal rx_dlm_word       : std_logic_vector(7 downto 0);
-
+  signal send_net_reset    : std_logic;
+  signal make_reset        : std_logic;
 begin
 ---------------------------------------------------------------------------
 -- Reset Generation
 ---------------------------------------------------------------------------
 
   GSR_N <= pll_lock;
-
+  send_net_reset <= med_stat_op(15);
+  
   THE_RESET_HANDLER : trb_net_reset_handler
     generic map(
       RESET_DELAY => x"FEEE"
@@ -217,13 +219,14 @@ begin
       SYSCLK_IN     => clk_sys_i,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
       RESET_IN      => '0',              -- general reset signal (SYSCLK)
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      TRB_RESET_IN  => make_reset,       -- TRBnet reset signal (SYSCLK)
       CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
       RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
       DEBUG_OUT     => open
       );  
 
-
+make_reset <= med_stat_op(13); -- or med_stat_op(1) or med_stat_op(0);
+      
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
@@ -517,11 +520,11 @@ THE_SODA_INPUT : med_ecp3_sfp_sync
     IS_SYNC_SLAVE => c_YES
     )
   port map(
-    CLK                => clk_raw_internal, --clk_200_i,
+    CLK                => clk_raw_internal,
     SYSCLK             => clk_sys_i,
     RESET              => reset_i,
     CLEAR              => clear_i,
-    --Internal Connection for TrbNet data -> not used a.t.m.
+    --Internal Connection for TrbNet data
     MED_DATA_IN        => med_data_out(15 downto 0),
     MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
     MED_DATAREADY_IN   => med_dataready_out(0),
@@ -562,7 +565,7 @@ THE_SODA_INPUT : med_ecp3_sfp_sync
     CTRL_DEBUG         => (others => '0')
    );      
 
-   
+
 ---------------------------------------------------------------------------
 -- The Soda Slave
 ---------------------------------------------------------------------------         
@@ -595,7 +598,7 @@ THE_SODA_INPUT : med_ecp3_sfp_sync
 ---------------------------------------------------------------------------
 -- Test Connector
 ---------------------------------------------------------------------------    
-  TEST_LINE(15 downto 0) <= (others => '0');
+  TEST_LINE(15 downto 0) <= med_stat_debug(15 downto 0);
 
 ---------------------------------------------------------------------------
 -- Test Circuits
diff --git a/soda_source/trb3_periph_sodasource.vhd b/soda_source/trb3_periph_sodasource.vhd
index dddc764..5b95bff 100644
--- a/soda_source/trb3_periph_sodasource.vhd
+++ b/soda_source/trb3_periph_sodasource.vhd
@@ -561,7 +561,7 @@ THE_SODA_SOURCE : med_ecp3_sfp_sync
 ---------------------------------------------------------------------------
 -- Test Connector
 ---------------------------------------------------------------------------    
---  TEST_LINE(15 downto 0) <= (others => '0');
+ TEST_LINE(15 downto 0) <= med_stat_debug(79 downto 64);
 ---------------------------------------------------------------------------
 -- Test Circuits
 ---------------------------------------------------------------------------