From: Jan Michel Date: Wed, 12 Feb 2014 16:38:19 +0000 (+0100) Subject: latest version of start design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3e2e77de17888ca816be8e6a17a38f44a196a0c3;p=trb3.git latest version of start design --- diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf index 14b11e7..efeac68 100644 --- a/base/trb3_periph_ada.lpf +++ b/base/trb3_periph_ada.lpf @@ -87,7 +87,7 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# -# SYSCONFIG MCCLK_FREQ = 20; + SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; diff --git a/hadesstart/config.vhd b/hadesstart/config.vhd index fbc5c24..0243ff6 100644 --- a/hadesstart/config.vhd +++ b/hadesstart/config.vhd @@ -10,19 +10,21 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ ---Include GbE logic +--TDC settings constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; constant NUM_TDC_CHANNELS_POWER2: integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons constant USE_DOUBLE_EDGE : integer := c_YES; --use only every fourth input as in HPTDC high precision mode constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES; - + --Include SPI on AddOn connector constant INCLUDE_SPI : integer := c_YES; --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; +--number of real inputs to the FPGA + constant PHYSICAL_INPUTS : integer := 16; --Run wih 125 MHz instead of 100 MHz constant USE_125_MHZ : integer := c_NO; --not implemented yet! diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index ab58a3e..3471433 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -482,7 +482,7 @@ begin THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 10, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"a000", others => x"0000"), + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0) ) port map( @@ -729,13 +729,13 @@ end generate; gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate THE_TRIG_LOGIC : input_to_trigger_logic generic map( - INPUTS => 16, + INPUTS => PHYSICAL_INPUTS, OUTPUTS => 4 ) port map( CLK => clk_100_i, - INPUT => inputs_i(15 downto 0), + INPUT => inputs_i(PHYSICAL_INPUTS-1 downto 0), OUTPUT => trig_out, DATA_IN => trig_din, @@ -782,7 +782,7 @@ end generate; CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels STATUS_REG_NR => 20, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + TDC_VERSION => x"151", -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map ( @@ -884,5 +884,7 @@ end generate; -- Trigger on a TDC Channel FPGA5_COMM(10 downto 7) <= trig_out; - + FPGA5_COMM(6 downto 3) <= (others => 'Z'); + FPGA5_COMM(1) <= 'Z'; + end architecture;