From: Jan Michel <j.michel@gsi.de>
Date: Tue, 23 Jun 2020 14:41:59 +0000 (+0200)
Subject: change dirich project to new Serdes files
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3f8de7da3b9d10aff33298e6336de423c20f01ca;p=dirich.git

change dirich project to new Serdes files
---

diff --git a/dirich/dirich.prj b/dirich/dirich.prj
index b0f7c89..f7dee80 100644
--- a/dirich/dirich.prj
+++ b/dirich/dirich.prj
@@ -136,9 +136,11 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
 #add_file -verilog -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0_softlogic.v"
 #add_file -vhdl -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0.vhd"
 #add_file -vhdl -lib work "diamond/pcs/pcs.vhd"
-add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0_softlogic.v"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd"
-add_file -vhdl -lib work "../cores/pcs.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+
+
 
 #TrbNet Endpoint
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"