From: hadaq Date: Tue, 22 Jan 2013 19:37:48 +0000 (+0000) Subject: keep current working status3 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=3f9b65ee3ff58fa6635b747e6218cc51df6296db;p=trb3.git keep current working status3 --- diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index b0a92aa..2fd8581 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -96,7 +96,8 @@ architecture Behavioral of nx_timestamp_fifo_read is signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal register_fifo_status : std_logic_vector(31 downto 0); + + signal reset_ctr : std_logic; signal frame_clock_ctr_inc_r : std_logic; begin @@ -353,7 +354,8 @@ begin fifo_out(8), fifo_new_frame, register_fifo_data, - frame_sync_wait_done + frame_sync_wait_done, + reset_ctr ) variable fifo_tag_given : std_logic_vector(3 downto 0); @@ -396,7 +398,10 @@ begin when S_SYNC_RESYNC => rs_sync_reset_x <= '1'; frame_clock_ctr_inc_s_x <= '1'; - nx_frame_resync_ctr_x <= nx_frame_resync_ctr + 1; + if (reset_ctr = '0') then + nx_frame_resync_ctr_x <= nx_frame_resync_ctr + 1; + end if; + frame_sync_wait_ctr_x <= x"14"; NEXT_STATE_SYNC <= S_SYNC_WAIT; @@ -408,21 +413,17 @@ begin end if; end case; + + if (reset_ctr = '1') then + nx_frame_resync_ctr_x <= (others => '0'); + end if; + end process PROC_SYNC_TO_NX_FRAME; ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- - register_fifo_status(0) <= fifo_full; - register_fifo_status(1) <= fifo_empty; - register_fifo_status(2) <= fifo_data_valid; - register_fifo_status(3) <= fifo_new_frame; - register_fifo_status(15 downto 4) <= (others => '0'); - register_fifo_status(23 downto 16) <= nx_frame_resync_ctr; - register_fifo_status(30 downto 24) <= (others => '0'); - register_fifo_status(31) <= nx_frame_synced; - -- Give status info to the TRB Slow Control Channel PROC_FIFO_REGISTERS: process(CLK_IN) begin @@ -433,37 +434,53 @@ begin slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; frame_clock_ctr_inc_r <= '0'; + reset_ctr <= '0'; else slv_data_out_o <= (others => '0'); - slv_ack_o <= '1'; + slv_ack_o <= '0'; slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; frame_clock_ctr_inc_r <= '0'; + reset_ctr <= '0'; if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => - slv_data_out_o <= register_fifo_data; + slv_data_out_o <= register_fifo_data; + slv_ack_o <= '1'; when x"0001" => - slv_data_out_o <= register_fifo_status; + slv_data_out_o(0) <= fifo_full; + slv_data_out_o(1) <= fifo_empty; + slv_data_out_o(3 downto 2) <= (others => '0'); + slv_data_out_o(4) <= fifo_data_valid; + slv_data_out_o(5) <= fifo_new_frame; + slv_data_out_o(30 downto 6) <= (others => '0'); + slv_data_out_o(31) <= nx_frame_synced; + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(7 downto 0) <= nx_frame_resync_ctr; + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + slv_unknown_addr_o <= '1'; end case; elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0001" => frame_clock_ctr_inc_r <= '1'; + slv_ack_o <= '1'; + + when x"0002" => + reset_ctr <= '1'; + slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; end case; - else - slv_ack_o <= '0'; end if; end if; end if; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index d8e69b8..3ba2ca9 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -12,6 +12,7 @@ entity nx_trigger_generator is TRIGGER_OUT : out std_logic; TS_RESET_OUT : out std_logic; + TESTPULSE_OUT : out std_logic; -- Slave bus SLV_READ_IN : in std_logic; @@ -40,12 +41,13 @@ architecture Behavioral of nx_trigger_generator is signal trigger_o_x : std_logic; signal ts_reset_o : std_logic; signal ts_reset_o_x : std_logic; + signal testpulse_o_x : std_logic; + signal testpulse_o : std_logic; type STATES is (S_IDLE, - S_WAIT_TS_RESET, S_NEXT_CYCLE, - S_SET_TRIGGER, - S_WAIT_TRIGGER + S_SET_TESTPULSE, + S_WAIT_TRIGGER_END ); signal STATE, NEXT_STATE : STATES; @@ -56,7 +58,7 @@ architecture Behavioral of nx_trigger_generator is signal slv_ack_o : std_logic; signal reg_trigger_period : unsigned(15 downto 0); - signal reg_trigger_length : unsigned(15 downto 0); + signal reg_testpulse_length : unsigned(15 downto 0); signal reg_trigger_num_cycles : unsigned(7 downto 0); signal reg_reset_on : std_logic; @@ -92,12 +94,14 @@ begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then trigger_o <= '0'; + testpulse_o <= '0'; ts_reset_o <= '0'; wait_timer_init <= (others => '0'); trigger_cycle_ctr <= (others => '0'); STATE <= S_IDLE; else trigger_o <= trigger_o_x; + testpulse_o <= testpulse_o_x; ts_reset_o <= ts_reset_o_x; wait_timer_init <= wait_timer_init_x; trigger_cycle_ctr <= trigger_cycle_ctr_x; @@ -109,10 +113,14 @@ begin PROC_TRIGGER_OUT: process(STATE, start_cycle, reg_trigger_num_cycles, + reg_trigger_period, + reg_reset_on, + reg_testpulse_length, wait_timer_done ) begin trigger_o_x <= '0'; + testpulse_o_x <= '0'; ts_reset_o_x <= '0'; wait_timer_init_x <= (others => '0'); trigger_cycle_ctr_x <= trigger_cycle_ctr; @@ -121,10 +129,10 @@ begin when S_IDLE => if (start_cycle = '1') then trigger_cycle_ctr_x <= reg_trigger_num_cycles; - if reg_reset_on = '1' then + if (reg_reset_on = '1') then ts_reset_o_x <= '1'; wait_timer_init_x <= reg_trigger_period; - NEXT_STATE <= S_WAIT_TS_RESET; + NEXT_STATE <= S_WAIT_TRIGGER_END; else NEXT_STATE <= S_NEXT_CYCLE; end if; @@ -132,34 +140,33 @@ begin NEXT_STATE <= S_IDLE; end if; - when S_WAIT_TS_RESET => - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_TS_RESET; - else - NEXT_STATE <= S_NEXT_CYCLE; - end if; - when S_NEXT_CYCLE => if (trigger_cycle_ctr > 0) then + trigger_o_x <= '1'; trigger_cycle_ctr_x <= trigger_cycle_ctr - 1; - wait_timer_init_x <= reg_trigger_length; - NEXT_STATE <= S_SET_TRIGGER; + if (reg_testpulse_length > 0) then + wait_timer_init_x <= reg_testpulse_length; + NEXT_STATE <= S_SET_TESTPULSE; + else + wait_timer_init_x <= reg_trigger_period; + NEXT_STATE <= S_WAIT_TRIGGER_END; + end if; else - NEXT_STATE <= S_IDLE; + NEXT_STATE <= S_IDLE; end if; - when S_SET_TRIGGER => - trigger_o_x <= '1'; + when S_SET_TESTPULSE => + testpulse_o_x <= '1'; if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_TRIGGER; + NEXT_STATE <= S_SET_TESTPULSE; else - wait_timer_init_x <= reg_trigger_period - reg_trigger_length; - NEXT_STATE <= S_WAIT_TRIGGER; + wait_timer_init_x <= reg_trigger_period - reg_testpulse_length; + NEXT_STATE <= S_WAIT_TRIGGER_END; end if; - when S_WAIT_TRIGGER => + when S_WAIT_TRIGGER_END => if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_TRIGGER; + NEXT_STATE <= S_WAIT_TRIGGER_END; else NEXT_STATE <= S_NEXT_CYCLE; end if; @@ -177,7 +184,7 @@ begin if( RESET_IN = '1' ) then reg_trigger_period <= x"00ff"; reg_trigger_num_cycles <= x"01"; - reg_trigger_length <= x"000a"; + reg_testpulse_length <= (others => '0'); reg_reset_on <= '0'; slv_data_out_o <= (others => '0'); slv_no_more_data_o <= '0'; @@ -203,7 +210,7 @@ begin reg_trigger_num_cycles <= unsigned(SLV_DATA_IN(7 downto 0)); slv_ack_o <= '1'; when x"0003" => - reg_trigger_length <= unsigned(SLV_DATA_IN(15 downto 0)); + reg_testpulse_length <= unsigned(SLV_DATA_IN(15 downto 0)); slv_ack_o <= '1'; when x"0004" => reg_reset_on <= SLV_DATA_IN(0); @@ -225,7 +232,7 @@ begin slv_ack_o <= '1'; when x"0003" => slv_data_out_o(15 downto 0) <= - std_logic_vector(reg_trigger_length); + std_logic_vector(reg_testpulse_length); slv_ack_o <= '1'; when x"0004" => slv_data_out_o(0) <= reg_reset_on; @@ -249,6 +256,7 @@ begin -- Trigger Output TRIGGER_OUT <= trigger_o; TS_RESET_OUT <= ts_reset_o; + TESTPULSE_OUT <= testpulse_o; -- Slave Bus SLV_DATA_OUT <= slv_data_out_o; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index 8771524..8f04494 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -37,10 +37,8 @@ end entity; architecture Behavioral of nx_trigger_handler is signal start_cycle : std_logic; - signal trigger_cycle_ctr : unsigned(7 downto 0); - signal trigger_cycle_ctr_x : unsigned(7 downto 0); - signal wait_timer_init : unsigned(15 downto 0); - signal wait_timer_init_x : unsigned(15 downto 0); + signal wait_timer_init : unsigned(9 downto 0); + signal wait_timer_init_x : unsigned(9 downto 0); signal wait_timer_done : std_logic; signal trigger_o : std_logic; signal trigger_o_x : std_logic; @@ -61,7 +59,7 @@ architecture Behavioral of nx_trigger_handler is signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal reg_timestamp_hold_delay : unsigned(15 downto 0); + signal reg_timestamp_hold_delay : unsigned(9 downto 0); begin @@ -76,7 +74,7 @@ begin -- Timer nx_timer_1: nx_timer generic map ( - CTR_WIDTH => 16 + CTR_WIDTH => 10 ) port map ( CLK_IN => CLK_IN, @@ -123,8 +121,12 @@ begin when S_IDLE => if (TRIGGER_IN = '1') then trigger_o_x <= '1'; - wait_timer_init_x <= reg_timestamp_hold_delay; - NEXT_STATE <= S_WAIT_HOLD; + if (reg_timestamp_hold_delay > 0) then + wait_timer_init_x <= reg_timestamp_hold_delay; + NEXT_STATE <= S_WAIT_HOLD; + else + NEXT_STATE <= S_WAIT_TRIGGER_RELEASE; + end if; else trigger_busy_o_x <= '0'; NEXT_STATE <= S_IDLE; @@ -133,7 +135,7 @@ begin when S_WAIT_HOLD => if (wait_timer_done = '1') then timestamp_hold_o_x <= '1'; - NEXT_STATE <= S_IDLE; + NEXT_STATE <= S_WAIT_TRIGGER_RELEASE; else NEXT_STATE <= S_WAIT_HOLD ; end if; @@ -161,37 +163,39 @@ begin slv_unknown_addr_o <= '0'; start_cycle <= '0'; slv_ack_o <= '0'; - reg_timestamp_hold_delay <= x"00ff"; + reg_timestamp_hold_delay <= (others => '0'); else slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; start_cycle <= '0'; - + if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0000" => - reg_timestamp_hold_delay <= SLV_DATA_IN(15 downto 0); + reg_timestamp_hold_delay <= SLV_DATA_IN(9 downto 0); slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + end case; elsif (SLV_READ_IN = '1') then case SLV_ADDR_IN is + when x"0000" => - slv_data_out_o(15 downto 0) <= + slv_data_out_o(9 downto 0) <= std_logic_vector(reg_timestamp_hold_delay); - slv_data_out_o(31 downto 16) <= (others => '0'); + slv_data_out_o(31 downto 10) <= (others => '0'); slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + end case; - else - slv_ack_o <= '0'; end if; end if; end if; diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 34d5ddd..e101e6a 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -116,7 +116,8 @@ architecture Behavioral of nXyter_FEE_board is signal timestamp_hold : std_logic; signal trigger_busy : std_logic; - -- Testpulse Generator + -- Trigger Generator + signal trigger : std_logic; signal nx_testpulse_o : std_logic; begin @@ -133,8 +134,9 @@ begin DEBUG_LINE_OUT(6) <= timestamp_hold; DEBUG_LINE_OUT(7) <= nx_token_return; DEBUG_LINE_OUT(8) <= nx_nomore_data; - DEBUG_LINE_OUT(9) <= trigger_busy; - DEBUG_LINE_OUT(15 downto 10) <= (others => '0'); + DEBUG_LINE_OUT(9) <= trigger; + DEBUG_LINE_OUT(10) <= trigger_busy; + DEBUG_LINE_OUT(15 downto 11) <= (others => '0'); ------------------------------------------------------------------------------- -- Port Maps @@ -166,7 +168,7 @@ begin PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler 1 => 0, -- I2C master - 2 => 1, -- Timestamp Fifo + 2 => 2, -- Timestamp Fifo 3 => 0, -- Data Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator @@ -218,8 +220,8 @@ begin BUS_WRITE_ENABLE_OUT(2) => slv_write(2), BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+0) => slv_addr(2*16+0), - BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open, + BUS_ADDR_OUT(2*16+1 downto 2*16) => slv_addr(2*16+1 downto 2*16), + BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open, BUS_TIMEOUT_OUT(2) => open, BUS_DATAREADY_IN(2) => slv_ack(2), BUS_WRITE_ACK_IN(2) => slv_ack(2), @@ -399,8 +401,6 @@ begin DEBUG_OUT => open ); --- DEBUG_LINE_OUT(15) <= nx_testpulse_o; - ------------------------------------------------------------------------------- -- Data Buffer FIFO ------------------------------------------------------------------------------- @@ -484,7 +484,7 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - TRIGGER_IN => nx_testpulse_o, + TRIGGER_IN => trigger, TRIGGER_RELEASE_IN => trigger_release, TRIGGER_OUT => trigger_ack, TIMESTAMP_HOLD_OUT => timestamp_hold, @@ -497,7 +497,7 @@ begin SLV_ACK_OUT => slv_ack(7), SLV_NO_MORE_DATA_OUT => slv_no_more_data(7), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7), - -- DEBUG_OUT(14 downto 0) => DEBUG_LINE_OUT(14 downto 0) + -- DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => open ); @@ -509,8 +509,9 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - TRIGGER_OUT => nx_testpulse_o, + TRIGGER_OUT => trigger, TS_RESET_OUT => nx_ts_reset_2, + TESTPULSE_OUT => nx_testpulse_o, SLV_READ_IN => slv_read(5), SLV_WRITE_IN => slv_write(5), SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), @@ -529,7 +530,7 @@ begin ------------------------------------------------------------------------------- nx_ts_reset_o <= nx_ts_reset_1 or nx_ts_reset_2; NX_RESET_OUT <= not nx_ts_reset_o; - NX_TESTPULSE_OUT <= not nx_testpulse_o; + NX_TESTPULSE_OUT <= nx_testpulse_o; ------------------------------------------------------------------------------- -- I2C Signals diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 16adf19..e3e87a4 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -366,6 +366,7 @@ component nx_trigger_generator RESET_IN : in std_logic; TRIGGER_OUT : out std_logic; TS_RESET_OUT : out std_logic; + TESTPULSE_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0);