From: Tobias Weber <toweber86@gmail.com>
Date: Thu, 19 Jul 2018 13:28:44 +0000 (+0200)
Subject: because modelsim wants it
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=402c2c757e0c419066753ecb9896f7abbdb41f94;p=trb3.git

because modelsim wants it
---

diff --git a/mupix/Mupix8/sources/Datapath/DataMuxWithConversion.vhd b/mupix/Mupix8/sources/Datapath/DataMuxWithConversion.vhd
index 2e44e82..c8bddb2 100644
--- a/mupix/Mupix8/sources/Datapath/DataMuxWithConversion.vhd
+++ b/mupix/Mupix8/sources/Datapath/DataMuxWithConversion.vhd
@@ -217,7 +217,6 @@ begin
             fifo_rden(fifo_sel_reg)        <= '1';
             increase_counter(fifo_sel_reg) <= '1';
             -- width conversion
-            conversioncounter              <= conversioncounter + 1;
             data_shift(1)                  <= data_shift(0);
             data_shift(0)                  <= data_select;
             if empty_delay = "11" then
@@ -225,12 +224,15 @@ begin
             end if;
             case conversioncounter is   -- also controls fifo readout
               when 0 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren <= '0';
                 dataout   <= (others => '0');
               when 1 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren <= '1';
                 dataout   <= data_shift(0)(c_mupixhitsize - 1 downto 8);
               when 2 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren <= '1';
                 if empty_delay = "11" then
                   dataout <= data_shift(1)(7 downto 0) & padding_0;
@@ -239,6 +241,7 @@ begin
                 end if;
                 fifo_rden(fifo_sel_reg) <= '0';
               when 3 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren <= '1';
                 if empty_delay = "11" then
                   dataout <= data_shift(1)(15 downto 0) & padding_1;
@@ -247,6 +250,7 @@ begin
                 end if;
                 fifo_rden(fifo_sel_reg) <= '0';
               when 4 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren <= '1';
                 if empty_delay = "11" then
                   dataout <= data_shift(1)(23 downto 0) & padding_2;
@@ -255,6 +259,7 @@ begin
                 end if;
                 fifo_rden(fifo_sel_reg) <= '0';
               when 5 =>
+                conversioncounter              <= conversioncounter + 1;
                 buff_wren               <= '1';
                 dataout                 <= data_shift(1)(31 downto 0);
                 fifo_rden(fifo_sel_reg) <= '0';