From: hadeshyp Date: Tue, 30 Mar 2010 14:07:34 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~313 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4072eb7715b8f54773522512a778473c38894d84;p=trbnet.git *** empty log message *** --- diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 13dac12..1826a47 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -50,4 +50,25 @@ entity handler_data is DEBUG_OUT : out std_logic_vector(31 downto 0) ); -end entity; \ No newline at end of file +end entity; + +--------------------------------------------------------------------------- +-- LVL1 Info FiFo +--------------------------------------------------------------------------- +-- 15 - 0 : trigger number +-- 23 - 16 : trigger code +-- 27 - 24 : trigger type +--Fifo has an internal output register. Output is valid two clock cycles after read + +--------------------------------------------------------------------------- +-- Data FiFo +--------------------------------------------------------------------------- +-- 31 - 0 : FEE data +-- 35 - 32 : trigger number 3..0 + + +architecture handler_data_arch of handler_data is + +begin + +end architecture; diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index c8c9cf2..b0f85e9 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -6,9 +6,15 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; +-- Missing: +-- Missing event check +-- wrong length of words in fifo check +-- speed-up? 2 cycles instead of 3 + + entity handler_ipu is generic( - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1 + DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 ); port( CLOCK : in std_logic; @@ -35,10 +41,317 @@ entity handler_ipu is IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - --Debug DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; +architecture handler_ipu_arch of handler_ipu is + + type cnt10_DAT_t is array (DATA_INTERFACE_NUMBER-1 downto 0) of unsigned(15 downto 0); + type fsm_state_t is (IDLE, WAIT_FOR_LENGTH, GOT_LENGTH, WAITING_FOR_EVENT, SEND_DHDR, READ_DATA, END_READOUT); + signal current_state, next_state : fsm_state_t; + signal state_bits : std_logic_vector(3 downto 0); + + signal error_not_found, next_error_not_found : std_logic; + signal error_sync : std_logic; + signal error_missing, next_error_missing : std_logic; + signal error_not_configured : std_logic; + signal lvl1_fifo_read, next_lvl1_fifo_read : std_logic; + + signal hdr_fifo_read, next_hdr_fifo_read : std_logic; + signal hdr_fifo_valid_read, next_hdr_fifo_valid_read : std_logic; + signal last_hdr_fifo_valid_read : std_logic; + signal first_fifo_read, next_first_fifo_read : std_logic; + + signal dat_fifo_read : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal dat_fifo_select, next_dat_fifo_select : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal dat_fifo_finished : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal dat_fifo_read_length : cnt10_DAT_t; + signal dat_fifo_valid_read, next_dat_fifo_valid_read : std_logic; + + signal ipu_dataready_i, next_ipu_dataready_i : std_logic; + signal ipu_data_i, next_ipu_data_i : std_logic_vector(31 downto 0); + signal ipu_finished_i, next_ipu_finished_i : std_logic; + signal ipu_error_pattern_i : std_logic_vector(31 downto 0); + signal ipu_length_i : std_logic_vector(15 downto 0); + + signal total_length, next_total_length : unsigned(15 downto 0); + + signal dat_fifo_number, next_dat_fifo_number : integer range 0 to DATA_INTERFACE_NUMBER-1; + + + +begin +--------------------------------------------------------------------------- +-- State Machine +--------------------------------------------------------------------------- + THE_FSM_REG : process(CLOCK) + begin + if rising_edge(CLOCK) then + if RESET = '1' then + current_state <= IDLE; + lvl1_fifo_read <= '0'; + hdr_fifo_read <= '0'; + else + current_state <= next_state; + error_not_found <= next_error_not_found; + error_missing <= next_error_missing; + lvl1_fifo_read <= next_lvl1_fifo_read; + hdr_fifo_read <= next_hdr_fifo_read; + ipu_finished_i <= next_ipu_finished_i; + ipu_dataready_i <= next_ipu_dataready_i; + ipu_data_i <= next_ipu_data_i; + dat_fifo_select <= next_dat_fifo_select; + first_fifo_read <= next_first_fifo_read; + dat_fifo_number <= next_dat_fifo_number; + end if; + end if; + end process; + + + THE_FSM : process(current_state, error_not_found, IPU_START_READOUT_IN, DAT_HDR_DATA_EMPTY_IN, + DAT_HDR_DATA_IN, last_hdr_fifo_valid_read, ipu_dataready_i, IPU_READ_IN, + DAT_HDR_DATA_EMPTY_IN, error_missing, dat_fifo_valid_read, next_dat_fifo_number, + dat_fifo_finished, dat_fifo_number, ipu_dataready_i) + begin + next_state <= current_state; + next_error_not_found <= error_not_found; + next_error_missing <= error_missing; + next_hdr_fifo_read <= '0'; + next_lvl1_fifo_read <= '0'; + next_ipu_data_i <= (others => '0'); + next_ipu_dataready_i <= '0'; + next_ipu_finished_i <= '0'; + next_first_fifo_read <= '0'; + next_dat_fifo_number <= dat_fifo_number; + + case current_state is + when IDLE => + if IPU_START_READOUT_IN = '1' then + next_state <= WAIT_FOR_LENGTH; + next_lvl1_fifo_read <= '1'; + next_hdr_fifo_read <= '1'; + next_error_not_found <= '0'; + next_error_missing <= '0'; + next_dat_fifo_number <= 0; + end if; + + when WAIT_FOR_LENGTH => + if or_all(DAT_DATA_EMPTY_IN) = '1' or DAT_HDR_DATA_EMPTY_IN = '1' then + next_state <= WAITING_FOR_EVENT; + else + next_state <= GOT_LENGTH; + end if; + + when GOT_LENGTH => + if last_hdr_fifo_valid_read = '1' then + next_state <= SEND_DHDR; + end if; + --missing: compare data flags and hdr fifo data + + when SEND_DHDR => + next_ipu_data_i <= x"0" & DAT_HDR_DATA_IN(27 downto 0); + next_ipu_dataready_i <= '1'; + if ipu_dataready_i = '1' and IPU_READ_IN = '1' then + next_state <= READ_DATA; + next_dat_fifo_number <= 0; + next_first_fifo_read <= not dat_fifo_finished(0); + next_ipu_dataready_i <= '0'; + end if; + + when READ_DATA => + if dat_fifo_finished(dat_fifo_number) = '1' and IPU_READ_IN = '1' then + if dat_fifo_number = DATA_INTERFACE_NUMBER-1 then + next_state <= END_READOUT; + else + next_dat_fifo_number <= dat_fifo_number + 1; + next_first_fifo_read <= not dat_fifo_finished(next_dat_fifo_number); + end if; + end if; + next_ipu_dataready_i <= dat_fifo_valid_read or (ipu_dataready_i and not IPU_READ_IN); + next_ipu_data_i <= DAT_DATA_IN(dat_fifo_number*32+31 downto dat_fifo_number*32); + + when END_READOUT => + next_ipu_finished_i <= '1'; + if IPU_START_READOUT_IN = '0' then + next_state <= IDLE; + end if; + + when WAITING_FOR_EVENT => + --CTS request came, but no data in Fifo yet + next_error_not_found <= '1'; + end case; + end process; + + PROC_DAT_FIFO_SELECT : process(next_dat_fifo_number, next_state) + begin + next_dat_fifo_select <= (others => '0'); + if next_state = READ_DATA then + next_dat_fifo_select(next_dat_fifo_number) <= '1'; + end if; + end process; + +--------------------------------------------------------------------------- +-- Data Fifo Handling +--------------------------------------------------------------------------- + gen_fifo_read : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + + --Read signal for data fifos + dat_fifo_read(i) <= dat_fifo_select(i) and ((IPU_READ_IN and ipu_dataready_i) or first_fifo_read) and not dat_fifo_finished(i); + + + --Count words read from data fifos + PROC_DAT_FIFO_COUNT : process(CLOCK) + begin + if rising_edge(CLOCK) then + if hdr_fifo_valid_read = '1' then + dat_fifo_read_length(i) <= unsigned(DAT_HDR_DATA_IN(i*18+9 downto i*18)); + elsif dat_fifo_read(i) = '1' then + dat_fifo_read_length(i) <= dat_fifo_read_length(i) - to_unsigned(1,1); + end if; + end if; + end process; + + + --Compare counter to read value from hdr_fifo and set finished signal + PROC_DAT_FIFO_FINISHED : process(CLOCK) + begin + if rising_edge(CLOCK) then + if hdr_fifo_valid_read = '1' then + dat_fifo_finished(i) <= '0'; + elsif (dat_fifo_read_length(i) = to_unsigned(1,10) and dat_fifo_read(i) = '1') + or dat_fifo_read_length(i) = 0 then + dat_fifo_finished(i) <= '1'; + end if; + end if; + end process; + + end generate; + + PROC_DAT_FIFO_VALID_READ : process(CLOCK) + begin + if rising_edge(CLOCK) then + next_dat_fifo_valid_read <= or_all(dat_fifo_read and dat_fifo_select) and not or_all(DAT_DATA_EMPTY_IN and dat_fifo_select); + dat_fifo_valid_read <= next_dat_fifo_valid_read; + end if; + end process; + + +--------------------------------------------------------------------------- +-- Header fifo read +--------------------------------------------------------------------------- + PROC_HDR_FIFO_VALID_READ : process(CLOCK) + begin + if rising_edge(CLOCK) then + next_hdr_fifo_valid_read <= hdr_fifo_read and not DAT_HDR_DATA_EMPTY_IN; + hdr_fifo_valid_read <= next_hdr_fifo_valid_read; + last_hdr_fifo_valid_read <= hdr_fifo_valid_read; + if last_hdr_fifo_valid_read = '1' then + total_length <= next_total_length; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- Some hand-written adders (gives a bit better results...) +--------------------------------------------------------------------------- + gen_add_1 : if DATA_INTERFACE_NUMBER = 1 generate + next_total_length <= (dat_fifo_read_length(0)); + end generate; + gen_add_2 : if DATA_INTERFACE_NUMBER = 2 generate + next_total_length <= ((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))); + end generate; + gen_add_3 : if DATA_INTERFACE_NUMBER = 3 generate + next_total_length <= ((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + + (dat_fifo_read_length(2)); + end generate; + gen_add_4 : if DATA_INTERFACE_NUMBER = 4 generate + next_total_length <= ((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + + ((dat_fifo_read_length(2)) + (dat_fifo_read_length(3))); + end generate; + gen_add_5 : if DATA_INTERFACE_NUMBER = 5 generate + next_total_length <= ((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + + ((dat_fifo_read_length(2)) + (dat_fifo_read_length(3))) + + ((dat_fifo_read_length(4))); + end generate; + gen_add_6 : if DATA_INTERFACE_NUMBER = 6 generate + next_total_length <= ((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + + ((dat_fifo_read_length(2)) + (dat_fifo_read_length(3))) + + ((dat_fifo_read_length(4)) + (dat_fifo_read_length(5))); + end generate; + gen_add_7 : if DATA_INTERFACE_NUMBER = 7 generate + next_total_length <= (((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + + ((dat_fifo_read_length(2)) + (dat_fifo_read_length(3)))) + + (((dat_fifo_read_length(4)) + (dat_fifo_read_length(5))) + + ((dat_fifo_read_length(6))); + end generate; + + +--------------------------------------------------------------------------- +-- Compare Event Information +--------------------------------------------------------------------------- + + PROC_COMPARE_NUMBER : process(CLOCK) + begin + if rising_edge(CLOCK) then + if current_state = IDLE then + error_sync <= '0'; + elsif dat_fifo_valid_read = '1' then + for i in 0 to NUMBER_OF_ADC-1 loop + if DAT_HDR_DATA_IN(3 downto 0) /= DAT_DATA_FLAGS_IN(dat_fifo_number*4+3 downto dat_fifo_number*4+0) then + error_sync <= '1'; + end if; + end loop; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- Connection to IPU Handler +--------------------------------------------------------------------------- + IPU_DATAREADY_OUT <= ipu_dataready_i; + IPU_DATA_OUT <= ipu_data_i; + IPU_LENGTH_OUT <= ipu_length_i; + IPU_ERROR_PATTERN_OUT <= ipu_error_pattern_i; + IPU_READOUT_FINISHED_OUT <= ipu_finished_i; + + ipu_length_i <= std_logic_vector(total_length); + + ADC_HDR_DATA_READ_OUT <= (others => hdr_fifo_read); + ADC_DATA_READ_OUT <= dat_fifo_read; + +--------------------------------------------------------------------------- +-- Error and Status Bits +--------------------------------------------------------------------------- + ipu_error_pattern_i(19 downto 0) <= (others => '0'); + ipu_error_pattern_i(20) <= error_not_found; --event not found + ipu_error_pattern_i(21) <= error_missing; --part of data missing + ipu_error_pattern_i(22) <= error_sync; --severe sync problem + ipu_error_pattern_i(23) <= error_not_configured; --FEE not configured + ipu_error_pattern_i(31 downto 24) <= (others => '0'); + + error_not_configured <= '0'; + + +--------------------------------------------------------------------------- +-- Debug +--------------------------------------------------------------------------- + state_bits <= x"0" when current_state = IDLE + else x"1" when current_state = WAIT_FOR_LENGTH + else x"2" when current_state = GOT_LENGTH + else x"3" when current_state = SEND_DHDR + else x"4" when current_state = READ_DATA + else x"5" when current_state = END_READOUT + else x"F"; + + DEBUG_OUT( 3 downto 0) <= state_bits; + DEBUG_OUT(11 downto 4) <= (others => '0'); + DEBUG_OUT(12) <= error_not_found; + DEBUG_OUT(13) <= error_missing; + DEBUG_OUT(14) <= error_sync; + DEBUG_OUT(15) <= error_not_configured; + + +end architecture; \ No newline at end of file diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index ef89779..29648d9 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -36,4 +36,11 @@ entity handler_lvl1 is --Debug DEBUG_OUT : out std_logic_vector (15 downto 0) ); -end entity; \ No newline at end of file +end entity; + + +architecture handler_lvl1_arch of handler_lvl1 is + +begin + +end architecture; \ No newline at end of file diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index a50e55e..e1c3954 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -22,11 +22,11 @@ entity handler_trigger_and_data is --To Endpoint --Timing Trigger (registered) - LVL1_TIMING_TRG_IN : in std_logic; + LVL1_VALID_TRIGGER_IN : in std_logic; LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --LVL1_handler connection + LVL1_TRG_DATA_VALID_IN : in std_logic; LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_RECEIVED_IN : in std_logic; LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); @@ -46,13 +46,7 @@ entity handler_trigger_and_data is IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --To FEE - --Trigger to FEE - FEE_TIMING_TRIGGER_OUT : out std_logic; --timing trigger (registered) - FEE_INT_TRG_NUMBER : out std_logic_vector(15 downto 0); --internal trigger counter, valid with timing trigger - FEE_TRG_RECEIVED_OUT : out std_logic; --TRG Info valid & FEE busy - FEE_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); --trigger type - FEE_TRG_INFO_OUT : out std_logic_vector(23 downto 0); --further trigger details - FEE_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --trigger number + --FEE to Trigger FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); @@ -62,6 +56,9 @@ entity handler_trigger_and_data is FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + --Status Registers + STATUS_OUT : out std_logic_vector(127 downto 0); + --Debug DEBUG_LVL1_HANDLER_OUT : out std_logic_vector(31 downto 0); DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); @@ -73,6 +70,9 @@ end entity; --Data inputs are read from 0 to MAX - 0 will always come first, MAX is always last. --To add debug information in front or behind the data, simply configure one more data port than needed for data +--data buffer threshold has to be set to fifo_depth - max_event_size - 2 when TRG_RELEASE_AFTER_DATA_FINISH = c_YES or +--fifo_depth - 2*max_event_size - 2 when TRG_RELEASE_AFTER_DATA_FINISH = c_NO + architecture handler_trigger_and_data_arch of handler_trigger_and_data is @@ -101,40 +101,6 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is begin - ------------------------------------------------------------------------ --- The LVL1 Handler ------------------------------------------------------------------------ - THE_LVL1_HANDLER : handler_lvl1 - port map( - RESET => RESET, - CLOCK => CLOCK, - --Timing Trigger - LVL1_TIMING_TRG_IN => LVL1_TIMING_TRG_IN, - LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, - --LVL1_handler connection - LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, - LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_IN, - LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, - LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, - LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, - LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, - LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT, - --FEE logic / Data Handler - FEE_TIMING_TRIGGER_OUT => fee_timing_trigger, - FEE_TRG_RECEIVED_OUT => fee_trg_received, - FEE_TRG_TYPE_OUT => fee_trg_type, - FEE_TRG_INFO_OUT => fee_trg_info, - FEE_TRG_CODE_OUT => fee_trg_code, - FEE_TRG_NUMBER_OUT => fee_trg_number, - FEE_RELEASE_IN => fee_trg_release, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits, - --Debug - DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT - ); - - - ----------------------------------------------------------------------- -- Combine all trg_release and trg_statusbits to one ----------------------------------------------------------------------- @@ -160,7 +126,6 @@ begin end if; end process; - ----------------------------------------------------------------------- -- The data handler, containing all buffers ----------------------------------------------------------------------- @@ -243,6 +208,19 @@ begin +----------------------------------------------------------------------- +-- Connect Outputs +----------------------------------------------------------------------- + LVL1_TRG_RELEASE_OUT <= fee_trg_release; + LVL1_ERROR_PATTERN_OUT <= fee_trg_statusbits; + + FEE_TIMING_TRIGGER_OUT <= LVL1_TIMING_TRG_IN; + FEE_TRG_NUMBER_OUT <= LVL1_TRG_NUMBER_IN; + FEE_TRG_RECEIVED_OUT <= LVL1_TRG_RECEIVED_IN; + FEE_TRG_TYPE_OUT <= LVL1_TRG_TYPE_IN; + FEE_TRG_INFO_OUT <= LVL1_TRG_INFORMATION_IN; + + end architecture; \ No newline at end of file diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 88890f5..abdab36 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -27,73 +27,78 @@ entity trb_net16_endpoint_hades_full is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers - REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers - REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR - REGIO_USE_VAR_ENDPOINT_ID: integer range c_NO to c_YES := c_NO; - CLOCK_FREQUENCY : integer range 1 to 200 := 100 + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic := '1'; + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received - MED_STAT_OP_IN : in std_logic_vector(15 downto 0); - MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) - -- LVL1 trigger APL - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_RECEIVED_OUT : out std_logic; - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; - LVL1_TRG_RELEASE_IN : in std_logic := '0'; - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only --Data Port - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); --start strobe - IPU_START_READOUT_OUT: out std_logic; + IPU_START_READOUT_OUT : out std_logic; --detector data, equipped with DHDR - IPU_DATA_IN : in std_logic_vector (31 downto 0); - IPU_DATAREADY_IN : in std_logic; + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_IN : in std_logic; + IPU_READOUT_FINISHED_IN : in std_logic; --will be low every second cycle due to 32bit -> 16bit conversion - IPU_READ_OUT : out std_logic; - IPU_LENGTH_IN : in std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- Slow Control Data Port @@ -126,7 +131,6 @@ entity trb_net16_endpoint_hades_full is REGIO_ONEWIRE_MONITOR_OUT : out std_logic; REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); - TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger @@ -150,76 +154,76 @@ end trb_net16_endpoint_hades_full; architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full is -signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); -signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); - -signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); -signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); - -signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); -signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); - -signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); -signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); - --- for the connection to the multiplexer -signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); -signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); - -signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); -signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_IN : std_logic_vector(7 downto 0); - -signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); -signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); -signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0); -signal buf_APL_READ_OUT : std_logic_vector(3 downto 0); -signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0); -signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0); -signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0); -signal buf_APL_SEND_IN : std_logic_vector(3 downto 0); -signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); -signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); -signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0); -signal buf_APL_READ_IN : std_logic_vector(3 downto 0); -signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0); -signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0); -signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0); -signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0); - -signal MY_ADDRESS : std_logic_vector(15 downto 0); - -signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); -signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); -signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); -signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); -signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); -signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); - -signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0); - -signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); -signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - -signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); -signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); -signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); -signal buf_IDRAM_WR_IN : std_logic; -signal reset_no_link : std_logic; -signal ONEWIRE_DATA : std_logic_vector(15 downto 0); -signal ONEWIRE_ADDR : std_logic_vector(2 downto 0); -signal ONEWIRE_WRITE : std_logic; + signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); + signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); + + signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); + signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); + + signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); + signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); + + signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); + signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); + + -- for the connection to the multiplexer + signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); + signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); + + signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); + signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); + signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); + signal MED_IO_READ_IN : std_logic_vector(7 downto 0); + + signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0); + signal buf_APL_READ_OUT : std_logic_vector(3 downto 0); + signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0); + signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0); + signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0); + signal buf_APL_SEND_IN : std_logic_vector(3 downto 0); + signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0); + signal buf_APL_READ_IN : std_logic_vector(3 downto 0); + signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0); + signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0); + signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0); + signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0); + + signal MY_ADDRESS : std_logic_vector(15 downto 0); + + signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); + signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); + signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); + signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); + signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); + signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); + + signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0); + + signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); + signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); + signal buf_IDRAM_WR_IN : std_logic; + signal reset_no_link : std_logic; + signal ONEWIRE_DATA : std_logic_vector(15 downto 0); + signal ONEWIRE_ADDR : std_logic_vector(2 downto 0); + signal ONEWIRE_WRITE : std_logic; signal buf_COMMON_STAT_REG_STROBE : std_logic_vector((std_COMSTATREG)-1 downto 0); signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0); @@ -242,6 +246,10 @@ signal ONEWIRE_WRITE : std_logic; signal trigger_number_match : std_logic; signal buf_TIMER_TICKS_OUT : std_logic_vector(1 downto 0); + signal buf_LVL1_VALID_TIMING_TRG_OUT : std_logic; + signal buf_LVL1_VALID_NOTIMING_TRG_OUT : std_logic; + signal buf_LVL1_INVALID_TRG_OUT : std_logic; + begin reset_no_link <= MED_STAT_OP_IN(14) or RESET; @@ -537,7 +545,7 @@ begin IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, IDRAM_WR_IN => buf_IDRAM_WR_IN, MY_ADDRESS_OUT => MY_ADDRESS, - TRIGGER_MONITOR => TRIGGER_MONITOR_IN, + TRIGGER_MONITOR => TRG_TIMING_TRG_RECEIVED_IN, GLOBAL_TIME => GLOBAL_TIME_OUT, LOCAL_TIME => LOCAL_TIME_OUT, TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT, @@ -788,7 +796,7 @@ begin if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then got_timing_trigger <= '0'; - elsif TRIGGER_MONITOR_IN = '1' or + elsif TRG_TIMING_TRG_RECEIVED_IN = '1' or (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then got_timing_trigger <= '1'; end if; @@ -803,35 +811,43 @@ begin buf_LVL1_ERROR_PATTERN_IN(17) <= not got_timing_trigger or LVL1_ERROR_PATTERN_IN(17); end process; + buf_LVL1_VALID_TIMING_TRG_OUT <= TRG_TIMING_TRG_RECEIVED_IN; + buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger + and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7); + buf_LVL1_INVALID_TRG_OUT <= '0'; ------------------------------------------------- -- Connect Outputs ------------------------------------------------- - LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; - LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT; - LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT; - LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT; - LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT; - LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num; - - COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE; - COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE; - STAT_REG_STROBE <= buf_STAT_REG_STROBE; - CTRL_REG_STROBE <= buf_CTRL_REG_STROBE; - - TIMER_TICKS_OUT <= buf_TIMER_TICKS_OUT; - - buf_CTRL_GEN <= IOBUF_CTRL_GEN; - REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT; - - STAT_DEBUG_1 <= REGIO_REGIO_STAT; - STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); - STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16); - STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3); - STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3); - STAT_DEBUG_2(15 downto 12) <= (others => '0'); - STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32); + LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; + LVL1_VALID_TIMING_TRG_OUT <= buf_LVL1_VALID_TIMING_TRG_OUT; + LVL1_VALID_NOTIMING_TRG_OUT <= buf_LVL1_VALID_NOTIMING_TRG_OUT; + LVL1_INVALID_TRG_OUT <= buf_LVL1_INVALID_TRG_OUT; + + LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT; + LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT; + LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT; + LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT; + LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num; + + COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE; + COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE; + STAT_REG_STROBE <= buf_STAT_REG_STROBE; + CTRL_REG_STROBE <= buf_CTRL_REG_STROBE; + + TIMER_TICKS_OUT <= buf_TIMER_TICKS_OUT; + + buf_CTRL_GEN <= IOBUF_CTRL_GEN; + REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT; + + STAT_DEBUG_1 <= REGIO_REGIO_STAT; + STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); + STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16); + STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3); + STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3); + STAT_DEBUG_2(15 downto 12) <= (others => '0'); + STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32); end architecture; diff --git a/trb_net16_trigger.vhd b/trb_net16_trigger.vhd index 6cca02e..ab4e4cd 100644 --- a/trb_net16_trigger.vhd +++ b/trb_net16_trigger.vhd @@ -145,56 +145,51 @@ begin end if; end process; - --save data from api while sending trailer in secure mode --- SECURE_GEN: if SECURE_MODE = 1 generate - CLK_REG2: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_TRG_ERROR_PATTERN_IN <= (others => '0'); - elsif TRG_RELEASE_IN = '1' then - buf_TRG_ERROR_PATTERN_IN <= TRG_ERROR_PATTERN_IN; - end if; + CLK_REG2: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_TRG_ERROR_PATTERN_IN <= (others => '0'); + elsif TRG_RELEASE_IN = '1' then + buf_TRG_ERROR_PATTERN_IN <= TRG_ERROR_PATTERN_IN; end if; - end process; --- end generate; + end if; + end process; --- SECURE_GEN2: if SECURE_MODE = 0 generate --- buf_TRG_ERROR_PATTERN_IN <= TRG_ERROR_PATTERN_IN; --- end generate; - --count packets - REG_TRANSFER_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - transfer_counter <= c_H0; - elsif buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - if transfer_counter = c_max_word_number then - transfer_counter <= (others => '0'); - else - transfer_counter <= transfer_counter + 1; - end if; +--count packets + REG_TRANSFER_COUNTER : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + transfer_counter <= c_H0; + elsif buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then + if transfer_counter = c_max_word_number then + transfer_counter <= (others => '0'); + else + transfer_counter <= transfer_counter + 1; end if; end if; - end process; + end if; + end process; - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - INT_DATA_OUT <= buf_INT_DATA_OUT; - INT_PACKET_NUM_OUT <= transfer_counter; - INT_OUT_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_INT_DATA_OUT <= "0000000000000" & TYPE_TRM; - buf_INT_DATAREADY_OUT <= '0'; - else - buf_INT_DATA_OUT <= next_INT_DATA_OUT; - buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; - end if; + INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; + INT_DATA_OUT <= buf_INT_DATA_OUT; + INT_PACKET_NUM_OUT <= transfer_counter; + + INT_OUT_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_INT_DATA_OUT <= "0000000000000" & TYPE_TRM; + buf_INT_DATAREADY_OUT <= '0'; + else + buf_INT_DATA_OUT <= next_INT_DATA_OUT; + buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; end if; - end process; + end if; + end process; --this holds the current packet type process(CLK) diff --git a/trb_net_components.vhd b/trb_net_components.vhd index f973ec5..ba9e56b 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -289,7 +289,7 @@ package trb_net_components is component trb_net16_endpoint_hades_full is generic ( USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - IBUF_DEPTH : channel_config_t := (1,6,6,6); + IBUF_DEPTH : channel_config_t := (6,6,6,6); FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); @@ -303,72 +303,78 @@ package trb_net_components is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers - REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers - REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := "0000000000000001"; + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR - REGIO_USE_VAR_ENDPOINT_ID: integer range c_NO to c_YES := c_NO; - CLOCK_FREQUENCY : integer range 1 to 200 := 100 + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received - MED_STAT_OP_IN : in std_logic_vector(15 downto 0); - MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only - -- LVL1 trigger APL - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_RECEIVED_OUT : out std_logic; - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; - LVL1_TRG_RELEASE_IN : in std_logic := '0'; - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --Data Port - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); --start strobe - IPU_START_READOUT_OUT: out std_logic; + IPU_START_READOUT_OUT : out std_logic; --detector data, equipped with DHDR - IPU_DATA_IN : in std_logic_vector (31 downto 0); - IPU_DATAREADY_IN : in std_logic; + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_IN : in std_logic; + IPU_READOUT_FINISHED_IN : in std_logic; --will be low every second cycle due to 32bit -> 16bit conversion - IPU_READ_OUT : out std_logic; - IPU_LENGTH_IN : in std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- Slow Control Data Port @@ -376,9 +382,8 @@ package trb_net_components is REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - - COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0); - COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); --following ports only used when using internal data port @@ -397,24 +402,22 @@ package trb_net_components is REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; REGIO_IDRAM_WR_IN : in std_logic := '0'; - REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; REGIO_ONEWIRE_MONITOR_OUT : out std_logic; REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); - TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick - --Debugging & Status information STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); STAT_DEBUG_1 : out std_logic_vector (31 downto 0); STAT_DEBUG_2 : out std_logic_vector (31 downto 0); MED_STAT_OP : out std_logic_vector (15 downto 0); - CTRL_MPLEX : in std_logic_vector (31 downto 0); - IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) );