From: Tobias Weber <toweber86@gmail.com>
Date: Mon, 7 Aug 2017 13:45:06 +0000 (+0200)
Subject: Miscallenous changes. Having issues with persisting timing violations showing up... 
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=40787069fed1a1632afc9028492b6b3cd6704ef4;p=trb3.git

Miscallenous changes. Having issues with persisting timing violations showing up every second compile.
---

diff --git a/base/trb3_periph_mupix.lpf b/base/trb3_periph_mupix.lpf
index 35f9d96..2c802ed 100644
--- a/base/trb3_periph_mupix.lpf
+++ b/base/trb3_periph_mupix.lpf
@@ -373,4 +373,4 @@ IOBUF GROUP "not_connected_group" IO_TYPE=LVCMOS25;
 ###########################################################
 ##Relax some timing constraints
 ###########################################################
-MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
+#MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd
index b2643cf..ca593b1 100644
--- a/mupix/sources/MuPix3_interface.vhd
+++ b/mupix/sources/MuPix3_interface.vhd
@@ -70,7 +70,6 @@ architecture RTL of mupix_interface is
   signal sensor_id                  : std_logic_vector(31 downto 0) := (others => '0');
 
   signal triggering            : std_logic := '0';
-  signal busy_r                : std_logic := '0';
   signal continousread         : std_logic := '0';
   signal readnow               : std_logic := '0';
   signal readmanual            : std_logic := '0';
@@ -229,8 +228,7 @@ begin
   -----------------------------------------------------------------------------
   --Readout Control
   -----------------------------------------------------------------------------
-
-  process(rst, clk)
+  process(clk)
   begin
     if rising_edge(clk) then
       if(rst = '1') then
@@ -273,7 +271,7 @@ begin
   -----------------------------------------------------------------------------
   --MuPix 3/4/6 Readout Statemachine
   -----------------------------------------------------------------------------
-  ro_statemachine : process(rst, clk)
+  ro_statemachine : process(clk)
   begin
     if rising_edge(clk) then
       if(rst = '1') then
@@ -500,27 +498,25 @@ begin
               delcounter   <= "00000100";
               eventcounter <= eventcounter + 1;
             end if;
-          when others =>
-            testoutro(8) <= '1';
-            state        <= waiting;
         end case;
       end if;
     end if;
   end process;
 
-  tsgen :
-  process(rst, clk)
-  begin
-    if(rst = '1') then
-      mupixcontrol.timestamps <= (others => '0');
-    elsif(clk'event and clk = '1') then
-      if(timestampcontrolbits(8) = '1') then
-        mupixcontrol.timestamps <= graycount;
-      else
-        mupixcontrol.timestamps <= timestampcontrolbits(7 downto 0);
-      end if;
-    end if;
-  end process;
+  tsgen : process(clk)
+	begin
+		if rising_edge(clk) then
+			if (rst = '1') then
+				mupixcontrol.timestamps <= (others => '0');
+			else
+				if (timestampcontrolbits(8) = '1') then
+					mupixcontrol.timestamps <= graycount;
+				else
+					mupixcontrol.timestamps <= timestampcontrolbits(7 downto 0);
+				end if;
+			end if;
+		end if;
+	end process;
 
   resetgraycounter <= timestampreset_in or timestampcontrolbits(9);
 
diff --git a/mupix/sources/TriggerHandler.vhd b/mupix/sources/TriggerHandler.vhd
index d77ca36..9de6ca1 100644
--- a/mupix/sources/TriggerHandler.vhd
+++ b/mupix/sources/TriggerHandler.vhd
@@ -73,7 +73,6 @@ architecture behavioral of TriggerHandler is
   signal timing_trigger_int      : std_logic                     := '0';
   signal timing_trigger_edge     : std_logic_vector(1 downto 0)  := "00";
   signal status_trigger_int      : std_logic                     := '0';
-  signal calibration_trigger_int : std_logic                     := '0';
   signal fast_clear_int          : std_logic                     := '0';
   signal flush_buffer_int        : std_logic                     := '0';
   signal trigger_busy_int        : std_logic                     := '0';
@@ -86,7 +85,6 @@ architecture behavioral of TriggerHandler is
   signal fee_trg_release_int     : std_logic                     := '0';
   signal fee_trg_statusbit_int   : std_logic_vector(31 downto 0) := (others => '0');
 --event buffer
-  signal fast_clear_o            : std_logic                     := '0';
 
 --registers
   signal reset_trigger_counters : std_logic := '0';
diff --git a/mupix/sources/graycounter.vhd b/mupix/sources/graycounter.vhd
index a15ad76..2722c1a 100644
--- a/mupix/sources/graycounter.vhd
+++ b/mupix/sources/graycounter.vhd
@@ -52,9 +52,9 @@ begin
     end if;
   end process clock_divider_proc;
 
-  process(clk, reset)
+  process(clk)
   begin
-    if (clk'event and clk = '1') then
+    if rising_edge(clk) then
       if (reset = '1') then
         no_ones_below(0) <= '1';
         counter_reg      <= (others => '0');