From: Michael Boehmer Date: Tue, 16 Aug 2022 09:03:52 +0000 (+0200) Subject: DLM stuff starts X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=42270790cf8afa8d6d6a5afa1c3cba39fb1c6cbb;p=trb3sc.git DLM stuff starts --- diff --git a/gbe_hub/par.p2t b/gbe_hub/par.p2t index 7825494..5d6b5e1 100644 --- a/gbe_hub/par.p2t +++ b/gbe_hub/par.p2t @@ -1,7 +1,7 @@ -w -l 5 -s 12 --t 1 # seed setting here! # 34 32 +-t 33 # seed setting here! # 34 32 -c 1 -e 2 -i 15 diff --git a/gbe_hub/trb3sc_gbe_hub.lpf b/gbe_hub/trb3sc_gbe_hub.lpf index f37c8d3..8e150d1 100644 --- a/gbe_hub/trb3sc_gbe_hub.lpf +++ b/gbe_hub/trb3sc_gbe_hub.lpf @@ -1,11 +1,9 @@ # locate the PCS blocks -#LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSD"; - -LOCATE COMP "THE_GBE_MED_RAW_PCSA/gbe_serdes/PCSD_INST" SITE "PCSA"; -LOCATE COMP "THE_GBE_MED_RAW_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB"; -LOCATE COMP "THE_GBE_MED_RAW_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; -LOCATE COMP "THE_GBE_MED_RAW_PCSD/gbe_serdes/PCSD_INST" SITE "PCSD"; +LOCATE COMP "THE_GBE_MED_PCSA/gbe_serdes/PCSD_INST" SITE "PCSA"; +LOCATE COMP "THE_GBE_MED_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB"; +LOCATE COMP "THE_GBE_MED_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; +LOCATE COMP "THE_GBE_MED_PCSD/gbe_serdes/PCSD_INST" SITE "PCSD"; # main frequencies diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index ef67a3c..dafb69d 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -55,7 +55,6 @@ add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" @@ -103,15 +102,11 @@ add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" add_file -vhdl -lib work "../../TOMcat/code/tomcat_tools.vhd" add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" -#add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -#add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -#add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" -#add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" @@ -132,7 +127,6 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -162,29 +156,17 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd" -#Hub -#add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" -#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" -#add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" -#add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" - #GbE -#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/gbe_med_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd" + add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" @@ -195,18 +177,18 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/inserter.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_inserter.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_remover.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd" @@ -218,9 +200,6 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/sgl_ctrl.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_raw.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_fifo.vhd" - add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index f23c779..94a9900 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -193,7 +193,22 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal tick_ms_int : std_logic; signal tick_us_int : std_logic; + + signal aux_reg : std_logic_vector(31 downto 0); + +-- signal dlm_found_int : std_logic; + signal dlm_inject_int : std_logic; + signal dlm_tx_data_int : std_logic_vector(7 downto 0); +-- signal dlm_rx_data_int : std_logic_vector(7 downto 0); + + signal dlm_ctr : unsigned(23 downto 0); + signal rst_dlm_ctr_x : std_logic; + signal rst_dlm_ctr : std_logic; + + signal dlm_tag_ctr : unsigned(7 downto 0); + signal inc_dlm_tag : std_logic; + begin -- SerDes usage: @@ -237,9 +252,42 @@ begin LED_RED_OUT => LED_RJ_RED(1), LED_GREEN_OUT => LED_RJ_GREEN(1) ); - + +--------------------------------------------------------------------------- +-- DLM timing generator +--------------------------------------------------------------------------- + THE_DLM_SEND_PROC: process( clk_sys ) + begin + if( rising_edge(clk_sys) ) then + inc_dlm_tag <= rst_dlm_ctr; + rst_dlm_ctr <= rst_dlm_ctr_x; + if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then + dlm_ctr <= (others => '0'); + elsif( aux_reg(31) = '1' ) then + dlm_ctr <= dlm_ctr + 1; + end if; + end if; + end process THE_DLM_SEND_PROC; + + rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0'; + + -- DLM "tag" for blinking LEDs :) + THE_DLM_TAG_CTR_PROC: process( clk_sys ) + begin + if( rising_edge(clk_sys) ) then + if( (reset_i = '1') or (aux_reg(31) = '0') ) then + dlm_tag_ctr <= (others => '0'); + elsif( inc_dlm_tag = '1' ) then + dlm_tag_ctr <= dlm_tag_ctr + 1; + end if; + end if; + end process THE_DLM_TAG_CTR_PROC; + + dlm_inject_int <= rst_dlm_ctr; + dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr); --------------------------------------------------------------------------- +-- FiFo controller --------------------------------------------------------------------------- THE_SGL_CTRL: entity sgl_ctrl port map( @@ -377,7 +425,8 @@ begin GSC_BUSY_IN => gsc_busy, -- reset MAKE_RESET_OUT => reset_via_gbe, - -- debug + -- debug signal aux_reg : std_logic_vector(31 downto 0); + STATUS_OUT => status, DEBUG_OUT => debug ); @@ -478,6 +527,14 @@ begin SCL_INOUT => open, --SI2C_SCL, -- Additional register ADDITIONAL_REG => additional_reg, + CTRL_REG => open, + AUX_REG => aux_reg, + -- Ethernet registers + FWD_MAC_OUT => open, + FWD_IP_OUT => open, + FWD_PORT_OUT => open, + -- Trigger + TRIGGER_OUT => open, --Slowcontrol BUS_RX => bustools_rx, BUS_TX => bustools_tx, @@ -498,7 +555,7 @@ begin --------------------------------------------------------------------------- -- PCSA is one port downlink (backplane) --------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSA: entity gbe_med_fifo + THE_GBE_MED_PCSA: entity gbe_med_fifo generic map( LINKS_ACTIVE => "0001" ) @@ -546,6 +603,12 @@ begin PCS_AN_READY_OUT(0) => open, -- for internal SCTRL LINK_ACTIVE_OUT(0) => open, -- for internal SCTRL TICK_MS_IN => tick_ms_int, + -- DLM + DLM_INJECT_IN => (others => '0'), + DLM_DATA_IN => (others => '0'), + DLM_FOUND_OUT => open, + DLM_DATA_OUT => open, + DLM_CLK_OUT => open, -- Debug STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32), DEBUG_OUT => open @@ -554,7 +617,7 @@ begin --------------------------------------------------------------------------- -- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon) --------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSB: entity gbe_med_fifo + THE_GBE_MED_PCSB: entity gbe_med_fifo generic map( LINKS_ACTIVE => "1111" ) @@ -639,6 +702,12 @@ begin RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, TICK_MS_IN => tick_ms_int, + -- DLM + DLM_INJECT_IN => (others => '0'), + DLM_DATA_IN => (others => '0'), + DLM_FOUND_OUT => open, + DLM_DATA_OUT => open, + DLM_CLK_OUT => open, -- Debug STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32), DEBUG_OUT => open @@ -647,7 +716,7 @@ begin --------------------------------------------------------------------------- -- PCSC is four ports downlink --------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo + THE_GBE_MED_PCSC: entity gbe_med_fifo generic map( LINKS_ACTIVE => "1111" ) @@ -732,6 +801,12 @@ begin RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, TICK_MS_IN => tick_ms_int, + -- DLM + DLM_INJECT_IN => (others => '0'), + DLM_DATA_IN => (others => '0'), + DLM_FOUND_OUT => open, + DLM_DATA_OUT => open, + DLM_CLK_OUT => open, -- Debug STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), DEBUG_OUT => open @@ -740,7 +815,7 @@ begin --------------------------------------------------------------------------- -- PCSD is one uplink / one downlink --------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSD: entity gbe_med_fifo + THE_GBE_MED_PCSD: entity gbe_med_fifo generic map( LINKS_ACTIVE => "0011", SNIFFER_PORT => 0 @@ -801,6 +876,12 @@ begin PCS_AN_READY_OUT(0) => open, -- for internal SCTRL LINK_ACTIVE_OUT(0) => link_active, -- for internal SCTRL TICK_MS_IN => tick_ms_int, + -- DLM + DLM_INJECT_IN => (others => '0'), + DLM_DATA_IN => (others => '0'), + DLM_FOUND_OUT => open, + DLM_DATA_OUT => open, + DLM_CLK_OUT => open, -- Debug STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32), DEBUG_OUT => open