From: Peter Lemmens Date: Tue, 13 Aug 2013 11:55:01 +0000 (+0200) Subject: soda-source written into the bus structure of trb3. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=422b05a88497f791dec53a752b544fbe5c3e0ca5;p=soda.git soda-source written into the bus structure of trb3. Register access is implemented making use of regIO-example (by Peter Schakel) controlling LEDs on trb3; i.e. slowcontrol is tested here. No more errors in Synplify so this should result in a downloadable and working firmware. First test is access to trb with trbcmd. ToDo next: - design/implement/test reply-checker - make new project for SODA-client or use conditional synthesis ("generate if") --- diff --git a/soda_source.ldf b/soda_source.ldf index 9e2ac23..4f9bd9f 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -11,6 +11,9 @@ + + + @@ -284,6 +287,18 @@ + + + + + + + + + + + + diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj index 8b20186..288ce95 100644 --- a/soda_source/soda_source_syn.prj +++ b/soda_source/soda_source_syn.prj @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09L-1 #-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Wed May 22 08:53:18 2013 +#-- Written on Thu Aug 8 09:58:23 2013 #project files @@ -103,6 +103,7 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_f add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/soda_source.vhd" #implementation: "soda_source" diff --git a/source/soda_components.vhd b/source/soda_components.vhd index 6af9fbe..2b63a24 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -76,20 +76,26 @@ package soda_components is --Internal Connection SODA_BURST_PULSE_IN : in std_logic := '0'; -- SODA_CMD_STROBE_IN : in std_logic := '0'; -- - SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others : '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit + SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic; - TX_DLM_OUT : out std_logic := '0'; -- - TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') + TX_DLM_OUT : out std_logic; + TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SODA_DATA_IN : in std_logic_vector(30 downto 0) := (others : '0'); - SODA_DATA_OUT : in std_logic_vector(30 downto 0) := (others : '0'); - SODA_ADDR : in std_logic_vector(30 downto 0) := (others : '0'); - SODA_READ : in std_logic := '0'; - SODA_WRITE : in std_logic := '0'; - SODA_ACK : in std_logic := '0' - ); + SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + SODA_READ_IN : in std_logic := '0'; + SODA_WRITE_IN : in std_logic := '0'; + SODA_ACK_OUT : out std_logic := '0'; + LEDS_ACT_OUT : out std_logic; + LEDS_OUT : out std_logic_vector(3 downto 0); + SPARE_LINE : in std_logic_vector(5 downto 0); + TEST_LINE : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); end component; component spi_flash_and_fpga_reload diff --git a/source/soda_d8crc8.vhd b/source/soda_d8crc8.vhd index b49827e..ff37754 100644 --- a/source/soda_d8crc8.vhd +++ b/source/soda_d8crc8.vhd @@ -31,7 +31,14 @@ library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all ; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; + entity soda_d8crc8 is port( CLOCK : in std_logic; diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd index 687a501..ec4f11a 100644 --- a/source/soda_packet_builder.vhd +++ b/source/soda_packet_builder.vhd @@ -2,7 +2,11 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; entity soda_packet_builder is port( @@ -22,18 +26,18 @@ end soda_packet_builder; architecture Behavioral of soda_packet_builder is -component soda_d8crc8 - port( - clock : in std_logic; - reset : in std_logic; - soc : in std_logic; - data : in std_logic_vector(7 downto 0); - data_valid : in std_logic; - eoc : in std_logic; - crc : out std_logic_vector(7 downto 0); - crc_valid : out std_logic - ); -end component; +--component soda_d8crc8 +-- port( +-- clock : in std_logic; +-- reset : in std_logic; +-- soc : in std_logic; +-- data : in std_logic_vector(7 downto 0); +-- data_valid : in std_logic; +-- eoc : in std_logic; +-- crc : out std_logic_vector(7 downto 0); +-- crc_valid : out std_logic +-- ); +--end component; -- constant c_K287 : std_logic_vector(7 downto 0) := x"FB"; diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd index 916464c..17ab0da 100644 --- a/source/soda_packet_handler.vhd +++ b/source/soda_packet_handler.vhd @@ -2,6 +2,11 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; entity soda_packet_handler is port( @@ -19,18 +24,18 @@ end soda_packet_handler; architecture Behavioral of soda_packet_handler is - component soda_d8crc8 - port( - clock : in std_logic; - reset : in std_logic; - soc : in std_logic; - data : in std_logic_vector(7 downto 0); - data_valid : in std_logic; - eoc : in std_logic; - crc : out std_logic_vector(7 downto 0); - crc_valid : out std_logic - ); - end component; +-- component soda_d8crc8 +-- port( +-- clock : in std_logic; +-- reset : in std_logic; +-- soc : in std_logic; +-- data : in std_logic_vector(7 downto 0); +-- data_valid : in std_logic; +-- eoc : in std_logic; +-- crc : out std_logic_vector(7 downto 0); +-- crc_valid : out std_logic +-- ); +-- end component; constant c_K287 : std_logic_vector(7 downto 0) := x"FB"; diff --git a/source/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd index 7cefc6d..5f76529 100644 --- a/source/soda_superburst_gen.vhd +++ b/source/soda_superburst_gen.vhd @@ -4,6 +4,11 @@ use ieee.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use ieee.std_logic_signed.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; entity soda_superburst_gen is generic( diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index ab3d2ff..d84ed9b 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -194,15 +194,16 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal sci2_data_out : std_logic_vector(7 downto 0); signal sci2_addr : std_logic_vector(8 downto 0); - --SODA + --SODA signal soda_ack : std_logic; signal soda_nack : std_logic; signal soda_write : std_logic; signal soda_read : std_logic; - signal soda_data_in : std_logic_vector(7 downto 0); - signal soda_data_out : std_logic_vector(7 downto 0); - signal soda_addr : std_logic_vector(8 downto 0); - + signal soda_data_in : std_logic_vector(31 downto 0); + signal soda_data_out : std_logic_vector(31 downto 0); + signal soda_addr : std_logic_vector(3 downto 0); + signal soda_leds : std_logic_vector(3 downto 0); + --TDC signal hit_in_i : std_logic_vector(63 downto 0); @@ -212,7 +213,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal rx_dlm_i : std_logic; signal tx_dlm_word : std_logic_vector(7 downto 0); signal rx_dlm_word : std_logic_vector(7 downto 0); - + --SODA signal rst_S : std_logic; signal clk_S : std_logic; @@ -224,6 +225,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal SOB_S : std_logic := '0'; signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); signal dlm_valid_S : std_logic; + begin --------------------------------------------------------------------------- -- Reset Generation @@ -406,8 +408,8 @@ THE_HUB : trb_net16_hub_base THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, others => 0) + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) ) port map( CLK => clk_sys_i, @@ -450,7 +452,7 @@ THE_HUB : trb_net16_hub_base BUS_DATAREADY_IN(1) => sci1_ack, BUS_WRITE_ACK_IN(1) => sci1_ack, BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', --SCI soda test Media Interface BUS_READ_ENABLE_OUT(2) => sci2_read, @@ -464,22 +466,21 @@ THE_HUB : trb_net16_hub_base BUS_DATAREADY_IN(2) => sci2_ack, BUS_WRITE_ACK_IN(2) => sci2_ack, BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => sci2_nack, + BUS_UNKNOWN_ADDR_IN(2) => sci2_nack, --soda Slow-control Interface BUS_READ_ENABLE_OUT(3) => soda_read, BUS_WRITE_ENABLE_OUT(3) => soda_write, - BUS_DATA_OUT(3*32+7 downto 3*32) => soda_data_in, - BUS_DATA_OUT(3*32+31 downto 3*32+8) => open, - BUS_ADDR_OUT(3*16+8 downto 3*16) => soda_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open, + BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in, + BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open, BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+7 downto 3*32) => soda_data_out, + BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out, BUS_DATAREADY_IN(3) => soda_ack, BUS_WRITE_ACK_IN(3) => soda_ack, BUS_NO_MORE_DATA_IN(3) => '0', BUS_UNKNOWN_ADDR_IN(3) => soda_nack, - + STAT_DEBUG => open ); @@ -569,48 +570,53 @@ THE_SYNC_LINK : med_ecp3_sfp_sync --------------------------------------------------------------------------- --- The Soda Source +-- The Soda Central --------------------------------------------------------------------------- - tx_dlm_i <= '0'; - tx_dlm_word <= x"00"; +-- tx_dlm_i <= '0'; +-- tx_dlm_word <= x"00"; - - superburst_gen : super_burst_generator - generic map(BURST_COUNT => 16) - port map( - SYSCLK => clk_sys_i, --clk_S, - RESET => reset_i, --rst_S, - CLEAR => '0', - CLK_EN => '0', - --Internal Connection - SODA_BURST_PULSE_IN => SOB_S, - START_OF_SUPERBURST => SOS_S, - SUPER_BURST_NR_OUT => super_burst_nr_S - ); - - packet_builder : soda_packet_builder - port map( - SYSCLK => clk_sys_i, --clk_S, - RESET => reset_i, --rst_S, - CLEAR => '0', - CLK_EN => '0', - --Internal Connection - SODA_CMD_STROBE_IN => soda_cmd_strobe_S, - START_OF_SUPERBURST => SOS_S, - SUPER_BURST_NR_IN => super_burst_nr_S, - SODA_CMD_WORD_IN => soda_cmd_word_S, - TX_DLM_OUT => dlm_valid_S, - TX_DLM_WORD_OUT => dlm_word_S - - ); +THE_SODA_SOURCE : soda_source + port map( + SYSCLK => clk_sys_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + SODA_BURST_PULSE_IN => SOB_S, + SODA_CMD_STROBE_IN => soda_cmd_strobe_S, + SODA_CMD_WORD_IN => soda_cmd_word_S, + + RX_DLM_WORD_IN => rx_dlm_word, + RX_DLM_IN => rx_dlm_i, + TX_DLM_OUT => tx_dlm_i, + TX_DLM_WORD_OUT => tx_dlm_word, + + SODA_DATA_IN => soda_data_in, + SODA_DATA_OUT => soda_data_out, + SODA_ADDR_IN => soda_addr, + SODA_READ_IN => soda_read, + SODA_WRITE_IN => soda_write, + SODA_ACK_OUT => soda_ack, + LEDS_ACT_OUT => open, + LEDS_OUT => soda_leds, + SPARE_LINE => open, + TEST_LINE => open, + STAT => open + ); +--end soda_source; + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); - LED_YELLOW <= '1'; - LED_GREEN <= not med_stat_op(9); - LED_RED <= not (med_stat_op(10) or med_stat_op(11)); +-- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); +-- LED_YELLOW <= '1'; +-- LED_GREEN <= not med_stat_op(9); +-- LED_RED <= not (med_stat_op(10) or med_stat_op(11)); + LED_ORANGE <= soda_leds(0); + LED_YELLOW <= soda_leds(1); + LED_GREEN <= soda_leds(2); + LED_RED <= soda_leds(3); --------------------------------------------------------------------------- -- Test Connector @@ -628,4 +634,4 @@ THE_SYNC_LINK : med_ecp3_sfp_sync -end trb3_periph_sodasource_arch; +end trb3_periph_sodasource_arch; \ No newline at end of file