From: Cahit Date: Fri, 15 Nov 2013 16:52:15 +0000 (+0100) Subject: changes for the review X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=42869f026df5986ef5df4c48e63f9053cc799d84;p=publication.git changes for the review --- diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf index df7d81b..ee493d7 100644 Binary files a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf and b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf differ diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex index feeadba..1ddb15e 100644 --- a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex +++ b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex @@ -118,8 +118,10 @@ successfully deployed. One key component of the TRB3 is the $64+1$ channel time-to-digital converter (TDC) implemented in the peripheral FPGAs of the TRB3 with a time precision -down to $7.2$\,ps on a single channel. It ``misuses'' FPGA resources (LUTs as -full-adders) as delay elements and can cope with burst hit rates of up to +down to $7.2$\,ps on a single channel. It ``misuses'' the carry chain lines +and the logic blocks along the lines as delay elements in order to generate +delay lines for fine time measurements. Each channel can save time information +for up to 127 hits per trigger and can cope with burst hit rates of up to $66$\,MHz. Owing to its flexible design, an application-specific trade-off between number of channels, time precision and dead-time can be achieved for each front-end design. Implementation details can be found in @@ -353,8 +355,9 @@ Finally, we present some planned or ongoing extensions of the platform: The detection of leading and trailing edge in a single TDC channel, which doubles the number of channels per board for timestamp and width measurements. This feature is highly desired for the -described charge-to-width front-end. The temperature independence of -the PaDiWa thresholds and of the TDC calibration is currently +described charge-to-width front-end. The dependency of the precision with the +temperature is discussed in \cite{ugur-nomeTDC2013}. The temperature +independency of the PaDiWa thresholds and of the TDC calibration is currently investigated. There are also several further front-end developments: Integration of the MuPix ASIC for the PANDA luminosity detector and the SPADIC ASIC for a TPC in Mainz. A $\sim50$ channel $10$\,bit @@ -381,6 +384,14 @@ Fellowship through GRK Symmetry Breaking (DFG/GRK 1581). in a Field Programmable Gate Array} \jinst{7}{2012}{C02004}. +\bibitem{ugur-nomeTDC2013} + C. U\u{g}ur, G. Korcyl, J. Michel, M. Penschuk and M. Traxler + \emph{264 Channel TDC Platform applying 65 channel high precision (7.2 ps + RMS) FPGA based TDCs}, Time-to-Digital Converters (NoMe TDC), + \href{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6658234&isnumber=6658224}{2013 + IEEE Nordic-Mediterranean Workshop on , vol., no., pp.1,5, 3-3 + Oct. 2013}. + \bibitem{ugur-twepp2012} C. U\u{g}ur, W. Koening, J. Michel, M. Palka and M. Traxler, \emph{Field programmable gate array based data