From: Ingo Froehlich Date: Wed, 28 Feb 2018 12:16:21 +0000 (+0100) Subject: w.i.p., IF X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=42fa09f1fb488fc49f38c703553e6110407df460;p=trbnet.git w.i.p., IF --- diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index c8409c2..b447a8f 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -47,7 +47,7 @@ end entity; architecture rx_control_arch of rx_control is -type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR, GET_CRC); +type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR, GET_CRC, GET_RETR); signal rx_state : rx_state_t; signal rx_state_bits : std_logic_vector(3 downto 0); signal rx_packet_num : std_logic_vector(2 downto 0); @@ -82,11 +82,17 @@ signal reg_rx_k_in : std_logic; signal reset_cnt : unsigned(7 downto 0); -signal crc_reset : std_logic; -signal crc_q : std_logic_vector(7 downto 0); -signal crc_en : std_logic; -signal crc_data : std_logic_vector(7 downto 0); - +signal crc_reset : std_logic; +signal crc_q : std_logic_vector(7 downto 0); +signal crc_en : std_logic; +signal crc_data : std_logic_vector(7 downto 0); +signal pulse_good : std_logic; +signal pulse_bad : std_logic; +signal got_pulse_good : std_logic := '0'; +signal got_pulse_bad : std_logic := '0'; +signal pulse_good_100 : std_logic; +signal pulse_bad_100 : std_logic; +signal waiting_for_retr : std_logic := '0'; begin @@ -94,9 +100,9 @@ begin -- Data to Endpoint ---------------------------------------------------------------------- - -ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -- when rising_edge(CLK_100); -buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100); + +ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (pulse_good_100 or got_pulse_good or pulse_bad_100 or got_pulse_bad); -- when rising_edge(CLK_100); +buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and (pulse_good_100 or got_pulse_good) when rising_edge(CLK_100); RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; RX_WRITE_OUT <= buf_rx_write_out; @@ -107,6 +113,16 @@ last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); process begin wait until rising_edge(CLK_100); + if pulse_good_100 = '1' then + got_pulse_good <= '1'; + elsif ct_fifo_empty = '1' then + got_pulse_good <= '0'; + end if; + if pulse_bad_100 = '1' then + got_pulse_bad <= '1'; + elsif ct_fifo_empty = '1' then + got_pulse_bad <= '0'; + end if; if RX_ALLOW_IN = '0' then rx_packet_num <= "100"; elsif buf_rx_write_out = '1' then @@ -167,7 +183,9 @@ PROC_RX_FSM : process begin idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); idle_hist_i(0) <= got_link_ready_i; crc_en <= '0'; - crc_reset <= '0'; + crc_reset <= '0'; + pulse_good <= '0'; + pulse_bad <= '0'; case rx_state is when SLEEP => @@ -199,6 +217,8 @@ PROC_RX_FSM : process begin rx_state <= START_RETR; when K_EOP => rx_state <= GET_CRC; + when K_BGN => + rx_state <= GET_RETR; when others => null; end case; else @@ -232,12 +252,23 @@ PROC_RX_FSM : process begin end if; when GET_CRC => --TODO: mitzaehlen, of CRC nach 5 16-Bit-Paketen kommt - crc_reset <= '1'; - rx_state <= FIRST; - if (crc_q = reg_rx_data_in) then - req_retr_i <= '1'; + -- alles wegwerfen bis neue retransmission kommt + crc_reset <= '1'; + rx_state <= FIRST; + if (crc_q = reg_rx_data_in and waiting_for_retr = '0') then -- CRC match + pulse_good <= '1'; + else + pulse_bad <= '1'; + if waiting_for_retr = '0' then + req_retr_i <= '1'; + waiting_for_retr <= '1'; + end if; end if; - + + when GET_RETR => + rx_state <= FIRST; + waiting_for_retr <= '0'; + when GET_DLM => rx_state_bits <= x"5"; rx_dlm_i <= '1'; @@ -315,6 +346,29 @@ REQUEST_RETRANSMIT_OUT_SYNC : pulse_sync PULSE_B_OUT => REQUEST_RETRANSMIT_OUT ); +PULSE_GOOD_SYNC : pulse_sync + port map( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_IN, + PULSE_A_IN => pulse_good, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => pulse_good_100 + ); + +PULSE_BAD_SYNC : pulse_sync + port map( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_IN, + PULSE_A_IN => pulse_bad, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => pulse_bad_100 + ); + + + + REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data diff --git a/media_interfaces/sync/tb/med_sync_tb.vhd b/media_interfaces/sync/tb/med_sync_tb.vhd index f6fea96..9884208 100644 --- a/media_interfaces/sync/tb/med_sync_tb.vhd +++ b/media_interfaces/sync/tb/med_sync_tb.vhd @@ -80,6 +80,7 @@ signal int2med_m, int2med_s : INT2MED; signal tx_data_m, tx_data_s, rx_data_m, rx_data_s : std_logic_vector(7 downto 0); signal tx_k_m, tx_k_s, rx_k_m, rx_k_s : std_logic; +signal do_once : std_logic := '0'; begin @@ -88,7 +89,17 @@ clear_m <= '0' after 51 ns; reset_s <= '0' after 201 ns; clear_s <= '0' after 51 ns; -rx_data_s <= transport tx_data_m after 250 ns; +process (tx_data_m) +begin + if (tx_data_m = x"11" and do_once = '0') then + rx_data_s(7 downto 1) <= transport tx_data_m(7 downto 1) after 250 ns; + rx_data_s(0) <= transport '0' after 250 ns; + do_once <= '1'; + else + rx_data_s <= transport tx_data_m after 250 ns; + end if; +end process; + rx_data_m <= transport tx_data_s after 250 ns; rx_k_s <= transport tx_k_m after 250 ns; rx_k_m <= transport tx_k_s after 250 ns; @@ -107,7 +118,32 @@ process begin int2med_m.data <= x"0000"; int2med_m.packet_num <= "000"; int2med_m.dataready <= '0'; - wait for 50 us; + wait for 30 us; + + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"affe"; + int2med_m.packet_num <= "100"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"affe"; + int2med_m.packet_num <= "000"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"affe"; + int2med_m.packet_num <= "001"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"affe"; + int2med_m.packet_num <= "010"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"affe"; + int2med_m.packet_num <= "011"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.dataready <= '0'; + int2med_m.data <= x"0000"; + wait for 1 us; wait until rising_edge(clk_100_m); wait for 1 ns; int2med_m.data <= x"1122"; int2med_m.packet_num <= "100"; @@ -130,6 +166,32 @@ process begin int2med_m.dataready <= '1'; wait until rising_edge(clk_100_m); wait for 1 ns; int2med_m.dataready <= '0'; + wait until rising_edge(clk_100_m); wait for 1 ns; + wait until rising_edge(clk_100_m); wait for 1 ns; + + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"dead"; + int2med_m.packet_num <= "100"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"dead"; + int2med_m.packet_num <= "000"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"dead"; + int2med_m.packet_num <= "001"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"dead"; + int2med_m.packet_num <= "010"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.data <= x"dead"; + int2med_m.packet_num <= "011"; + int2med_m.dataready <= '1'; + wait until rising_edge(clk_100_m); wait for 1 ns; + int2med_m.dataready <= '0'; + end process; diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index fdbc1a8..3e05dcf 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -351,7 +351,7 @@ begin if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) and ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' - and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then --TODO: Sync these 3 signals + and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' and load_eop = '0' then --TODO: Sync these 3 signals ram_read <= '1'; else ram_read <= '0';