From: Michael Boehmer Date: Fri, 8 Jul 2022 14:34:33 +0000 (+0200) Subject: FIFO on da way X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=43c41396b818aa86b52e085ab5544946280e2e14;p=trb3sc.git FIFO on da way --- diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index f0288aa..a3e21b3 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -239,6 +239,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_raw.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_fifo.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index cde1294..f61bb1a 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -120,7 +120,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal status : std_logic_vector(15 downto 0); - ---------------------------------------------------------------- + -- SerDes low level stuff signal tx_pll_lol_i : std_logic; signal tx_pll_lol_a_i : std_logic; signal tx_pll_lol_b_i : std_logic; @@ -131,7 +131,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal link_tx_ready_i : std_logic; signal status_raw : std_logic_vector(4 * 32 - 1 downto 0); - ---------------------------------------------------------------- + -- for SCRL endpoint (old style) signal mac_ready_conf : std_logic; signal mac_reconf : std_logic; signal mac_an_ready : std_logic; @@ -153,51 +153,18 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal mac_rx_eof : std_logic; signal mac_rx_err : std_logic; - signal fw_mac_rx_data_int : std_logic_vector(7 downto 0); - signal fw_mac_rx_wr_int : std_logic; - signal fw_mac_rx_eof_int : std_logic; - signal fw_mac_rx_err_int : std_logic; - signal fw_fifo_full_int : std_logic; - signal fw_fifo_wr_int : std_logic; - signal fw_fifo_data_int : std_logic_vector(8 downto 0); - signal fw_frame_req_int : std_logic; - signal fw_frame_ack_int : std_logic; - signal fw_frame_avail_int : std_logic; - signal fw_mac_tx_data_int : std_logic_vector(7 downto 0); - signal fw_mac_tx_read_int : std_logic; - signal fw_mac_fifoeof_int : std_logic; - signal fw_mac_fifoempty_int : std_logic; - signal fw_mac_fifoavail_int : std_logic; - signal fw_mac_ready_conf_int : std_logic; - signal fw_mac_reconf_int : std_logic; - signal fw_mac_an_ready_int : std_logic; - signal fw_link_active_int : std_logic; - signal fw_mac_tx_done_int : std_logic; - signal fw_mac_rx_fifofull_int : std_logic; - signal fw_frame_start_int : std_logic; - - signal bw_mac_rx_data_int : std_logic_vector(7 downto 0); - signal bw_mac_rx_wr_int : std_logic; - signal bw_mac_rx_eof_int : std_logic; - signal bw_mac_rx_err_int : std_logic; - signal bw_fifo_full_int : std_logic; - signal bw_fifo_wr_int : std_logic; - signal bw_fifo_data_int : std_logic_vector(8 downto 0); - signal bw_frame_req_int : std_logic; - signal bw_frame_ack_int : std_logic; - signal bw_frame_avail_int : std_logic; - signal bw_mac_tx_data_int : std_logic_vector(7 downto 0); - signal bw_mac_tx_read_int : std_logic; - signal bw_mac_fifoeof_int : std_logic; - signal bw_mac_fifoempty_int : std_logic; - signal bw_mac_fifoavail_int : std_logic; - signal bw_mac_ready_conf_int : std_logic; - signal bw_mac_reconf_int : std_logic; - signal bw_mac_an_ready_int : std_logic; - signal bw_link_active_int : std_logic; - signal bw_mac_tx_done_int : std_logic; - signal bw_mac_rx_fifofull_int : std_logic; - signal bw_frame_start_int : std_logic; + -- the new FIFO interface + signal fifo_data_rx : std_logic_vector(4 * 8 - 1 downto 0); + signal fifo_data_tx : std_logic_vector(4 * 8 - 1 downto 0); + signal fifo_full_rx : std_logic_vector(3 downto 0); + signal fifo_full_tx : std_logic_vector(3 downto 0); + signal fifo_wr_rx : std_logic_vector(3 downto 0); + signal fifo_wr_tx : std_logic_vector(3 downto 0); + signal fifo_start_rx : std_logic_vector(3 downto 0); + signal fifo_start_tx : std_logic_vector(3 downto 0); + signal frame_req_rx : std_logic_vector(3 downto 0); + signal frame_ack_rx : std_logic_vector(3 downto 0); + signal frame_avail_rx : std_logic_vector(3 downto 0); begin @@ -324,29 +291,6 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DEBUG_OUT => open ); --- DBG(0) <= mac_ready_conf; --- DBG(1) <= mac_reconf; --- DBG(2) <= mac_an_ready; --- DBG(3) <= mac_fifoavail; --- DBG(4) <= mac_fifoeof; --- DBG(5) <= mac_fifoempty; --- DBG(6) <= mac_rx_fifofull; --- DBG(14 downto 7) <= mac_tx_data; --- DBG(15) <= mac_tx_read; --- DBG(16) <= mac_tx_discrfrm; --- DBG(17) <= mac_tx_stat_en; --- -- MAC_TX_STATS_IN => mac_tx_stats, --- DBG(18) <= mac_tx_done; --- DBG(19) <= mac_rx_fifo_err; --- -- MAC_RX_STATS_IN => mac_rx_stats, --- DBG(27 downto 20) <= mac_rx_data; --- DBG(28) <= mac_rx_write; --- DBG(29) <= mac_rx_stat_en; --- DBG(30) <= mac_rx_eof; --- DBG(31) <= mac_rx_err; --- DBG(32) <= mac_rx_stats(18); -- control frame --- DBG(33) <= CLK_SUPPL_PCLK; - ------------------------------------------------------------------------------- -- SCTRL endpoint for GbE standalone ------------------------------------------------------------------------------- @@ -528,7 +472,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler --------------------------------------------------------------------------- -- PCSC is four ports downlink --------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSC: entity gbe_med_raw + THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo generic map( LINKS_ACTIVE => "1111" ) @@ -538,58 +482,19 @@ THE_CLOCK_RESET : entity work.clock_reset_handler CLK_SYS => clk_sys, CLK_125 => CLK_SUPPL_PCLK, CLK_125_RX => open, - -- MAC status and config - MAC_READY_CONF_OUT(0) => fw_mac_ready_conf_int, - MAC_READY_CONF_OUT(2 downto 1) => open, - MAC_READY_CONF_OUT(3) => bw_mac_ready_conf_int, - MAC_RECONF_IN(0) => fw_mac_reconf_int, - MAC_RECONF_IN(2 downto 1) => (others => '0'), - MAC_RECONF_IN(3) => bw_mac_reconf_int, - MAC_AN_READY_OUT(0) => fw_mac_an_ready_int, - MAC_AN_READY_OUT(2 downto 1) => open, - MAC_AN_READY_OUT(3) => bw_mac_an_ready_int, - -- MAC data interface - MAC_FIFOAVAIL_IN(0) => bw_mac_fifoavail_int, - MAC_FIFOAVAIL_IN(2 downto 1) => (others => '0'), - MAC_FIFOAVAIL_IN(3) => fw_mac_fifoavail_int, - MAC_FIFOEOF_IN(0) => bw_mac_fifoeof_int, - MAC_FIFOEOF_IN(2 downto 1) => (others => '0'), - MAC_FIFOEOF_IN(3) => fw_mac_fifoeof_int, - MAC_FIFOEMPTY_IN(0) => bw_mac_fifoempty_int, - MAC_FIFOEMPTY_IN(2 downto 1) => (others => '0'), - MAC_FIFOEMPTY_IN(3) => fw_mac_fifoempty_int, - MAC_RX_FIFOFULL_IN(0) => fw_mac_rx_fifofull_int, - MAC_RX_FIFOFULL_IN(2 downto 1) => (others => '0'), - MAC_RX_FIFOFULL_IN(3) => bw_mac_rx_fifofull_int, - -- MAC TX interface - MAC_TX_DATA_IN(7 downto 0) => bw_mac_tx_data_int, -- from TX_FIFO to C0 TX - MAC_TX_DATA_IN(23 downto 8) => (others => '0'), - MAC_TX_DATA_IN(31 downto 24) => fw_mac_tx_data_int, -- from TX_FIFO to C3 TX - MAC_TX_READ_OUT(0) => bw_mac_tx_read_int, - MAC_TX_READ_OUT(2 downto 1) => open, - MAC_TX_READ_OUT(3) => fw_mac_tx_read_int, - MAC_TX_DISCRFRM_OUT => open, - MAC_TX_STAT_EN_OUT => open, - MAC_TX_STATS_OUT => open, - MAC_TX_DONE_OUT(0) => bw_mac_tx_done_int, - MAC_TX_DONE_OUT(2 downto 1) => open, - MAC_TX_DONE_OUT(3) => fw_mac_tx_done_int, - -- MAC RX interface - MAC_RX_FIFO_ERR_OUT => open, - MAC_RX_STATS_OUT => open, - MAC_RX_DATA_OUT(7 downto 0) => fw_mac_rx_data_int, -- from C0 RX to RX_RB - MAC_RX_DATA_OUT(23 downto 8) => open, - MAC_RX_DATA_OUT(31 downto 24) => bw_mac_rx_data_int, -- from C3 RX to RX_RB - MAC_RX_WRITE_OUT(0) => fw_mac_rx_wr_int, - MAC_RX_WRITE_OUT(2 downto 1) => open, - MAC_RX_WRITE_OUT(3) => bw_mac_rx_wr_int, - MAC_RX_STAT_EN_OUT => open, - MAC_RX_EOF_OUT(0) => fw_mac_rx_eof_int, - MAC_RX_EOF_OUT(2 downto 1) => open, - MAC_RX_EOF_OUT(3) => bw_mac_rx_eof_int, - MAC_RX_ERROR_OUT(0) => fw_mac_rx_err_int, - MAC_RX_ERROR_OUT(2 downto 1) => open, - MAC_RX_ERROR_OUT(3) => bw_mac_rx_err_int, + -- FIFO interface RX + FIFO_DATA_OUT => fifo_data_rx, + FIFO_FULL_IN => fifo_full_rx, + FIFO_WR_OUT => fifo_wr_rx, + FRAME_REQ_IN => frame_req_rx, + FRAME_ACK_OUT => frame_ack_rx, + FRAME_AVAIL_OUT => frame_avail_rx, + FRAME_START_OUT => frame_start_rx, + -- FIFO interface TX + FIFO_FULL_OUT => fifo_full_tx, + FIFO_WR_IN => fifo_wr_tx, + FIFO_DATA_IN => fifo_data_tx, + FRAME_START_IN => frame_start_tx, -- SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(3), SD_PRSNT_N_IN(1) => HUB_MOD0(4), @@ -612,201 +517,67 @@ THE_CLOCK_RESET : entity work.clock_reset_handler STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), DEBUG_OUT => open ); - - DBG(3 downto 0) <= fw_mac_rx_data_int(3 downto 0); - DBG(7 downto 4) <= fw_mac_tx_data_int(3 downto 0); - DBG(11 downto 8) <= bw_mac_rx_data_int(3 downto 0); - DBG(15 downto 12) <= bw_mac_tx_data_int(3 downto 0); - DBG(16) <= fw_mac_rx_wr_int; - DBG(17) <= bw_mac_rx_wr_int; - DBG(18) <= fw_mac_tx_read_int; - DBG(19) <= bw_mac_tx_read_int; - DBG(20) <= fw_mac_rx_eof_int; - DBG(21) <= bw_mac_rx_eof_int; - DBG(22) <= fw_mac_fifoeof_int; - DBG(23) <= bw_mac_fifoeof_int; - DBG(24) <= fw_frame_start_int; - DBG(25) <= bw_frame_start_int; - DBG(26) <= fw_mac_fifoempty_int; - DBG(27) <= bw_mac_fifoempty_int; - DBG(28) <= fw_mac_rx_fifofull_int; - DBG(29) <= bw_mac_rx_fifofull_int; - DBG(30) <= fw_mac_an_ready_int; - DBG(31) <= bw_mac_an_ready_int; - DBG(32) <= clear; - DBG(33) <= CLK_SUPPL_PCLK; - --- DBG(7 downto 0) <= fw_mac_rx_data_int; --- DBG(8) <= fw_mac_rx_wr_int; --- DBG(9) <= fw_mac_rx_eof_int; --- DBG(10) <= fw_mac_rx_err_int; --- DBG(11) <= fw_mac_reconf_int; --- DBG(12) <= fw_mac_ready_conf_int; --- DBG(13) <= fw_mac_rx_fifofull_int; --- DBG(14) <= fw_mac_an_ready_int; --- DBG(15) <= '0'; --- DBG(23 downto 16) <= mac_rx_data; --- DBG(24) <= mac_rx_write; --- DBG(25) <= mac_rx_eof; --- DBG(26) <= mac_rx_err; --- DBG(27) <= mac_reconf; --- DBG(28) <= mac_ready_conf; --- DBG(29) <= mac_rx_fifofull; --- DBG(30) <= mac_an_ready; --- DBG(31) <= link_tx_ready_i; --- DBG(32) <= clear; --- DBG(33) <= CLK_SUPPL_PCLK; - - THE_FW_GBE_LSM: entity gbe_lsm - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- - MAC_AN_COMPLETE_IN => fw_mac_an_ready_int, - MAC_READY_CONF_IN => fw_mac_ready_conf_int, - MAC_RECONF_OUT => fw_mac_reconf_int, - -- - LINK_ACTIVE_OUT => fw_link_active_int, - -- - DEBUG => open - ); - - THE_FW_RB: entity rx_rb - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- MAC interface (RX) - MAC_RX_DATA_IN => fw_mac_rx_data_int, - MAC_RX_WR_IN => fw_mac_rx_wr_int, - MAC_RX_EOF_IN => fw_mac_rx_eof_int, - MAC_RX_ERROR_IN => fw_mac_rx_err_int, - MAC_RX_FIFOFULL_OUT => fw_mac_rx_fifofull_int, - -- FIFO interface (TX) - FIFO_FULL_IN => fw_fifo_full_int, - FIFO_WR_OUT => fw_fifo_wr_int, - FIFO_Q_OUT => fw_fifo_data_int, - FRAME_REQ_IN => fw_frame_req_int, - FRAME_ACK_OUT => fw_frame_ack_int, - FRAME_AVAIL_OUT => fw_frame_avail_int, - FRAME_START_OUT => fw_frame_start_int, - -- - DEBUG => open - ); - - THE_FW_FIFO: entity tx_fifo - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- MAC interface - MAC_TX_DATA_OUT => fw_mac_tx_data_int, - MAC_TX_READ_IN => fw_mac_tx_read_int, - MAC_FIFOEOF_OUT => fw_mac_fifoeof_int, - MAC_FIFOEMPTY_OUT => fw_mac_fifoempty_int, - MAC_FIFOAVAIL_OUT => fw_mac_fifoavail_int, - MAC_TX_DONE_IN => '0', -- not used - -- FIFO interface - FIFO_FULL_OUT => fw_fifo_full_int, - FIFO_WR_IN => fw_fifo_wr_int, - FIFO_D_IN => fw_fifo_data_int, - -- Link stuff - FRAME_START_IN => fw_frame_start_int, - LINK_ACTIVE_IN => fw_mac_an_ready_int, - -- - DEBUG => open - ); - THE_FW_FORWARDER: entity forwarder + -- scattering: data from uplink is distributed to downlinks + THE_SCATTER: entity scatter_ports port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, -- - FRAME_AVAIL_IN => fw_frame_avail_int, - FIFO_FULL_IN => fw_fifo_full_int, - FRAME_REQ_OUT => fw_frame_req_int, - FRAME_ACK_IN => fw_frame_ack_int, + FRAME_AVAIL_IN(3 downto 0) => , + FRAME_AVAIL_IN(15 downto 4) => (others => '0'), + FRAME_REQ_OUT(3 downto 0) => , + FRAME_REQ_OUT(15 downto 4) => open, + FRAME_ACK_IN(3 downto 0) => , + FRAME_ACK_IN(15 downto 4) => (others => '0'), + CYCLE_DONE_OUT => open, -- - DEBUG => open + DEBUG => open ); - THE_BW_GBE_LSM: entity gbe_lsm + THE_GATHER: entity gather_ports port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- - MAC_AN_COMPLETE_IN => bw_mac_an_ready_int, - MAC_READY_CONF_IN => bw_mac_ready_conf_int, - MAC_RECONF_OUT => bw_mac_reconf_int, + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, -- - LINK_ACTIVE_OUT => bw_link_active_int, - -- - DEBUG => open - ); - - THE_BW_RB: entity rx_rb - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- MAC interface (RX) - MAC_RX_DATA_IN => bw_mac_rx_data_int, - MAC_RX_WR_IN => bw_mac_rx_wr_int, - MAC_RX_EOF_IN => bw_mac_rx_eof_int, - MAC_RX_ERROR_IN => bw_mac_rx_err_int, - MAC_RX_FIFOFULL_OUT => bw_mac_rx_fifofull_int, - -- FIFO interface (TX) - FIFO_FULL_IN => bw_fifo_full_int, - FIFO_WR_OUT => bw_fifo_wr_int, - FIFO_Q_OUT => bw_fifo_data_int, - FRAME_REQ_IN => bw_frame_req_int, - FRAME_ACK_OUT => bw_frame_ack_int, - FRAME_AVAIL_OUT => bw_frame_avail_int, - FRAME_START_OUT => bw_frame_start_int, + FRAME_AVAIL_IN(3 downto 0) => , + FRAME_AVAIL_IN(15 downto 4) => (others => '0'), + FRAME_REQ_OUT(3 downto 0) => , + FRAME_REQ_OUT(15 downto 4) => open, + FRAME_ACK_IN(3 downto 0) => , + FRAME_ACK_IN(15 downto 4) => (others => '0'), + PORT_SELECT_OUT(3 downto 0) => , + PORT_SELECT_OUT(15 downto 4) => open, + CYCLE_DONE_OUT => open, -- - DEBUG => open + DEBUG => open ); - THE_BW_FIFO: entity tx_fifo - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- MAC interface - MAC_TX_DATA_OUT => bw_mac_tx_data_int, - MAC_TX_READ_IN => bw_mac_tx_read_int, - MAC_FIFOEOF_OUT => bw_mac_fifoeof_int, - MAC_FIFOEMPTY_OUT => bw_mac_fifoempty_int, - MAC_FIFOAVAIL_OUT => bw_mac_fifoavail_int, - MAC_TX_DONE_IN => '0', -- not used - -- FIFO interface - FIFO_FULL_OUT => bw_fifo_full_int, - FIFO_WR_IN => bw_fifo_wr_int, - FIFO_D_IN => bw_fifo_data_int, - -- Link stuff - FRAME_START_IN => bw_frame_start_int, - LINK_ACTIVE_IN => bw_mac_an_ready_int, - -- - DEBUG => open - ); + DBG(3 downto 0) <= (others => '0'); + DBG(7 downto 4) <= (others => '0'); + DBG(11 downto 8) <= '0'; + DBG(15 downto 12) <= '0'; + DBG(16) <= '0'; + DBG(17) <= '0'; + DBG(18) <= '0'; + DBG(19) <= '0'; + DBG(20) <= '0'; + DBG(21) <= '0'; + DBG(22) <= '0'; + DBG(23) <= '0'; + DBG(24) <= '0'; + DBG(25) <= '0'; + DBG(26) <= '0'; + DBG(27) <= '0'; + DBG(28) <= '0'; + DBG(29) <= '0'; + DBG(30) <= '0'; + DBG(31) <= '0'; + DBG(32) <= '0'; + DBG(33) <= '0'; - THE_BW_FORWARDER: entity forwarder - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- - FRAME_AVAIL_IN => bw_frame_avail_int, - FIFO_FULL_IN => bw_fifo_full_int, - FRAME_REQ_OUT => bw_frame_req_int, - FRAME_ACK_IN => bw_frame_ack_int, - -- - DEBUG => open - ); - --------------------------------------------------------------------------- -- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon) ---------------------------------------------------------------------------