From: Jan Michel Date: Thu, 12 Jul 2018 09:47:44 +0000 (+0200) Subject: add files for trigger logic test design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=43d7a5f5af072bd9064616267dc3f24787c31987;p=trb3sc.git add files for trigger logic test design --- diff --git a/triggerlogic/compile.pl b/triggerlogic/compile.pl new file mode 100755 index 0000000..8289ed4 --- /dev/null +++ b/triggerlogic/compile.pl @@ -0,0 +1,454 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; +use Term::ANSIColor qw(:constants); +use lib '.'; + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA1156"; +my $SPEEDGRADE="8"; + + +my %config = do "./config_compile.pl"; + + +my $TOPNAME = $config{TOPNAME}; +my $lattice_path = $config{lattice_path}; +my $synplify_path = $config{synplify_path}; +my $lm_license_file_for_synplify = $config{lm_license_file_for_synplify}; +my $lm_license_file_for_par = $config{lm_license_file_for_par}; +my $synplify_command = $config{synplify_command}; + +#my $synplify_locale_workaround = "en_US\@UTF-8"; +my $synplify_locale_workaround = "C"; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed + +my $include_TDC = $config{include_TDC} || 0; +my $include_GBE = $config{include_GBE} || 0; +my $twr_number_of_errors = $config{twr_number_of_errors} || 10; +my $pinout_file = $config{pinout_file} || $TOPNAME; +my $nodelist_file = $config{nodelist_file} || 'nodelist.txt'; + +$FAMILYNAME = $config{Familyname} if $config{Familyname}; +$DEVICENAME = $config{Devicename} if $config{Devicename}; +$PACKAGE = $config{Package} if $config{Package}; +$SPEEDGRADE = $config{Speedgrade} if $config{Speedgrade}; + +################################################################################### +#Settings for this project + +################################################################################### + +################################################################################### +#Options for the script +my $help = ""; +my $isMultiPar = 0; # set it to zero for single par run on the local machine +my $nrNodes = 0; # set it to one for single par run on the local machine +my $all = 1; +my $syn = 0; +my $map = 0; +my $par = 0; +my $timing = 0; +my $bitgen = 0; +my $con = 0; +my $guidefile = 0; +my $parallel = ''; + +my $result = GetOptions ( + "h|help" => \$help, + "m|mpar=i" => \$nrNodes, + "a|all" => \$all, + "c|con" => \$con, + "s|syn" => \$syn, + "mp|map" => \$map, + "p|par" => \$par, + "t|timing" => \$timing, + "b|bitgen" => \$bitgen, + "g|guide" => \$guidefile, + "mc|multicore" => \$parallel + ); + + + +if($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to run the whole process.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-c --con\tCompile constraints only.\n"; + print "-mp --map\tRun map part of the compile script.\n"; + print "-p --par\tRun par part of the compile script.\n"; + print "-t --timing\tRun timing analysis part of the compile script.\n"; + print "-b --bitgen\tRun bit generation part of the compile script.\n"; + print "-m --mpar\tSwitch for multi par. \"-m \" (Default = off)\n"; + print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n"; + print "\n"; + exit; +} + +if ($nrNodes!=0){ + $isMultiPar=1; +} +if ($con!=0 || $syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){ + $all=0; +} +$parallel = '&' if $parallel; + +################################################################################### + + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; + +#open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or +# die "Can't fork: $!"; +#while (<$SOURCE>) { +# if (/^(.*)=(.*)/) { +# print "setting A:$1 nach ${2}\n"; +# $ENV{$1} = ${2} ; +# } +#} +#close $SOURCE; + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'LC_ALL'}=$synplify_locale_workaround; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; +$ENV{'SYNPLIFY_BINARY'}=$config{synplify_binary}; + + + + + + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; + system ("cd workdir; ../../../trb3/base/linkdesignfiles.sh; cd ..;"); +} + +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); + + +if($con==1 || $all==1){ + #create full lpf file + print GREEN, "Generating constraints file...\n\n", RESET; + system("cp ../pinout/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf"); + +# system("cat ../pinout/trb3sc_basic.lpf >> $WORKDIR/$TOPNAME.lpf"); + my $c = "cat ../pinout/basic_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"; + system($c); + + system("cat $TOPNAME.lpf >> $WORKDIR/$TOPNAME.lpf"); + + if($include_TDC) { + #system("cat ../../trb3sc/tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat ../../trb3sc/tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat ../../trb3sc/tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + + #change the Ring buffer name in the constraints file according to the config.vhd + my $fh = new FileHandle("; + $fh -> close; + my $ringbuffersize = 5; + + foreach (@a) + { + if(/constant\s*RING_BUFFER_SIZE/) + { + my $tmp = $1 if $_ =~ /(:=.*;)/; + $ringbuffersize = $1 if $1 =~ /(\d+)/; + } + } + + my @newline; + $fh = new FileHandle("<$WORKDIR/$TOPNAME".".lpf"); + @a = <$fh>; + $fh -> close; + + foreach (@a) + { + if ($ringbuffersize == 0) { + $_ =~ s/Buffer_128.The_Buffer/Buffer_32.The_Buffer/g; + } + elsif ($ringbuffersize == 1 || $ringbuffersize == 5) { + $_ =~ s/Buffer_128.The_Buffer/Buffer_64.The_Buffer/g; + } + elsif ($ringbuffersize == 2) { + $_ =~ s/Buffer_128.The_Buffer/Buffer_96.The_Buffer/g; + } + elsif ($ringbuffersize == 3 || $ringbuffersize == 7) { + $_ =~ s/Buffer_128.The_Buffer/Buffer_128.The_Buffer/g; + } + else { + print "unknown ringbuffer size... \n"; + exit 129; + } + + push(@newline,$_); + } + $fh = new FileHandle(">$WORKDIR/$TOPNAME".".lpf"); + print $fh @newline; + $fh -> close; + + + #edit the lpf file according to tdc settings + system("unlink $WORKDIR/compile_tdc.pl"); + system("ln -s ../../../tdc/scripts/compile_tdc.pl $WORKDIR/"); + system ("./$WORKDIR/compile_tdc.pl", $WORKDIR, $TOPNAME, "config"); + } + + if($include_GBE) { + } + + #copy delay line to project folder + if($include_TDC) { + system("rm $WORKDIR/Adder_304.ngo"); + system("ln -s ../../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); + } + } + +if($guidefile && -f "$TOPNAME.ncd") { + system("cp $TOPNAME.ncd guidefile.ncd"); + $guidefile = " -g guidefile.ncd " + } +else { + $guidefile = ""; + } + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">$WORKDIR/version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); +my $tpmap = $TOPNAME . "_map" ; + +chdir $WORKDIR; +if($syn==1 || $all==1){ + system ("./compile_tdc.pl", $WORKDIR, $TOPNAME, "prj") if ($include_TDC); ## edit prj file for different designs + print GREEN, "Starting synthesis process...\n\n", RESET; +# $synplify_command = "$synplify_path/bin/synplify_pro" unless $synplify_command; + $synplify_command = "$synplify_path/bin/synplify_premier_dp" unless $synplify_command; + $c="$synplify_command -batch ../$TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); + + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a) + { + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | egrep --color \"\@E:\""; + system($c); + print RED, "ERROR in the log file $TOPNAME.srr Exiting...\n\n", RESET; + exit 129; + } + } +} + + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if($map==1 || $all==1){ + print GREEN, "Starting mapping process...\n\n", RESET; + + $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|; + execute($c); + + $fh = new FileHandle("<$TOPNAME"."_mrp.html"); + @a = <$fh>; + $fh -> close; + my $i=1; + my $print=0; + foreach (@a) + { + if(/WARNING/|$print) + { + if((grep /WARNING - map: There are semantic errors in the preference file/, $_) & ($i == 1)) + { + last; + } + elsif(grep /WARNING - map: There are semantic errors in the preference file/, $_) + { + print YELLOW, "There are errors in the constraints file. Better have a look...\n\n", RESET; + #sleep(5); # ERROR -> sleep is effective before the print + last; + } + elsif ($i == 1) + { + print RED,"\n\n", RESET; + print RED,"#################################################\n", RESET; + print RED,"CONSTRAINTS ERRORS\n", RESET; + print RED,"#################################################\n\n", RESET; + } + $print=1; + if(grep /WARNING.*UGROUP/, $_) + { + print RED, $_, RESET; + } + elsif(grep /FC|hitBuf|ff_en/, $_) + { + print YELLOW, $_, RESET; + } + else + { + print $_; + } + $i++; + } + } +} + +if($par==1 || $all==1){ + print GREEN, "Starting placement process...\n\n", RESET; + + system("rm $TOPNAME.ncd"); + if ($isMultiPar) + { + $c=qq|LC_ALL=en_US.UTF-8; par -m ../../scripts/$nodelist_file -n $nrNodes -f "../par.p2t" $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|; + execute($c); + + # find and copy the .ncd file which has met the timing constraints + $fh = new FileHandle("<$TOPNAME".".par"); + my @a = <$fh>; + my $isSuccess = 0; + $fh -> close; + my $i=1; + foreach (@a) + { + my @line = split(/\s+/, $_); + + if(@line && ($line[2] =~ m/^[0-9]+$/) && ($line[4] =~ m/^[0-9]+$/)) + { + if(($line[2] == 0) && ($line[4] == 0)) + { + print GREEN, "Copying $line[0].ncd file to workdir\n", RESET; + my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd"; + system($c); + print "\n\n"; + $isSuccess = 1; + last; + } + } + } + + if (!$isSuccess){ + print RED, "\n\n", RESET; + print RED, "#################################################\n", RESET; + print RED, "# !!!PAR not succesfull!!! #\n", RESET; + print RED, "#################################################\n\n", RESET; + exit 129; + } + $c="cat $TOPNAME.par"; + system($c); + } + else + { + $c=qq|par -f "../par.p2t" $guidefile $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; + execute($c); + #my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; + #system($c); + } + +} + + +if($timing==1 || $all==1){ + print GREEN, "Generating timing report...\n\n", RESET; + + # TWR Timing Report + $c=qq|trce -c -v $twr_number_of_errors -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf" $parallel|; + execute($c); + + $c=qq|trce -hld -c -v $twr_number_of_errors -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf" $parallel|; + execute($c); + + # IOR IO Timing Report + $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + +} + +if($bitgen==1 || $all==1){ + print GREEN, "Generating bit file...\n\n", RESET; + + $c=qq|ltxt2ptxt $TOPNAME.ncd|; + execute($c) unless $config{no_ltxt2ptxt} ; + + if($config{make_jed}) { + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|; + } + else { + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + } + execute($c); +} + +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; +execute($c); + +if($config{firefox_open}) { + $c=qq|firefox $TOPNAME.html|; + execute($c); + } + +chdir ".."; +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + $c = ". $lattice_bin_path/diamond_env; " . $c; + print GREEN, "\n\ncommand to execute: $c \n", RESET; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/triggerlogic/config.vhd b/triggerlogic/config.vhd new file mode 100644 index 0000000..698d9c0 --- /dev/null +++ b/triggerlogic/config.vhd @@ -0,0 +1,110 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 256; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CC"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"69"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 3; + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 64; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 64; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/triggerlogic/config_compile_frankfurt.pl b/triggerlogic/config_compile_frankfurt.pl new file mode 100644 index 0000000..b9f678d --- /dev/null +++ b/triggerlogic/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_trigger", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/N-2017.09-1', +#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +pinout_file => 'trb3sc_basic', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + diff --git a/triggerlogic/config_compile_gsi.pl b/triggerlogic/config_compile_gsi.pl new file mode 100644 index 0000000..1f1b04b --- /dev/null +++ b/triggerlogic/config_compile_gsi.pl @@ -0,0 +1,13 @@ +TOPNAME => "trb3sc_basic", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.4_x64/', +synplify_path => '/opt/synplicity/J-2014.09-SP2', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => 'nodes_gsi_template.txt', + +firefox_open => 0, + + diff --git a/triggerlogic/par.p2t b/triggerlogic/par.p2t new file mode 100644 index 0000000..cb0ad8d --- /dev/null +++ b/triggerlogic/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 26 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/triggerlogic/synplify.fdc b/triggerlogic/synplify.fdc new file mode 100644 index 0000000..1a8f9d8 --- /dev/null +++ b/triggerlogic/synplify.fdc @@ -0,0 +1,51 @@ +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /d/jspc22/trb/git/trb3sc/template/synplify.fdc +# Written on Thu Jun 18 11:51:05 2015 +# by Synplify Pro, I-2014.03L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +###==== END Collections + +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {clk240} {p:CLK_CORE_PCLK} -period {4.16} +create_clock -name {clksys} {n:THE_CLOCK_RESET.SYS_CLK_OUT} -period {10} +create_clock -name {clktxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.tx_full_clk_ch3} -period {5} +create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.rx_full_clk_ch3} -period {5} +create_clock -name {clkintfull} {n:THE_CLOCK_RESET.gen_norecov_clock\.gen_200\.THE_INT_PLL.CLKOP} -period {5} + +###==== END Clocks + +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" + +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs + + +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" + +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes + +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" + +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + + + + + + + + + diff --git a/triggerlogic/trb3sc_trigger.lpf b/triggerlogic/trb3sc_trigger.lpf new file mode 100644 index 0000000..82eb127 --- /dev/null +++ b/triggerlogic/trb3sc_trigger.lpf @@ -0,0 +1,7 @@ + +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x; + +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; + diff --git a/triggerlogic/trb3sc_trigger.prj b/triggerlogic/trb3sc_trigger.prj new file mode 100644 index 0000000..a8bd345 --- /dev/null +++ b/triggerlogic/trb3sc_trigger.prj @@ -0,0 +1,191 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_trigger" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_trigger.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + + + +add_file -vhdl -lib work "./trb3sc_trigger.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/triggerlogic/trb3sc_trigger.vhd b/triggerlogic/trb3sc_trigger.vhd new file mode 100644 index 0000000..f53720d --- /dev/null +++ b/triggerlogic/trb3sc_trigger.vhd @@ -0,0 +1,428 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + +entity trb3sc_trigger is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + TRIG_LEFT : in std_logic; --Trigger Input + + --Backplane, all lines + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_3V3 : inout std_logic_vector( 3 downto 0); + --Backplane for slaves on trbv3scbp1 + BACK_GPIO : inout std_logic_vector(3 downto 0); + + --AddOn Connector + INP : in std_logic_vector(63 downto 0); + + --KEL Connector + KEL : inout std_logic_vector(40 downto 1); -- <-- Inputs + X : out std_logic_vector(12 downto 1); + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); -- <-- Outputs + RJ_IO : inout std_logic_vector( 3 downto 0); + SPARE_IN : in std_logic_vector( 1 downto 0); + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + + + --Serdes: Backplane + --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane + --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- + --SFP D0,B3(D1) D0: GbE, B3: TrbNet + + +end entity; + +architecture trb3sc_arch of trb3sc_trigger is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busrdo_rx, bustrglogic_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busrdo_tx, bustrglogic_tx, bus_master_in : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + type a_t is array(1 to 16) of std_logic_vector(6000 downto 0); + signal c : a_t; + attribute syn_keep of c : signal is true; + attribute syn_preserve of c : signal is true; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci_rx : signal is true; + attribute syn_preserve of bussci_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + + type state_t is (IDLE, WRITE, FINISH, BUSYEND); + signal state : state_t; + signal data_counter, data_amount : unsigned(15 downto 0) := (others => '0'); + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(0).clk_full, + NET_CLK_HALF_IN => med2int(0).clk_half, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP_TX_DIS(0) <= '1'; + gen_sfp_con : if SERDES_NUM = 3 generate + sfp_los_i <= SFP_LOS(1); + sfp_prsnt_i <= SFP_MOD0(1); + SFP_TX_DIS(1) <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + ); + + readout_tx(0).data_finished <= '1'; + readout_tx(0).data_write <= '0'; + readout_tx(0).busy_release <= '1'; + + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busrdo_rx, --User config + BUS_RX(4) => bustrglogic_rx, + + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busrdo_tx, + BUS_TX(4) => bustrglogic_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => lcd_data, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => INP,--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_INPUTS => INP,--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_OUTPUTS => X(4 downto 1),--open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + RJ_IO <= "0000"; + +-- BACK_GPIO <= (others => 'Z'); + BACK_LVDS <= (others => '0'); + BACK_3V3 <= (others => 'Z'); + + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + LED_WHITE(0) <= time_counter(26) and time_counter(19); + LED_WHITE(1) <= time_counter(20); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + + + + + + + +end architecture; + + +