From: Jan Michel Date: Mon, 11 Jul 2016 16:55:56 +0000 (+0200) Subject: changed feedback in pll, lower frequency pwm, flash working X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=45050a4116e744cbcf85f9c4552498c60a20c47e;p=dirich.git changed feedback in pll, lower frequency pwm, flash working --- diff --git a/code/pwm_generator.vhd b/code/pwm_generator.vhd index 4ece0bc..43045d0 100644 --- a/code/pwm_generator.vhd +++ b/code/pwm_generator.vhd @@ -42,8 +42,8 @@ signal flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); signal pwm_i : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); signal ci : integer range 0 to CHANNELS-1; -signal clock_enable : std_logic; -signal timer : unsigned(3 downto 0); +signal clock_enable : std_logic_vector(15 downto 0) := x"0001"; +signal timer : unsigned(4 downto 0); begin @@ -86,20 +86,22 @@ GEN_REAL_VALUES : process begin set_tmp(ci) <= unsigned(signed(set(ci)) + compensate); ci <= ci + 1; --- --- temp_i <= signed(TEMP_IN); --- temp_calc_i <= signed(temp_i) * signed(set_compensate); --- compensate <= temp_calc_i(27 downto 12); + + temp_i <= signed(TEMP_IN); + temp_calc_i <= signed(temp_i) * signed(set_compensate); + compensate <= temp_calc_i(27 downto 12); end process; process begin wait until rising_edge(CLK); - timer <= timer + 1; - if timer(2 downto 0) = "000" then - clock_enable <= '1'; - else - clock_enable <= '0'; - end if; + clock_enable <= clock_enable(14 downto 0) & clock_enable(15); +-- if +-- timer <= timer + 1; +-- if timer(2 downto 0) = "000" then +-- clock_enable <= '1'; +-- else +-- clock_enable <= '0'; +-- end if; end process; @@ -109,7 +111,7 @@ gen_channels : for i in 0 to CHANNELS-1 generate process begin wait until rising_edge(CLK); - if clock_enable = '1' then + if clock_enable(i/2) = '1' then last_flag(i) <= flag(i); pwm_i(i) <= (last_flag(i) xor flag(i)); cnt(i) <= cnt(i) + resize(set_tmp(i),17); diff --git a/cores/pll_240_100/pll_240_100.lpc b/cores/pll_240_100/pll_240_100.lpc index b648669..ffe81c0 100644 --- a/cores/pll_240_100/pll_240_100.lpc +++ b/cores/pll_240_100/pll_240_100.lpc @@ -16,8 +16,8 @@ CoreRevision=5.8 ModuleName=pll_240_100 SourceFormat=vhdl ParameterFileVersion=1.0 -Date=03/18/2016 -Time=16:38:06 +Date=07/11/2016 +Time=18:43:16 [Parameters] Verilog=0 @@ -55,7 +55,7 @@ CLKOS3_TOL=0.0 CLKOS3_DIV=5 CLKOS3_ACTUAL_FREQ=120.000000 CLKOS3_MUXD=DISABLED -FEEDBK_PATH=CLKOS +FEEDBK_PATH=INT_OS CLKFB_DIV=1 FRACN_ENABLE=DISABLED FRACN_DIV= @@ -90,4 +90,4 @@ PLL_LOCK_STK=DISABLED PLL_USE_SMI=DISABLED [Command] -cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 2 +cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 6 diff --git a/cores/pll_240_100/pll_240_100.sbx b/cores/pll_240_100/pll_240_100.sbx index 7161108..4d87486 100644 --- a/cores/pll_240_100/pll_240_100.sbx +++ b/cores/pll_240_100/pll_240_100.sbx @@ -45,8 +45,8 @@ LFE5UM-85F-8BG381C synplify 2016-01-06.11:38:14 AM - 2016-01-06.02:19:54 PM - 3.6.0.83.4 + 2016-07-11.06:43:17 PM + 3.7.1.502 VHDL false @@ -115,7 +115,7 @@ Date - 01/06/2016 + 07/11/2016 ModuleName @@ -131,7 +131,7 @@ Time - 14:19:48 + 18:43:16 VendorName @@ -140,15 +140,15 @@ CLKFB_DIV - 5 + 1 CLKI_DIV - 6 + 2 CLKI_FREQ - 240 + 200 CLKOP_ACTUAL_FREQ @@ -160,7 +160,7 @@ CLKOP_DIV - 3 + 1 CLKOP_DPHASE @@ -172,7 +172,7 @@ CLKOP_MUXA - DISABLED + ENABLED CLKOP_TOL @@ -188,7 +188,7 @@ CLKOS2_ACTUAL_FREQ - 240.000000 + 200.000000 CLKOS2_APHASE @@ -196,7 +196,7 @@ CLKOS2_DIV - 1 + 3 CLKOS2_DPHASE @@ -208,11 +208,11 @@ CLKOS2_FREQ - 100.00 + 200 CLKOS2_MUXC - ENABLED + DISABLED CLKOS2_TOL @@ -348,7 +348,7 @@ FEEDBK_PATH - CLKOP + INT_OS FRACN_DIV @@ -376,7 +376,7 @@ PLL_BW - 4.966 + 8.185 PLL_LOCK_MODE @@ -413,7 +413,7 @@ cmd_line - -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 + -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 6 diff --git a/cores/pll_240_100/pll_240_100.vhd b/cores/pll_240_100/pll_240_100.vhd index 22dc396..1ca4f10 100644 --- a/cores/pll_240_100/pll_240_100.vhd +++ b/cores/pll_240_100/pll_240_100.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 -- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 2 +--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 6 -fdc /d/jspc22/trb/git/dirich/cores/pll_240_100/pll_240_100.fdc --- Fri Mar 18 16:38:06 2016 +-- Mon Jul 11 18:43:17 2016 library IEEE; use IEEE.std_logic_1164.all; @@ -25,8 +25,9 @@ architecture Structure of pll_240_100 is signal REFCLK: std_logic; signal CLKOS3_t: std_logic; signal CLKOS2_t: std_logic; - signal CLKOP_t: std_logic; signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; signal scuba_vhi: std_logic; signal scuba_vlo: std_logic; @@ -69,15 +70,15 @@ begin OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 5, CLKOS2_DIV=> 3, CLKOS_DIV=> 6, CLKOP_DIV=> 1, CLKFB_DIV=> 1, - CLKI_DIV=> 2, FEEDBK_PATH=> "CLKOS") - port map (CLKI=>CLKI, CLKFB=>CLKOS_t, PHASESEL1=>scuba_vlo, + CLKI_DIV=> 2, FEEDBK_PATH=> "INT_OS") + port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK, - INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>CLKFB_t); CLKOS3 <= CLKOS3_t; CLKOS2 <= CLKOS2_t; diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf index 6769e9b..5cae218 100644 --- a/dirich/dirich.lpf +++ b/dirich/dirich.lpf @@ -10,7 +10,8 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLOCK_IN 200 MHz; FREQUENCY PORT CLOCK_CAL 200 MHz; - +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "med2int_0.clk_full" 200 MHz; BLOCK PATH TO PORT "LED*"; @@ -24,6 +25,9 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + GSR_NET NET "GSR_N"; LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index b5379ad..f8513f4 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -270,10 +270,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record RESET => reset_i, --Flash & Reload - FLASH_CS => open, --FLASH_CS, - FLASH_CLK => flash_clk_i, --FLASH_CLK, - FLASH_IN => '0', --FLASH_OUT, - FLASH_OUT => open,--FLASH_IN, + FLASH_CS => FLASH_CS, --FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, --FLASH_OUT, + FLASH_OUT => FLASH_IN,--FLASH_IN, PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI @@ -308,17 +308,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record ); --- THE_FLASH_CLOCK : usrmclk --- port map( --- USRMCLKI => time_counter(23), --- USRMCLKTS => '1' --- ); --- --- FLASH_CLK <= time_counter(23); --- FLASH_HOLD <= time_counter(27); --- FLASH_WP <= time_counter(26); --- FLASH_CS <= time_counter(25); --- FLASH_IN <= time_counter(24); + +FLASH_HOLD <= '1'; +FLASH_WP <= '1'; + --------------------------------------------------------------------------- -- PWM / Thresh diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index 9102479..d0d3cb7 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -86,7 +86,7 @@ LOCATE COMP "PWM[30]" SITE "A16"; LOCATE COMP "PWM[31]" SITE "E14"; LOCATE COMP "PWM[32]" SITE "E15"; DEFINE PORT GROUP "PWM_group" "PWM*" ; -IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS25 DRIVE=12 SLEWRATE=FAST BANK_VCCIO=2.5; +IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW BANK_VCCIO=2.5; LOCATE COMP "LED_GREEN" SITE "G16"; LOCATE COMP "LED_ORANGE" SITE "H16";