From: Peter Lemmens <p.j.j.lemmens@rug.nl>
Date: Thu, 10 Oct 2013 14:25:55 +0000 (+0200)
Subject: tx_control replaced by special soda-version to remedy latancy problems.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=454eb0c1f7023e89cf9c96daa2f92d4d4a1c3a2d;p=soda.git

tx_control replaced by special soda-version to remedy latancy problems.
Still occasional reset problems: got_link_ready_i sometimes goes low, indicating link-loss

Dedicated signal introduced for LINK_PHASE (for proper start of 8-bit tx in 16-bit interface) and
TX_DLM_INIT (early warning to tx_control state-machine; 1st byte loss is mended.
---

diff --git a/sfp_1_200_int.txt b/sfp_1_200_int.txt
new file mode 120000
index 0000000..65141a0
--- /dev/null
+++ b/sfp_1_200_int.txt
@@ -0,0 +1 @@
+../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
diff --git a/soda_client.ldf b/soda_client.ldf
index 9b9b10f..4e9700b 100644
--- a/soda_client.ldf
+++ b/soda_client.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+        <Options top="trb3_periph_sodaclient"/>
         <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -38,6 +38,15 @@
         <Source name="source/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
             <Options/>
         </Source>
+        <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -305,15 +314,6 @@
         <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
         <Source name="source/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
             <Options top_module="trb3_periph_sodaclient"/>
         </Source>
diff --git a/soda_source.ldf b/soda_source.ldf
index 369f753..8455f12 100644
--- a/soda_source.ldf
+++ b/soda_source.ldf
@@ -44,6 +44,12 @@
         <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="source/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -278,9 +284,6 @@
         <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
         <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -311,9 +314,6 @@
         <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
         <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd
index 361f159..378b7c7 100644
--- a/source/med_ecp3_sfp_sync_down.vhd
+++ b/source/med_ecp3_sfp_sync_down.vhd
@@ -9,61 +9,61 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.med_sync_define.all;
+use work.soda_components.all;
 
 entity med_ecp3_sfp_sync_down is
-  generic(
-    SERDES_NUM : integer range 0 to 3 := 0;
---     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
-    IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
-    );
-  port(
-    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    --Internal Connection TX
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic := '0';
-    --Internal Connection RX
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-    MED_DATAREADY_OUT  : out std_logic := '0';
-    MED_READ_IN        : in  std_logic;
-    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
-    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
-    
-    --Sync operation
-    RX_DLM             : out std_logic := '0';
-    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-    TX_DLM             : in  std_logic := '0';
-    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-    
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;  --not used
-    SD_REFCLK_N_IN     : in  std_logic;  --not used
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
-   );
+	generic(	SERDES_NUM : integer range 0 to 3 := 0;
+				IS_SYNC_SLAVE   : integer := c_NO);       --select slave mode
+	port(
+		CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+		SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+		RESET              : in  std_logic; -- synchronous reset
+		CLEAR              : in  std_logic; -- asynchronous reset
+		--Internal Connection TX
+		MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+		MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+		MED_DATAREADY_IN   : in  std_logic;
+		MED_READ_OUT       : out std_logic := '0';
+		--Internal Connection RX
+		MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+		MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+		MED_DATAREADY_OUT  : out std_logic := '0';
+		MED_READ_IN        : in  std_logic;
+		CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
+		CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+
+		--Sync operation
+		RX_DLM             : out std_logic := '0';
+		RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
+		TX_DLM             : in  std_logic := '0';
+		TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+		TX_DLM_INIT				: in std_logic := '0';	--PL!
+		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
+
+		--SFP Connection
+		SD_RXD_P_IN        : in  std_logic;
+		SD_RXD_N_IN        : in  std_logic;
+		SD_TXD_P_OUT       : out std_logic;
+		SD_TXD_N_OUT       : out std_logic;
+		SD_REFCLK_P_IN     : in  std_logic;  --not used
+		SD_REFCLK_N_IN     : in  std_logic;  --not used
+		SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+		SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+		SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+		--Control Interface
+		SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ           : in  std_logic := '0';
+		SCI_WRITE          : in  std_logic := '0';
+		SCI_ACK            : out std_logic := '0';
+		SCI_NACK           : out std_logic := '0';
+		-- Status and control port
+		STAT_OP            : out std_logic_vector (15 downto 0);
+		CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
+		STAT_DEBUG         : out std_logic_vector (63 downto 0);
+		CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+	);
 end entity;
 
 
@@ -108,12 +108,14 @@ signal rx_k              : std_logic;
 signal rx_error          : std_logic;
 
 signal rst_n             : std_logic;
+signal rst						: std_logic;		-- PL!
 signal rx_serdes_rst     : std_logic;
 signal tx_serdes_rst     : std_logic;
 signal tx_pcs_rst        : std_logic;
 signal rx_pcs_rst        : std_logic;
 signal rst_qd            : std_logic;
 signal serdes_rst_qd     : std_logic;
+signal sd_los_i          : std_logic;	--PL!
 
 signal rx_los_low        : std_logic;
 signal lsm_status        : std_logic;
@@ -137,6 +139,7 @@ signal tx_allow           : std_logic;
 signal rx_allow           : std_logic;
 signal tx_allow_q         : std_logic;
 signal rx_allow_q         : std_logic;
+signal link_phase_S			: std_logic;	--PL!
 signal request_retr_i     : std_logic;
 signal start_retr_i       : std_logic;
 signal request_retr_position_i  : std_logic_vector(7 downto 0);
@@ -170,7 +173,9 @@ CLK_RX_FULL_OUT <= clk_rx_full;
 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
 
 
-rst_n <= not CLEAR;
+--rst_n <= not CLEAR;	PL!
+rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst   <=     (CLEAR or sd_los_i or internal_make_link_reset_out);
 
 
 gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
@@ -191,7 +196,7 @@ THE_SERDES : entity work.serdes_sync_downstream
     hdinn_ch0            => SD_RXD_N_IN,
     hdoutp_ch0           => SD_TXD_P_OUT,
     hdoutn_ch0           => SD_TXD_N_OUT,
-    rxiclk_ch0           => clk_200_i,
+--    rxiclk_ch0           => clk_200_i,
     txiclk_ch0           => clk_200_i,
     rx_full_clk_ch0      => clk_rx_full,
     rx_half_clk_ch0      => clk_rx_half,
@@ -262,18 +267,18 @@ THE_TX_FSM : tx_reset_fsm
     );
 
 -- Master does not do bit-locking    
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = 1) else x"0000";
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
 
 
 --Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
 PROC_ALLOW : process begin
   wait until rising_edge(clk_200_i);
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
     rx_allow <= '1';
   else
     rx_allow <= '0';
   end if;
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
     tx_allow <= '1';
   else
     tx_allow <= '0';
@@ -299,38 +304,40 @@ end process;
 -------------------------------------------------      
 -- TX Data
 -------------------------------------------------         
-THE_TX : tx_control
-  port map(
-    CLK_200                => clk_200_i,
-    CLK_100                => SYSCLK,
-    RESET_IN               => CLEAR,
-
-    TX_DATA_IN             => MED_DATA_IN,
-    TX_PACKET_NUMBER_IN    => MED_PACKET_NUM_IN,
-    TX_WRITE_IN            => MED_DATAREADY_IN,
-    TX_READ_OUT            => MED_READ_OUT,
-
-    TX_DATA_OUT            => tx_data,
-    TX_K_OUT               => tx_k,
-
-    REQUEST_RETRANSMIT_IN  => request_retr_i,             --TODO
-    REQUEST_POSITION_IN    => request_retr_position_i,    --TODO
-
-    START_RETRANSMIT_IN    => start_retr_i,               --TODO
-    START_POSITION_IN      => request_retr_position_i,    --TODO
-
-    SEND_DLM               => TX_DLM,
-    SEND_DLM_WORD          => TX_DLM_WORD,
-    
-    SEND_LINK_RESET_IN     => CTRL_OP(15),
-    TX_ALLOW_IN            => tx_allow,
-    RX_ALLOW_IN            => rx_allow,
-
-    DEBUG_OUT              => debug_tx_control_i,
-    STAT_REG_OUT           => stat_tx_control_i
-    );  
-
-
+THE_TX : soda_tx_control
+	port map(
+		CLK_200						=> clk_200_i,
+		CLK_100						=> SYSCLK,
+		RESET_IN						=> rst,		--CLEAR, PL!
+
+		TX_DATA_IN					=> MED_DATA_IN,
+		TX_PACKET_NUMBER_IN		=> MED_PACKET_NUM_IN,
+		TX_WRITE_IN					=> MED_DATAREADY_IN,
+		TX_READ_OUT					=> MED_READ_OUT,
+
+		TX_DATA_OUT					=> tx_data,
+		TX_K_OUT						=> tx_k,
+
+		REQUEST_RETRANSMIT_IN	=> request_retr_i,             --TODO
+		REQUEST_POSITION_IN		=> request_retr_position_i,    --TODO
+
+		START_RETRANSMIT_IN		=> start_retr_i,               --TODO
+		START_POSITION_IN			=> request_retr_position_i,    --TODO
+
+		TX_DLM_INIT					=>	TX_DLM_INIT,
+		SEND_DLM						=> TX_DLM,
+		SEND_DLM_WORD				=> TX_DLM_WORD,
+
+		SEND_LINK_RESET_IN		=> CTRL_OP(15),
+		TX_ALLOW_IN					=> tx_allow,
+		RX_ALLOW_IN					=> rx_allow,
+		LINK_PHASE_OUT				=>	link_phase_S,		--PL!
+
+		DEBUG_OUT					=> debug_tx_control_i,
+		STAT_REG_OUT				=> stat_tx_control_i
+);  
+
+LINK_PHASE_OUT		<= link_phase_S;		--PL!
 -------------------------------------------------      
 -- RX Data
 -------------------------------------------------             
@@ -338,7 +345,7 @@ THE_RX_CONTROL : rx_control
   port map(
     CLK_200                        => clk_200_i,
     CLK_100                        => SYSCLK,
-    RESET_IN                       => CLEAR,
+    RESET_IN                       => rst,		--CLEAR, PL!
 
     RX_DATA_OUT                    => MED_DATA_OUT,
     RX_PACKET_NUMBER_OUT           => MED_PACKET_NUM_OUT,
@@ -483,8 +490,8 @@ debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
       
 STAT_DEBUG <= debug_reg;
 
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
-
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
 
 STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
 STAT_OP(14) <= '0';
diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx
index 60b8645..472bcba 100644
--- a/source/serdes_sync_downstream.ipx
+++ b/source/serdes_sync_downstream.ipx
@@ -1,10 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 09 11 08:27:01.177" version="8.1" type="IP" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 10:05:44.402" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 09 11 08:26:59.000"/>
-		<File name="serdes_sync_downstream.pp" type="pp" modified="2013 09 11 08:26:59.000"/>
-		<File name="serdes_sync_downstream.sym" type="sym" modified="2013 09 11 08:26:59.000"/>
-		<File name="serdes_sync_downstream.tft" type="tft" modified="2013 09 11 08:26:59.000"/>
-		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 09 11 08:26:59.000"/>
+		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 10 02 10:05:42.000"/>
+		<File name="serdes_sync_downstream.pp" type="pp" modified="2013 10 02 10:05:42.000"/>
+		<File name="serdes_sync_downstream.sym" type="sym" modified="2013 10 02 10:05:43.000"/>
+		<File name="serdes_sync_downstream.tft" type="tft" modified="2013 10 01 11:57:48.000"/>
+		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 10 02 10:05:42.000"/>
+		<File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2013 10 01 11:57:48.000"/>
   </Package>
 </DiamondModule>
diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc
index 40b2812..687f5e4 100644
--- a/source/serdes_sync_downstream.lpc
+++ b/source/serdes_sync_downstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_downstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=09/11/2013
-Time=08:26:59
+Date=10/02/2013
+Time=10:05:42
 
 [Parameters]
 Verilog=0
@@ -55,7 +55,7 @@ _tx_data_width0=8
 _tx_data_width1=8
 _tx_data_width2=8
 _tx_data_width3=8
-_tx_fifo0=DISABLED
+_tx_fifo0=ENABLED
 _tx_fifo1=ENABLED
 _tx_fifo2=ENABLED
 _tx_fifo3=ENABLED
@@ -91,7 +91,7 @@ _rx_data_width0=8
 _rx_data_width1=8
 _rx_data_width2=8
 _rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
 _rx_fifo1=ENABLED
 _rx_fifo2=ENABLED
 _rx_fifo3=ENABLED
diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt
index 7ea13c8..5883a95 100644
--- a/source/serdes_sync_downstream.txt
+++ b/source/serdes_sync_downstream.txt
@@ -19,8 +19,8 @@ CH0_RX_DATA_RATE        "FULL"
 CH0_TX_DATA_RATE        "FULL"
 CH0_TX_DATA_WIDTH       "8"
 CH0_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "DISABLED"
-CH0_RX_FIFO        "ENABLED"
+CH0_TX_FIFO       "ENABLED"
+CH0_RX_FIFO        "DISABLED"
 CH0_TDRV      "0"
 #CH0_TX_FICLK_RATE      200
 #CH0_RXREFCLK_RATE        "200"
@@ -52,7 +52,7 @@ CCLMARK                 "7"
 CH0_SSLB                "DISABLED"
 CH0_SPLBPORTS           "DISABLED"
 CH0_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
+INT_ALL                 "ENABLED"
 QD_REFCK2CORE           "DISABLED"
 
 
diff --git a/source/serdes_sync_downstream.vhd b/source/serdes_sync_downstream.vhd
index 36d0a69..7070523 100644
--- a/source/serdes_sync_downstream.vhd
+++ b/source/serdes_sync_downstream.vhd
@@ -1538,7 +1538,6 @@ entity serdes_sync_downstream is
     hdinp_ch0, hdinn_ch0    :   in std_logic;
     hdoutp_ch0, hdoutn_ch0   :   out std_logic;
     sci_sel_ch0    :   in std_logic;
-    rxiclk_ch0    :   in std_logic;
     txiclk_ch0    :   in std_logic;
     rx_full_clk_ch0   :   out std_logic;
     rx_half_clk_ch0   :   out std_logic;
@@ -2199,7 +2198,7 @@ port map  (
   PCIE_PHYSTATUS_0 => open,
   SCISELCH0 => sci_sel_ch0,
   SCIENCH0 => fpsc_vhi,
-  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_RXI_CLK_0 => fpsc_vlo,
   FF_TXI_CLK_0 => txiclk_ch0,
   FF_EBRD_CLK_0 => fpsc_vlo,
   FF_RX_F_CLK_0 => rx_full_clk_ch0,
diff --git a/source/serdes_sync_upstream.ipx b/source/serdes_sync_upstream.ipx
index 1e5e015..0148d22 100644
--- a/source/serdes_sync_upstream.ipx
+++ b/source/serdes_sync_upstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 09 11 07:50:28.463" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 09:44:25.936" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="serdes_sync_upstream.lpc" type="lpc" modified="2013 09 11 07:50:24.000"/>
-		<File name="serdes_sync_upstream.pp" type="pp" modified="2013 09 11 07:50:24.000"/>
-		<File name="serdes_sync_upstream.sym" type="sym" modified="2013 09 11 07:50:24.000"/>
-		<File name="serdes_sync_upstream.tft" type="tft" modified="2013 09 11 07:50:24.000"/>
-		<File name="serdes_sync_upstream.txt" type="pcs_module" modified="2013 09 11 07:50:24.000"/>
-		<File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2013 09 11 07:50:24.000"/>
+		<File name="serdes_sync_upstream.lpc" type="lpc" modified="2013 10 02 09:44:23.000"/>
+		<File name="serdes_sync_upstream.pp" type="pp" modified="2013 10 02 09:44:23.000"/>
+		<File name="serdes_sync_upstream.sym" type="sym" modified="2013 10 02 09:44:24.000"/>
+		<File name="serdes_sync_upstream.tft" type="tft" modified="2013 10 02 09:44:23.000"/>
+		<File name="serdes_sync_upstream.txt" type="pcs_module" modified="2013 10 02 09:44:23.000"/>
+		<File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2013 10 02 09:44:23.000"/>
   </Package>
 </DiamondModule>
diff --git a/source/serdes_sync_upstream.lpc b/source/serdes_sync_upstream.lpc
index 0ea1ddd..6abc82d 100644
--- a/source/serdes_sync_upstream.lpc
+++ b/source/serdes_sync_upstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_upstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=09/11/2013
-Time=07:50:24
+Date=10/02/2013
+Time=09:44:23
 
 [Parameters]
 Verilog=0
diff --git a/source/serdes_sync_upstream.txt b/source/serdes_sync_upstream.txt
index 1c55bd7..5883a95 100644
--- a/source/serdes_sync_upstream.txt
+++ b/source/serdes_sync_upstream.txt
@@ -52,7 +52,7 @@ CCLMARK                 "7"
 CH0_SSLB                "DISABLED"
 CH0_SPLBPORTS           "DISABLED"
 CH0_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
+INT_ALL                 "ENABLED"
 QD_REFCK2CORE           "DISABLED"
 
 
diff --git a/source/soda_calibration_timer.vhd b/source/soda_calibration_timer.vhd
index 658a53f..0f1269f 100644
--- a/source/soda_calibration_timer.vhd
+++ b/source/soda_calibration_timer.vhd
@@ -12,7 +12,7 @@ use work.soda_components.all;
 
 entity soda_calibration_timer is
 	port(
-		SYSCLK						: in	std_logic; -- fabric clock
+		SODACLK						: in	std_logic; -- fabric clock
 		RESET							: in	std_logic; -- synchronous reset
 		CLEAR							: in	std_logic; -- asynchronous reset
 		CLK_EN						: in	std_logic; 
@@ -31,9 +31,9 @@ architecture Behavioral of soda_calibration_timer is
 
 begin
 
-	packet_fsm_proc : process(SYSCLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)
+	packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)
 	begin
-		if rising_edge(SYSCLK) then
+		if rising_edge(SODACLK) then
 			if (RESET='1') then
 				CALIB_VALID_OUT					<= '0';
 				CALIB_TIME_OUT						<= (others => '0');
diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index a378d25..35decf0 100644
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -9,6 +9,8 @@ use work.trb_net16_hub_func.all;
 
 package soda_components is
 
+	constant	c_NOT_IN_SYNC			: std_logic	:= '1';
+	constant	c_IN_SYNC				: std_logic	:= '0';
 	constant	c_HUB_CHILDREN			: natural range 1 to 4 := 2;
 	type		t_HUB_DLM				is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
 	type		t_HUB_DLM_WORD			is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
@@ -42,7 +44,7 @@ package soda_components is
 			CLEAR							: in	std_logic; -- asynchronous reset
 			CLK_EN						: in	std_logic;
 			--Internal Connection
-			LINK_PHASE_IN				: in	std_logic_vector(1 downto 0) := (others => '0');
+			LINK_PHASE_IN				: in	std_logic := '0';
 			SODA_CMD_STROBE_IN		: in	std_logic := '0';	-- 
 			START_OF_SUPERBURST		: in	std_logic := '0';
 			SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
@@ -100,6 +102,9 @@ package soda_components is
 			RX_DLM_IN				: in std_logic;
 			TX_DLM_OUT				: out	std_logic;
 			TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
+			TX_DLM_INIT_OUT		: out	std_logic	:= '0';	--PL!
+			LINK_PHASE_IN			: in	std_logic	:= '0';	--PL!
+
 
 			SODA_DATA_IN			: in	std_logic_vector(31 downto 0) := (others => '0');
 			SODA_DATA_OUT			: out	std_logic_vector(31 downto 0) := (others => '0');
@@ -181,7 +186,7 @@ package soda_components is
 
 	component soda_reply_handler
 		port(
-			SYSCLK						: in	std_logic; -- fabric clock
+			SODACLK						: in	std_logic; -- fabric clock
 			RESET							: in	std_logic; -- synchronous reset
 			CLEAR							: in	std_logic; -- asynchronous reset
 			CLK_EN						: in	std_logic;
@@ -197,7 +202,7 @@ package soda_components is
 
 	component soda_calibration_timer
 		port(
-			SYSCLK						: in	std_logic; -- fabric clock
+			SODACLK						: in	std_logic; -- fabric clock
 			RESET							: in	std_logic; -- synchronous reset
 			CLEAR							: in	std_logic; -- asynchronous reset
 			CLK_EN						: in	std_logic; 
@@ -257,59 +262,59 @@ package soda_components is
 	end component;
 	
 component med_ecp3_sfp_sync_down is
-  generic(
-    SERDES_NUM : integer range 0 to 3 := 0;
---     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
-    IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
-    );
-  port(
-    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    --Internal Connection TX
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic := '0';
-    --Internal Connection RX
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-    MED_DATAREADY_OUT  : out std_logic := '0';
-    MED_READ_IN        : in  std_logic;
-    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
-    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
-    
-    --Sync operation
-    RX_DLM             : out std_logic := '0';
-    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-    TX_DLM             : in  std_logic := '0';
-    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-    
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;  --not used
-    SD_REFCLK_N_IN     : in  std_logic;  --not used
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
-   );
+	generic(
+		SERDES_NUM				: integer range 0 to 3 := 0;
+		IS_SYNC_SLAVE 			: integer := c_NO);       --select slave mode
+	port(
+		CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+		SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+		RESET              : in  std_logic; -- synchronous reset
+		CLEAR              : in  std_logic; -- asynchronous reset
+		--Internal Connection TX
+		MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+		MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+		MED_DATAREADY_IN   : in  std_logic;
+		MED_READ_OUT       : out std_logic := '0';
+		--Internal Connection RX
+		MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+		MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+		MED_DATAREADY_OUT  : out std_logic := '0';
+		MED_READ_IN        : in  std_logic;
+		CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
+		CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+
+		--Sync operation
+		RX_DLM             : out std_logic := '0';
+		RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
+		TX_DLM             : in  std_logic := '0';
+		TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+		TX_DLM_INIT				: in  std_logic := '0'; --PL!
+		LINK_PHASE_OUT			: out std_logic := '0';	--PL!
+
+		--SFP Connection
+		SD_RXD_P_IN        : in  std_logic;
+		SD_RXD_N_IN        : in  std_logic;
+		SD_TXD_P_OUT       : out std_logic;
+		SD_TXD_N_OUT       : out std_logic;
+		SD_REFCLK_P_IN     : in  std_logic;  --not used
+		SD_REFCLK_N_IN     : in  std_logic;  --not used
+		SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+		SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+		SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+		--Control Interface
+		SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ           : in  std_logic := '0';
+		SCI_WRITE          : in  std_logic := '0';
+		SCI_ACK            : out std_logic := '0';
+		SCI_NACK           : out std_logic := '0';
+		-- Status and control port
+		STAT_OP            : out std_logic_vector (15 downto 0);
+		CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
+		STAT_DEBUG         : out std_logic_vector (63 downto 0);
+		CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+	);
 end component;
 
 component med_ecp3_sfp_sync_up is
@@ -341,7 +346,7 @@ component med_ecp3_sfp_sync_up is
     RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
     TX_DLM             : in  std_logic := '0';
     TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-    
+
     --SFP Connection
     SD_RXD_P_IN        : in  std_logic;
     SD_RXD_N_IN        : in  std_logic;
@@ -368,4 +373,38 @@ component med_ecp3_sfp_sync_up is
    );
 end component;
 
+component soda_tx_control
+  port(
+    CLK_200									: in  std_logic;
+    CLK_100									: in  std_logic;
+    RESET_IN								: in  std_logic;
+
+    TX_DATA_IN								: in  std_logic_vector(15 downto 0);
+    TX_PACKET_NUMBER_IN					: in  std_logic_vector(2 downto 0);
+    TX_WRITE_IN							: in  std_logic;
+    TX_READ_OUT							: out std_logic;
+
+    TX_DATA_OUT							: out std_logic_vector( 7 downto 0);
+    TX_K_OUT								: out std_logic;
+
+    REQUEST_RETRANSMIT_IN				: in  std_logic := '0';
+    REQUEST_POSITION_IN					: in  std_logic_vector( 7 downto 0) := (others => '0');
+
+    START_RETRANSMIT_IN					: in  std_logic := '0';
+    START_POSITION_IN					: in  std_logic_vector( 7 downto 0) := (others => '0');
+    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+    TX_DLM_INIT							: in  std_logic := '0';
+    SEND_DLM								: in  std_logic := '0';
+    SEND_DLM_WORD							: in  std_logic_vector( 7 downto 0) := (others => '0');
+    
+    SEND_LINK_RESET_IN					: in  std_logic := '0';
+    TX_ALLOW_IN							: in  std_logic := '0';
+    RX_ALLOW_IN							: in  std_logic := '0';
+	 LINK_PHASE_OUT						: out std_logic := '0';
+
+    DEBUG_OUT								: out std_logic_vector(31 downto 0);
+    STAT_REG_OUT							: out std_logic_vector(31 downto 0)
+    );
+end component;
+
 end package;
diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd
index 3f68c1e..81ff2fc 100644
--- a/source/soda_packet_builder.vhd
+++ b/source/soda_packet_builder.vhd
@@ -16,7 +16,7 @@ entity soda_packet_builder is
 		CLEAR							: in	std_logic; -- asynchronous reset
 		CLK_EN						: in	std_logic; 
 		--Internal Connection
-		LINK_PHASE_IN				: in	std_logic_vector(1 downto 0) := (others => '0');
+		LINK_PHASE_IN				: in	std_logic := '0';	--_vector(1 downto 0) := (others => '0');
 		SODA_CMD_STROBE_IN		: in	std_logic := '0';	-- 
 		START_OF_SUPERBURST		: in	std_logic := '0';
 		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
@@ -49,6 +49,7 @@ architecture Behavioral of soda_packet_builder is
 													c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
 												);
 	signal	packet_state_S				:	packet_state_type := c_IDLE;
+	
 
 begin
 
@@ -72,7 +73,7 @@ begin
 	TX_DLM_OUT					<=	soda_pkt_valid_S;
 	
 	
-	packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)
+	packet_fsm_proc : process(SODACLK)
 	begin
 		if rising_edge(SODACLK) then
 			if (RESET='1') then
@@ -81,142 +82,173 @@ begin
 				case packet_state_S is
 					when c_IDLE	=>
 						if (START_OF_SUPERBURST='1') then
-							if (LINK_PHASE_IN = "00") then
-								packet_state_S	<= c_BST1;
+							if (LINK_PHASE_IN = c_IN_SYNC) then
+								packet_state_S		<= c_BST1;
+								soda_pkt_valid_S	<= '1';
+								soda_pkt_word_S	<= '1' & super_burst_nr_S(30 downto 24);
 							else
-								packet_state_S	<= c_WAIT4BST1;
+								packet_state_S		<= c_WAIT4BST1;
+								soda_pkt_valid_S	<= '0';
 							end if;
 						elsif (soda_cmd_strobe_S='1') then
-							if (LINK_PHASE_IN = "00") then
-								packet_state_S	<= c_CMD1;
+							if (LINK_PHASE_IN = c_IN_SYNC) then
+								packet_state_S		<= c_CMD1;
+								soda_pkt_valid_S	<= '1';
+								soda_pkt_word_S	<= '0' & soda_cmd_word_S(30 downto 24);
 							else
-								packet_state_S	<= c_WAIT4CMD1;
+								packet_state_S		<= c_WAIT4CMD1;
+								soda_pkt_valid_S	<= '0';
 							end if;
 						else
 							packet_state_S	<=	c_IDLE;
+							TIME_CAL_OUT			<= '0';
+							soda_pkt_valid_S		<= '0';
+							soda_pkt_word_S		<= (others=>'0');
 						end if;
 					when c_WAIT4BST1	=>
-						if (LINK_PHASE_IN = "00") then
-							packet_state_S	<= c_BST1;
-						else
-							packet_state_S	<= c_WAIT4BST1;
-						end if;
+						packet_state_S	<= c_BST1;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= '1' & super_burst_nr_S(30 downto 24);
 					when c_BST1	=>
 						packet_state_S	<= c_BST2;
+						soda_pkt_valid_S		<= '0';
 					when c_BST2	=>
 						packet_state_S	<= c_BST3;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= super_burst_nr_S(23 downto 16);
 					when c_BST3	=>
 						packet_state_S	<= c_BST4;
+						soda_pkt_valid_S		<= '0';
 					when c_BST4	=>
 						packet_state_S	<= c_BST5;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= super_burst_nr_S(15 downto 8);
 					when c_BST5	=>
 						packet_state_S	<= c_BST6;
+						soda_pkt_valid_S		<= '0';
 					when c_BST6	=>
 						packet_state_S	<= c_BST7;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= super_burst_nr_S(7 downto 0);
 					when c_BST7	=>
 						packet_state_S	<= c_BST8;
+						soda_pkt_valid_S		<= '0';
 					when c_BST8	=>
 						if (soda_cmd_strobe_S='0') then
 							packet_state_S	<= c_IDLE;
 						else
 							packet_state_S	<= c_CMD1;
 						end if;
+						soda_pkt_valid_S		<= '0';
+						soda_pkt_word_S		<= (others=>'0');
 					when c_WAIT4CMD1	=>
-						if (LINK_PHASE_IN = "00") then
-							packet_state_S	<= c_CMD1;
-						else
-							packet_state_S	<= c_WAIT4CMD1;
-						end if;
+						packet_state_S	<= c_CMD1;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= '0' & soda_cmd_word_S(30 downto 24);
 					when c_CMD1	=>
-							packet_state_S	<= c_CMD2;
+						packet_state_S	<= c_CMD2;
+						soda_pkt_valid_S		<= '0';
 					when c_CMD2	=>
-							packet_state_S	<= c_CMD3;
+						packet_state_S	<= c_CMD3;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= soda_cmd_word_S(23 downto 16);
 					when c_CMD3	=>
-							packet_state_S	<= c_CMD4;
+						packet_state_S	<= c_CMD4;
+						soda_pkt_valid_S		<= '0';
 					when c_CMD4	=>
-							packet_state_S	<= c_CMD5;
+						packet_state_S	<= c_CMD5;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= soda_cmd_word_S(15 downto 8);
 					when c_CMD5	=>
-							packet_state_S	<= c_CMD6;
+						packet_state_S	<= c_CMD6;
+						soda_pkt_valid_S		<= '0';
 					when c_CMD6	=>
-							packet_state_S	<= c_CMD7;
+						packet_state_S	<= c_CMD7;
+						soda_pkt_valid_S		<= '1';
+						soda_pkt_word_S		<= soda_cmd_word_S(7 downto 0);
 					when c_CMD7	=>
 						if (crc_valid_S = '0') then
 							packet_state_S	<= c_ERROR;
 						else
 							packet_state_S	<= c_CMD8;
 						end if;
+						soda_pkt_valid_S		<= '0';
 					when c_CMD8	=>
 						packet_state_S		<= c_IDLE;
+						soda_pkt_valid_S		<= '0';
+						soda_pkt_word_S		<= (others=>'0');
 					when c_ERROR	=>
 						packet_state_S		<= c_IDLE;
+						soda_pkt_valid_S		<= '0';
 					when others	=>
 						packet_state_S		<= c_IDLE;
+						soda_pkt_valid_S		<= '0';
 				end case;
 			end if;
 		end if;
 	end process;
 
-	soda_packet_fill_proc : process(SODACLK, packet_state_S)
-	begin
-		if rising_edge(SODACLK) then
-			case packet_state_S is
-					when c_IDLE	=>
-						TIME_CAL_OUT			<= '0';
-						soda_pkt_valid_S		<= '0';
-						soda_pkt_word_S		<= (others=>'0');
-					when c_WAIT4BST1	=>		-- no need to do anything just yet.
-					when c_BST1	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= '1' & super_burst_nr_S(30 downto 24);
-					when c_BST2	=>
-						soda_pkt_valid_S		<= '0';
-					when c_BST3	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= super_burst_nr_S(23 downto 16);
-					when c_BST4	=>
-						soda_pkt_valid_S		<= '0';
-					when c_BST5	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= super_burst_nr_S(15 downto 8);
-					when c_BST6	=>
-						soda_pkt_valid_S		<= '0';
-					when c_BST7	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= super_burst_nr_S(7 downto 0);
-						EXPECTED_REPLY_OUT	<= super_burst_nr_S(7 downto 0);
-					when c_BST8	=>
-						soda_pkt_valid_S		<= '0';
-					when c_WAIT4CMD1	=>		-- no need to do anything just yet.
-					when c_CMD1	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= '0' & soda_cmd_word_S(30 downto 24);
-					when c_CMD2	=>
-						soda_pkt_valid_S		<= '0';
-					when c_CMD3	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= soda_cmd_word_S(23 downto 16);
-					when c_CMD4	=>
-						soda_pkt_valid_S		<= '0';
-					when c_CMD5	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= soda_cmd_word_S(15 downto 8);
-					when c_CMD6	=>
-						soda_pkt_valid_S		<= '0';
-					when c_CMD7	=>
-						soda_pkt_valid_S		<= '1';
-						soda_pkt_word_S		<= crc_out_S;
-						EXPECTED_REPLY_OUT	<= crc_out_S;
-						TIME_CAL_OUT			<= '1';
-					when c_CMD8	=>
-						TIME_CAL_OUT			<= '0';
-						soda_pkt_valid_S		<= '0';
-					when others	=>
-						TIME_CAL_OUT			<= '0';
-						soda_pkt_valid_S		<= '0';
-						soda_pkt_word_S		<= (others=>'0');
-			end case;		
-		end if;
-	end process;
+	--soda_packet_fill_proc : process(SODACLK, packet_state_S)
+	--begin
+		--if rising_edge(SODACLK) then
+			--case packet_state_S is
+					--when c_IDLE	=>
+						--TIME_CAL_OUT			<= '0';
+						--soda_pkt_valid_S		<= '0';
+						--soda_pkt_word_S		<= (others=>'0');
+					--when c_WAIT4BST1	=>		-- no need to do anything just yet.
+					--when c_BST1	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= '1' & super_burst_nr_S(30 downto 24);
+					--when c_BST2	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_BST3	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= super_burst_nr_S(23 downto 16);
+					--when c_BST4	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_BST5	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= super_burst_nr_S(15 downto 8);
+					--when c_BST6	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_BST7	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= super_burst_nr_S(7 downto 0);
+						--EXPECTED_REPLY_OUT	<= super_burst_nr_S(7 downto 0);
+					--when c_BST8	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_WAIT4CMD1	=>		-- no need to do anything just yet.
+					--when c_CMD1	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= '0' & soda_cmd_word_S(30 downto 24);
+					--when c_CMD2	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_CMD3	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= soda_cmd_word_S(23 downto 16);
+					--when c_CMD4	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_CMD5	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= soda_cmd_word_S(15 downto 8);
+					--when c_CMD6	=>
+						--soda_pkt_valid_S		<= '0';
+					--when c_CMD7	=>
+						--soda_pkt_valid_S		<= '1';
+						--soda_pkt_word_S		<= crc_out_S;
+						--EXPECTED_REPLY_OUT	<= crc_out_S;
+						--TIME_CAL_OUT			<= '1';
+					--when c_CMD8	=>
+						--TIME_CAL_OUT			<= '0';
+						--soda_pkt_valid_S		<= '0';
+					--when others	=>
+						--TIME_CAL_OUT			<= '0';
+						--soda_pkt_valid_S		<= '0';
+						--soda_pkt_word_S		<= (others=>'0');
+			--end case;		
+		--end if;
+	--end process;
 
 
 	crc_gen_proc : process(SODACLK, packet_state_S)
diff --git a/source/soda_reply_handler.vhd b/source/soda_reply_handler.vhd
index 3c341ae..5324d90 100644
--- a/source/soda_reply_handler.vhd
+++ b/source/soda_reply_handler.vhd
@@ -10,7 +10,7 @@ use work.soda_components.all;
 
 entity soda_reply_handler is
 	port(
-		SYSCLK						: in	std_logic; -- fabric clock
+		SODACLK						: in	std_logic; -- fabric clock
 		RESET							: in	std_logic; -- synchronous reset
 		CLEAR							: in	std_logic; -- asynchronous reset
 		CLK_EN						: in	std_logic;
@@ -30,9 +30,9 @@ architecture Behavioral of soda_reply_handler is
 
 begin
 
-	reply_fsm_proc : process(SYSCLK)
+	reply_fsm_proc : process(SODACLK)
 	begin
-		if rising_edge(SYSCLK) then
+		if rising_edge(SODACLK) then
 			if (RESET='1') then
 				REPLY_VALID_OUT	<= '0';
 				REPLY_OK_OUT		<= '0';
diff --git a/source/soda_source.vhd b/source/soda_source.vhd
index ded23a0..0bc1705 100644
--- a/source/soda_source.vhd
+++ b/source/soda_source.vhd
@@ -20,9 +20,11 @@ entity soda_source is
 		SODA_BURST_PULSE_IN	: in	std_logic := '0';	-- 
 
 		RX_DLM_WORD_IN			: in	std_logic_vector(7 downto 0) := (others => '0');
-		RX_DLM_IN				: in std_logic;
+		RX_DLM_IN				: in	std_logic;
 		TX_DLM_OUT				: out	std_logic;
-		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
+		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
+		TX_DLM_INIT_OUT		: out	std_logic	:= '0';	--PL!
+		LINK_PHASE_IN			: in	std_logic	:= '0';	--PL!
 
 		SODA_DATA_IN			: in	std_logic_vector(31 downto 0) := (others => '0');
 		SODA_DATA_OUT			: out	std_logic_vector(31 downto 0) := (others => '0');
@@ -37,7 +39,6 @@ end soda_source;
 architecture Behavioral of soda_source is
 
 	--SODA
-	signal link_phase_S					: std_logic_vector(1 downto 0) := (others => '0');
 	signal soda_cmd_word_S				: std_logic_vector(30 downto 0)	:= (others => '0');
 	signal soda_cmd_strobe_S			: std_logic := '0';
 	signal soda_cmd_strobe_sodaclk_S	: std_logic := '0';	
@@ -93,7 +94,7 @@ begin
 			CLEAR						=>	'0',
 			CLK_EN					=> CLK_EN,
 			--Internal Connection
-			LINK_PHASE_IN			=>	link_phase_S,
+			LINK_PHASE_IN			=>	LINK_PHASE_IN,		--link_phase_S,	PL!
 			SODA_CMD_STROBE_IN	=> soda_cmd_strobe_sodaclk_S,
 			START_OF_SUPERBURST	=> start_of_superburst_S,
 			SUPER_BURST_NR_IN		=> super_burst_nr_S,
@@ -106,7 +107,7 @@ begin
 
 	src_reply_handler : soda_reply_handler
 		port map(
-			SYSCLK						=>	SODACLK,
+			SODACLK						=>	SODACLK,
 			RESET							=> RESET,
 			CLEAR							=>	'0',
 			CLK_EN						=>	'1',
@@ -120,7 +121,7 @@ begin
 
 	src_calibration_timer : soda_calibration_timer
 		port map(
-			SYSCLK						=>	SODACLK,
+			SODACLK						=>	SODACLK,
 			RESET							=> RESET,
 			CLEAR							=>	'0',
 			CLK_EN						=>	'1',
@@ -141,21 +142,44 @@ begin
 			end if;
 		end if;
 	end process;
+
+
+
 -----------------------------------------------------------
---	Phase fsm for 16-bit transmissions							--
+--	TX_DLM_INIT for media-interface transmissions			--
 -----------------------------------------------------------
-	phase_fsm_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if( RESET = '1' ) then
-				link_phase_S	<= (0 => '1', others => '0');
-			elsif (link_phase_S < 1) then
-				link_phase_S	<= link_phase_S + 1;
-			else
-				link_phase_S <= (others => '0');
-			end if;
-		end if;
+	tx_dlm_init_proc : process (SODACLK, start_of_superburst_S, soda_cmd_strobe_S)
+	begin
+		if( RESET = '1' ) then 
+			TX_DLM_INIT_OUT	<= '0';
+		elsif ((start_of_superburst_S='1' or soda_cmd_strobe_S='1') and LINK_PHASE_IN=c_IN_SYNC) then
+			TX_DLM_INIT_OUT	<=	'1';
+		elsif rising_edge(SODACLK) then
+			if (start_of_superburst_S='1' or soda_cmd_strobe_S='1') then
+				TX_DLM_INIT_OUT	<=	'1';
+			else
+				TX_DLM_INIT_OUT	<=	'0';
+			end if;
+		end if;
 	end process;
+
+	
+
+-----------------------------------------------------------
+--	Phase fsm for 16-bit transmissions							--
+-----------------------------------------------------------
+--	phase_fsm_proc : process(SODACLK)
+--	begin
+--		if rising_edge(SODACLK) then
+--			if( RESET = '1' ) then
+--				link_phase_S	<= '0';		--	(0 => '1', others => '0');
+--			elsif (link_phase_S='0') then
+--				link_phase_S	<= '1';
+--			else
+--				link_phase_S 	<= '0';	--(others => '0');
+--			end if;
+--		end if;
+--	end process;
 
 ---------------------------------------------------------
 -- RegIO Statemachine
diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd
index d6c282f..2d3d483 100644
--- a/source/trb3_periph_sodaclient.vhd
+++ b/source/trb3_periph_sodaclient.vhd
@@ -576,14 +576,14 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
---	LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
---	LED_YELLOW <= '1';
---	LED_GREEN  <= not med_stat_op(9);
---	LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
-	LED_ORANGE <= soda_leds(0);
-	LED_YELLOW <= soda_leds(1);
-	LED_GREEN  <= soda_leds(2);
-	LED_RED    <= soda_leds(3);
+	LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+	LED_YELLOW <= soda_leds(0);	--'1';
+	LED_GREEN  <= not med_stat_op(9);
+	LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
+--	LED_ORANGE <= soda_leds(0);
+--	LED_YELLOW <= soda_leds(1);
+--	LED_GREEN  <= soda_leds(2);
+--	LED_RED    <= soda_leds(3);
 
 ---------------------------------------------------------------------------
 -- DEBUG
diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd
index ab2a589..e5795f5 100644
--- a/source/trb3_periph_sodasource.vhd
+++ b/source/trb3_periph_sodasource.vhd
@@ -196,13 +196,13 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
 
 	--SODA
 	signal soda_ack      : std_logic;
---	signal soda_nack     : std_logic;
 	signal soda_write    : std_logic;
 	signal soda_read     : std_logic;
 	signal soda_data_in  : std_logic_vector(31 downto 0);
 	signal soda_data_out : std_logic_vector(31 downto 0);
 	signal soda_addr     : std_logic_vector(3 downto 0);  
 	signal soda_leds     : std_logic_vector(3 downto 0);  
+
 
 	--TDC
   signal hit_in_i : std_logic_vector(63 downto 0);
@@ -213,6 +213,8 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal rx_dlm_i          : std_logic;
   signal tx_dlm_word       : std_logic_vector(7 downto 0);
   signal rx_dlm_word       : std_logic_vector(7 downto 0);
+	signal tx_dlm_init_S			: std_logic;	--PL!
+	signal link_phase_S			: std_logic;	--PL!
 
 	--SODA
 	signal SOB_S							: std_logic := '0';
@@ -537,7 +539,9 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down
     RX_DLM             => rx_dlm_i,
     RX_DLM_WORD        => rx_dlm_word,
     TX_DLM             => tx_dlm_i,
-    TX_DLM_WORD        => tx_dlm_word,
+    TX_DLM_WORD        => tx_dlm_word,
+	 TX_DLM_INIT			=> tx_dlm_init_S,			--PL!
+	 LINK_PHASE_OUT		=>	link_phase_S,		--PL!
     --SFP Connection
     SD_RXD_P_IN        => SERDES_ADDON_RX(0),
     SD_RXD_N_IN        => SERDES_ADDON_RX(1),
@@ -591,7 +595,8 @@ THE_SODA_SOURCE : soda_source
 		RX_DLM_IN				=> rx_dlm_i,
 		TX_DLM_OUT				=> tx_dlm_i, 
 		TX_DLM_WORD_OUT		=> tx_dlm_word,
-
+		TX_DLM_INIT_OUT		=> tx_dlm_init_S,
+		LINK_PHASE_IN			=> link_phase_S,
 		SODA_DATA_IN			=> soda_data_in,
 		SODA_DATA_OUT			=> soda_data_out,
 		SODA_ADDR_IN			=> soda_addr,
@@ -606,14 +611,14 @@ THE_SODA_SOURCE : soda_source
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
---	LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
---	LED_YELLOW <= '1';
---	LED_GREEN  <= not med_stat_op(9);
---	LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
-	LED_ORANGE <= soda_leds(0);
-	LED_YELLOW <= soda_leds(1);
-	LED_GREEN  <= soda_leds(2);
-	LED_RED    <= soda_leds(3);
+	LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+	LED_YELLOW <= soda_leds(0);	--'1';
+	LED_GREEN  <= not med_stat_op(9);
+	LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
+--	LED_ORANGE <= soda_leds(0);
+--	LED_YELLOW <= soda_leds(1);
+--	LED_GREEN  <= soda_leds(2);
+--	LED_RED    <= soda_leds(3);
 
 ---------------------------------------------------------------------------
 -- Test Connector